ZeroG Wireless, Inc., Delaware Corporation Patent applications |
Patent application number | Title | Published |
20090119444 | MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING - The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block | 05-07-2009 |
20090054004 | Biasing for Stacked Circuit Configurations - A biasing scheme for compensating for a difference in biasing currents between a first circuit element ( | 02-26-2009 |
20080278243 | Edge alignment for frequency synthesizers - A frequency synthesizer ( | 11-13-2008 |