| Zentrum Mikroelektronik Dresden AG Patent applications |
| Patent application number | Title | Published |
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| 20120112947 | WIDE RANGE CHARGE BALANCING CAPACITIVE-TO-DIGITAL CONVERTER - A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor. | 05-10-2012 |
| 20120098557 | CAPACITIVE INPUT TEST METHOD - Method and system are provided for evaluating linearity of a capacitive-to-digital converter (CDC) of a capacitive sensor integrated circuit chip. The evaluating employs multiple test capacitors, which may be on-chip with the CDC, and includes: obtaining capacitance values for the multiple test capacitors and parasitic capacitances of a first input A and a second input B to the capacitive-to-digital converter; applying the multiple test capacitors in multiple permutations to the first input A and the second input B, and for each of at least some permutations, determining an error between an expected output of the CDC using the obtained capacitance values and an actual measured output of the CDC; and determining linearity error for the CDC using the determined errors for the permutations of applying the multiple test capacitors to the first input A and the second input B of the CDC. | 04-26-2012 |
| 20120013391 | ADAPTIVE BOOTSTRAP CIRCUIT FOR CONTROLLING CMOS SWITCH(ES) - An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type. | 01-19-2012 |
| 20110137593 | Method and Arrangement for Digital Measuring a Capacitive Sensor - An arrangement for digital measuring a capacitive sensor is provided with a charge balance frequency converter having an operational amplifier with an inverting input, a noninverting input and an output. Between the output and the inverting input an integrating capacitor is connected, and the noninverting input is connected with a reference potential. The arrangement provides a simple switched capacitor architecture for measuring the sensor capacitance, which tolerates grounded sensor capacitors, and which is not affected by the shunt resistance. The value of the shunt resistance is determined at the same time. The arrangement makes use of a two frequency measurement of the capacitor resistance combination by using the charge balancing procedure followed by a calculation based on the results of two conversions and the ratio of the clock frequencies of the first and second conversion. | 06-09-2011 |
| 20090302907 | CIRCUIT ARRANGEMENT FOR PRODUCING A DEFINED OUTPUT SIGNAL - A circuit arrangement for producing a defined output signal in CMOS integrated circuit is provided in which the output of a sensor signal conditioning circuit is connected to the drain terminal of a first N channel depletion transistor, to a source terminal of a second N channel depletion transistor and to the output (OUT) of an integrated CMOS circuit. The gate terminals of the first and second N channel depletion transistors are connected to the output (VP) of a control circuit and the first terminal of a discharge resistance. The second terminal of the discharge resistance and the source terminal of the first N channel depletion transistor are connected to a potential VSS, and the drain terminal of the second N channel depletion transistor is connected to a potential VDD. | 12-10-2009 |
| 20090201969 | CIRCUIT ARRANGEMENT TO ADJUST AND CALIBRATE A MEMS-SENSOR DEVICE FOR FLOW MEASUREMENT OF GASES OR LIQUIDS - Circuitry is disclosed for the calibration of heating element and ambient temperature sensors, comprising: a) an amplifier having positive and negative inputs, and an output; b) one or more heating MOS transistors selectably coupled in parallel and having 1) a heating transistor drain coupled to the positive input of the amplifier; 2) a heating transistor source configured to receive a supply voltage; and 3) a heating transistor gate coupled to the amplifier output; c) one or more ambient MOS transistors selectably coupled in parallel and having 1) an ambient transistor drain, 2) an ambient transistor gate coupled to the amplifier output; and 3) an ambient transistor source configured to receive the supply voltage; d) a temperature difference resistance configured: 1) to be coupled at least partially between an ambient connection and the ambient transistor drain; and 2) to be coupled at least partially between the ambient connection and the negative input of the amplifier. | 08-13-2009 |
| 20090160257 | METHOD FOR AUTOMATIC OPERATING VOLTAGE DETECTION - A method for automatic operating voltage detection, in which one internal supply voltage (vdd) is selected from at least two different external supply voltages, with a first external voltage supply (VDDA) being applied permanently, is based on the object of reducing the circuit complexity for automatic operating voltage detection, the operating current caused by the selection arrangement and the required chip area, in which case the voltage ratios between the two different external supply voltages can be as required. This object is achieved in that a reference voltage (Vref) and a voltage (VDDreg) is produced from the first external supply voltage (VDDA), the reference voltage (Vref) is compared with a second external supply voltage (VDDIO), and either the voltage (VDDreg) produced from the first external supply voltage (VDDA) or the second external supply voltage (VVDIO) is released as an internal supply voltage (vdd), depending on the comparison. | 06-25-2009 |
| 20090153238 | METHOD AND SYSTEM FOR REDUCING A DYNAMIC OFFSET DURING THE PROCESSING OF ASYMMETRIC SIGNAL STRINGS - The invention relates to a method and a system for reducing a dynamic offset during the processing of asymmetric signal strings. The aim of the invention is to provide a method and a system for reducing a dynamic offset which allows to reduce any disturbing influence on subsequent process steps. According to the invention, this aim is achieved by a discharge of the capacity in every no-pulse period by a value depending on the value of the amplitude of the voltage of the high-pass structure on the input side. | 06-18-2009 |
