Zeno Semiconductor, Inc. Patent applications |
Patent application number | Title | Published |
20140328128 | NAND String Utilizing Floating Body Memory Cell - NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described. | 11-06-2014 |
20140307501 | SCALABLE FLOATING BODY MEMORY CELL FOR MEMORY COMPILERS AND METHOD OF USING FLOATING BODY MEMORIES WITH MEMORY COMPILERS - A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided. | 10-16-2014 |
20140254259 | Dual-Port Semiconductor Memory and First In First Out (FIFO) Memory Having Electrically Floating Body Transistor - Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device. | 09-11-2014 |
20140042503 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 02-13-2014 |
20130094280 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Comprising Resistive Change Material and Method of Operating - A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating. | 04-18-2013 |
20120081976 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 04-05-2012 |
20120081940 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell is formed in a semiconductor. The semiconductor memory cell includes: a floating body region defining at least a portion of a surface of the semiconductor memory cell, the floating body region having a first conductivity type; and a buried region located within the semiconductor memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type. | 04-05-2012 |
20120014180 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted. | 01-19-2012 |