| YIELD MICROELECTRONICS CORP. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120040504 | METHOD FOR INTEGRATING DRAM AND NVM - The present invention discloses a method for integrating DRAM and NVM, which comprises steps: sequentially forming on a portion of surface of a DRAM semiconductor substrate a first gate insulation layer and a first gate layer functioning as a floating gate; and implanting ion into regions of the semiconductor substrate, which are at two sides of the first gate insulation layer, to form two heavily-doped areas that are adjacent to the first gate insulation layer and respectively function as a drain and a source; respectively forming over the first gate layer a second gate insulation layer and a second gate layer functioning as a control gate. The present invention not only increases the transmission speed but also reduces the power consumption, the fabrication cost and the package cost. | 02-16-2012 |
| 20120039131 | LOW-VOLTAGE EEPROM ARRAY - A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines. | 02-16-2012 |
| 20120039129 | COST SAVING ELECTRICALLY-ERASABLE-PROGRAMMABLE READ-ONLY MEMORY (EEPROM) ARRAY - A cost saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line. | 02-16-2012 |
| 20110286281 | REFERENCE CURRENT GENERATOR USED FOR PROGRAMMING AND ERASING OF NON-VOLATILE MEMORY - A reference current generator used for programming and erasing of the non-volatile memory. Wherein, a self-biasing reference generator is used to generate a first reference voltage of a negative temperature coefficient and a second reference voltage of a positive temperature coefficient. A voltage converter receives said first reference voltage and generate a third reference voltage having its temperature coefficient less than that of said first reference voltage, and said second reference voltage and said third reference voltage are input to a reference current source, such that said reference current source generates a reference current of low temperature sensitivity. Through said reference current source, said second reference voltage and said third reference voltage are used to compensate said negative temperature coefficient of a threshold voltage of a transistor, thus reducing difference of times required for programming and erasure under various operation temperatures. | 11-24-2011 |
| 20110182124 | NON-VOLATILE MEMORY LOW VOLTAGE AND HIGH SPEED ERASURE METHOD - A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory. | 07-28-2011 |
