| XMOS Limited Patent applications |
| Patent application number | Title | Published |
|---|
| 20110131559 | COMPILING AND LINKING - A method of generating a computer program, the method comprising: independently compiling a plurality of source code modules to generate a plurality of respective object modules comprising a plurality of respective threads explicitly designated by a user to be executed in parallel; in each of the object modules, inserting at least one symbol indicative of a property of the object module's thread potentially conflicting with a corresponding property of a thread of another of said object module as a result of parallel execution of those threads; executing a linker to perform a linking process on said object modules, the linking process comprising: assessing the symbols in conjunction with one another to determine whether a conflict exists between the threads of two or more of the respective object modules; and linking the object modules to generate a computer program in which said threads are executable in parallel, wherein the linking is performed in dependence on said assessment. | 06-02-2011 |
| 20110131558 | LINK-TIME RESOURCE ALLOCATION FOR A MULTI-THREADED PROCESSOR ARCHITECTURE - A method comprising: independently compiling a plurality of modules of source code to generate a plurality of respective object modules comprising a plurality of respective parallel threads explicitly designated by a user to be executed in parallel on a target platform; in each of the object modules, inserting at least one symbol indicative of a usage of a resource of the target platform associated with the respective thread; executing a linker to perform a linking process for linking the object modules, wherein the linking process comprises assessing the symbols in conjunction with one another, and based on the assessment generating an indication relating to a usage of the resource required for execution of the threads in parallel. | 06-02-2011 |
| 20110131396 | TIMING ANALYSIS - One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the execution unit and arranged to generate a periodically updated counter value during execution. The execution unit comprises logic configured to identify an opcode representing a trap-if-late instruction in said sequence, and in response to execute the trap-if-late instruction by comparing a target value to the counter value and generating an exception on condition that the counter value represents a time that is late relative to said target value. Another aspect provides a compiler for inserting trap-if-late instructions based on timing constraints in higher-level code. | 06-02-2011 |
| 20080229310 | Processor instruction set - The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread. | 09-18-2008 |
