| Winbond Electronics Corporation Patent applications |
| Patent application number | Title | Published |
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| 20100049948 | Serial flash semiconductor memory - A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories. | 02-25-2010 |
| 20090292876 | In-System Programming to Switch Memory Access from One Area to Another in Memory Cards - In-system programming to switch memory access from one area to another in memory cards is disclosed. A command to access a first area of a memory card is received. Access is switched from the first area of the memory card to a second area of the memory card if specified data follows the received command allowing for the memory access switch. | 11-26-2009 |
| 20090210734 | WAKEUP OF A NON-POWERED UNIVERSAL SERIAL BUS - Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power. | 08-20-2009 |
| 20090110213 | PROGRAMMABLE INTEGRATED MICROPHONE INTERFACE CIRCUIT - An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated circuit includes a bias circuit, an amplifier circuit, and two feedback circuits. The bias circuit provides a microphone bias signal to the microphone and provides a sensed microphone signal. The amplifier circuit includes a first input, a second input, and an output. The first input is configured to receive the sensed microphone signal, a first feedback signal, and a second feedback signal. The second input is configured to receive a first reference signal. The feedback circuits are in communication with the output and the first input of the amplifier circuit. In a specific embodiment, the first feedback circuit includes an RC circuit and the second feedback circuit includes an integrator. | 04-30-2009 |
| 20090046827 | Time interval measurement for capacitive detection - Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area. | 02-19-2009 |
| 20090045823 | Power efficient capacitive detection - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area. | 02-19-2009 |
| 20090043916 | Handshake Free Sharing in a Computer Architecture - A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit. | 02-12-2009 |
| 20080310655 | PROGRAMMABLE INTEGRATED MICROPHONE INTERFACE CIRCUIT - An integrated circuit for providing programmable microphone interface includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. In an embodiment, the integrated circuit includes a bias circuit, an amplifier circuit and two feedback circuits. The amplifier circuit includes a first input, a second input, and an output. The first input receives either the input signal or a feedback signal, depending upon mode control signals. The second input receives either the feedback signal or the input signal depending upon the mode control signals. The first feedback circuit is in communication with the output and the first input of the amplifier and includes a first resistor and a first capacitor connected in parallel. The second feedback circuit includes an integrator circuit and provides the feedback signal. The mode control signals can be set in a programmable mode control register. | 12-18-2008 |
| 20080310616 | METHOD AND SYSTEM FOR SUBSCRIBER LINE INTERFACE CIRCUIT - A subscriber line interface circuit apparatus includes a linefeed circuit and a subscriber line control circuit (SLCC). In an embodiment, the linefeed circuit includes a signal conversion circuit which provides a differential mode signal and a common mode signal in response to at least a tip signal and a ring signal from the subscriber loop. The linefeed circuit includes a tip control circuit and a ring control circuit. In an embodiment, the SLCC is provided in a single integrated circuit chip and is coupled to the linefeed circuit which isolates the SLCC from the tip or ring signals. The SLCC includes a first and a second differential mode inputs for receiving the differential mode signal, and a common-mode input for receiving the common-mode signal. In an embodiment, the SLCC also provides various tip control signals and ring control signals to the tip control circuit and the ring control circuit, respectively. | 12-18-2008 |
| 20080250252 | Systems and methods for bios processing - Methods and systems for Basic Input/Output System BIOS processing such as hashing are disclosed. In one embodiment, there is a direct interface between a security module and a non-volatile memory storing the BIOS in a computing system so that the security module may directly access the BIOS without using the central processing unit CPU as an intermediary. In one embodiment, the security module is powered by standby power and therefore can begin BIOS processing even if the computing system has not yet been turned on. | 10-09-2008 |
