| Winbond Electronics Corp. Patent applications |
| Patent application number | Title | Published |
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| 20120089773 | DYNAMIC RANDOM ACCESS MEMORY UNIT AND DATA REFRESHING METHOD THEREOF - A dynamic random access memory (DRAM) unit and a data refreshing method thereof are provided. The DRAM unit includes a memory array, a refresh address module, and a refresh control module. The memory array includes multiple memory cells. The refresh address module produces a refresh word line address cyclically during a refresh mode. The refresh control module coupled to the memory array and the refresh address module obtains a start word line address and a stop word line address corresponding to the start word line address to form a memory word line address interval. Then, the refresh control module determines that the refresh word line address is within the memory word line address interval to execute a data charging operation to the memory cells corresponding to the refresh word line address, or stop the data charging operation otherwise, so as to reduce power consumption during the refresh mode. | 04-12-2012 |
| 20120086500 | FUSE DETECTING APPARATUS - A fuse detecting apparatus including a detector, a calibrator and a logical operating unit is disclosed. The detector includes a detecting switch module and a detecting latch. The detecting switch module generates an initial detecting result according to a first and a second control signals and a status of the fuse. The detecting latch stores a voltage level of the initial detecting result or maintains its originally stored voltage level according to the initial detecting result for generating a pre-calibrating detecting signal. The calibrator includes a calibrating switch module and a calibrating latch. The calibrating switch module generates a calibrating result according to the first and the second control signals. The calibrating latch stores the calibrating result and generates a calibrating signal accordingly. The logical operating unit generates a calibrated detecting signal according to the pre-calibrating detecting signal and the calibrating signal. | 04-12-2012 |
| 20110279102 | CONTROL CIRCUIT OF CHARGE PUMP CIRCUIT - A control circuit of a charge pump circuit is disclosed, which includes a ring oscillator and a load status detection unit. The ring oscillator herein is for producing a clock signal and adjusting the frequency of the clock signal according to a first control signal, and stopping generating the clock signal according to an adjustment signal. The load status detection unit is for producing the first control signal and determining a time point to enable the first control signal according to the voltage drop variation of an output voltage of the charge pump circuit and the adjustment signal, wherein the pulse width of the adjustment signal gets narrower with a smaller drop amplitude of the output voltage value. | 11-17-2011 |
| 20110201170 | METHOD OF FABRICATING MEMORY - A method of fabricating a memory is provided. A substrate comprising a memory region and a periphery region is provided. A plurality of gates is formed on the substrate and a first spacer is formed on a sidewall of each gate, where a plurality of openings is formed between the gates in the memory region. A first material layer formed on the substrate in the memory region covers the gates in the memory region and fills the openings. A process is performed to the periphery region. The first material layer is partially removed to form a first pattern in each opening respectively. A second material layer formed on the substrate covers the memory region and the periphery region to expose the first patterns. The first patterns are removed to form a plurality of contact openings in the second material layer. The contact plugs are formed in the contact openings. | 08-18-2011 |
| 20110053338 | FLASH MEMORY AND METHOD OF FABRICATING THE SAME - In a method of fabricating a flash memory, a substrate with isolation structures formed therein and a dielectric layer and a floating gate formed thereon between isolation structures is provided. A mask layer is formed on the substrate, covering the isolation structures in a periphery region and the isolation structure in a cell region adjacent to the periphery region. The isolation structures in the cell region not covered by the mask layer are partially removed. Therefore, a first height difference is between surfaces of the isolation structures in the periphery region and a surface of the dielectric layer, and between a surface of the isolation structure in the cell region adjacent to the periphery region and the surface of the dielectric layer. A second height difference smaller than the first height difference is between surfaces of other isolation structures in the cell region and the surface of the dielectric layer. | 03-03-2011 |
| 20100315877 | DATA SENSING MODULE AND SENSING CIRCUIT FOR FLASH MEMORY - A sensing circuit for a flash memory is provided. The sensing circuit includes a first transistor, a detector, and a charge circuit. A drain of the first transistor is coupled to a bias, a gate thereof receives an inverted signal, and a source thereof receives a data. In addition, the drain of the first transistor is further coupled to the detector. Therefore, the detector detects a voltage of the drain of the first transistor. When the voltage of the drain is lower than a threshold voltage, the detector enables a control signal. The charge circuit charges the source of the first transistor when the control signal is enabled, until the voltage of the drain of the first transistor reaches the threshold voltage. | 12-16-2010 |
| 20100283146 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure. | 11-11-2010 |
| 20100265774 | METHOD FOR DETERMINING NATIVE THRESHOLD VOLTAGE OF NONVOLATILE MEMORY - A method for determining native threshold voltage of nonvolatile memory includes following steps. A memory cell including a control gate, a charge storage layer, a source region, and a drain region is provided. A programming operation is performed on the memory cell by using F-N tunneling effect to obtain a programming curve of time versus threshold voltage. In the programming operation, a positive voltage is applied to the control gate. An erase operation is performed on the memory cell by using F-N tunneling effect to obtain an erasure curve of time versus threshold voltage. In the erase operation, a negative voltage is applied to the control gate. The absolute values of the positive voltage and the negative voltage are the same. The native threshold voltage of memory cell is determined from the cross point of the programming curve and the erasure curve. | 10-21-2010 |
| 20100213432 | PHASE CHANGE MEMORY DEVICE AND FABRICATION THEREOF - A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer. | 08-26-2010 |
| 20100202232 | REFRESHING METHOD - A refreshing method suitable for a memory device is provided which includes the following steps. A sleep mode is set and the memory device cannot be read and programmed in the sleep mode. A first and a second memory cell arrays are sequentially auto-refreshed, and the steps for auto-refreshing each of the first and the second memory cell arrays individually include: during an equalization period, switching the potential of a sense line pair, a first bit line pair and a second bit line pair to a reference voltage wherein the sense line pair is not coupled to the second bit line pair, and during a refreshing period, adjusting the potential of the first and the second bit line pairs according to a refresh sequence of the first and the second memory cell arrays, thereby coupling the sense line pair to one of the first and the second bit line pairs. | 08-12-2010 |
| 20100165708 | MEMORY CONTROLLER AND DECODER - A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced. | 07-01-2010 |
| 20100163828 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer. | 07-01-2010 |
| 20100117050 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 05-13-2010 |
| 20100007353 | GROUP OF CIRCUITS AND TESTING METHOD THEREOF AND TESTING MACHINE THEREOF - A Group of circuits and a testing method thereof and a testing machine thereof are provided. In the testing method, a first voltage of a first circuit is adjusted to be a second voltage according to a first adjusting signal, wherein the second voltage is closer to a standard voltage compared to the first voltage. Further, a third voltage of a second circuit is adjusted to be a forth voltage according to a second adjusting signal, and the forth voltage is closer to the standard voltage compared to the third voltage. In addition, a margin range of the second voltage and a margin range of the forth voltage are adjusted together according to a margin adjusting signal. Thereby, time required for testing the first circuit and the second circuit can be decreased, so as to lower the cost. | 01-14-2010 |
| 20100006814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer. | 01-14-2010 |
| 20090296450 | Memory And Writing Method Thereof - A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level. | 12-03-2009 |
| 20090294995 | OVERLAY MARK - An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer. | 12-03-2009 |
| 20090294750 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively. | 12-03-2009 |
| 20090267240 | METHOD OF MANUFACTURING AN OVERLAY MARK - A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures. | 10-29-2009 |
| 20090257484 | METHOD FOR AUDIO-VIDEO ENCODING AND APPARATUS FOR MULTIMEDIA STORAGE - The invention relates a method for audio-video encoding and an apparatus for multimedia storage. First, a video chunk and an audio chunk are read from a audio-video file. Then the video chunk is divided into a plurality of video blocks, wherein size of each video block at least equals to the size of one unit frame. The audio chunk is divided into a plurality of audio blocks. Finally, according to a playing sequence, at least one audio block is employed between each two video blocks. | 10-15-2009 |
| 20090250691 | PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME - A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate. | 10-08-2009 |
| 20090231940 | MEMORY AND VOLTAGE MONITORING DEVICE THEREOF - A memory and a voltage monitoring device thereof are provided. the voltage monitoring device of the memory includes a system voltage detector, a charge pump circuit and a data output unit. The system voltage detector is coupled to the charge pump circuit and the data output unit for detecting a system voltage and thereby producing control signals. The charge pump circuit can produce a word line voltage according to the above-mentioned control signals. The data output unit decides outputting the above-mentioned control signals or the output data of the memory according to a special command, wherein the control signals correspond to the word line voltages. Therefore, the control signals and the word line voltages may be easily monitored. | 09-17-2009 |
| 20090191367 | MEMORY DEVICES, STYLUS-SHAPED STRUCTURES, ELECTRONIC APPARATUSES, AND METHODS FOR FABRICATING THE SAME - An exemplary hollow stylus-shaped structure is disclosed, including a hollow column spacer formed over a base layer and a hollow cone spacer stacked over the hollow column spacer, wherein the hollow cone spacer, the hollow column spacer, and the base layer form a space, and sidewalls of the hollow cone spacer and the hollow column spacer are made of silicon-containing organic or inorganic materials. | 07-30-2009 |
| 20090189142 | Phase-Change Memory - A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. | 07-30-2009 |
| 20090189140 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal. | 07-30-2009 |
| 20090174470 | LATCH-UP PROTECTION DEVICE - A latch-up protection device is provided. The latch-up protection device includes a first transistor, a detection module, and a processing module. The first transistor includes a first source/drain coupled to a pad, a body and a second source/drain coupled to a first voltage, and a gate. The detection module is adapted for detecting a terminal voltage between the first source/drain and the second source/drain of the first transistor, and generating a first signal when the terminal voltage is greater than a trigger voltage. The processing module is coupled between the detection module and the gate of the first transistor, for conducting a logic processing to the first signal, and generating an enable signal to the gate of the first transistor to conduct the first transistor. | 07-09-2009 |
| 20090169100 | MOTION-ORIENTED IMAGE COMPENSATING METHOD - A motion-oriented image compensating method is disclosed. The method uses the pixel luminance of a present image data and a last image data to judge the minimum motion vector in X-axis and the minimum motion vector in Y-axis of the present image data, following by conducting luminance compensation of the pixels according to the above-mentioned two minimum motion vectors to advance the sharpness of image edges and thereby the image quality. | 07-02-2009 |
| 20090164869 | MEMORY ARCHITECTURE AND CONFIGURATION METHOD THEREOF - A memory architecture and a configuration method thereof are provided. In the memory configuration method, a data to be stored in the memory and a corresponding error correction code (ECC) are first provided. When the data is written into the memory, the ECC is stored next to the corresponding data, such that the ECC and the corresponding data can be adjoined with each other in the memory. As a result, when the data is read from the memory, the data and the corresponding ECC can be obtained in turn, so as to achieve the purpose of checking the correctness of the data with a smaller buffer, and the hardware cost of the buffer can also be reduced. | 06-25-2009 |
| 20090147566 | Phase Change Memory And Control Method Thereof - A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein. | 06-11-2009 |
| 20090146127 | PHASE CHANGE MEMORY - Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the heaters. The bottom electrodes are respectively coupled to the heaters. Regarding the transistors, their first terminals are respectively coupled to the bottom electrodes, their control terminals are used for coupling to word lines, and their second terminals are used for coupling to bit lines. In an embodiment with four heaters, the regions the heaters aimed at the phase change element form a 2×2 storage array. | 06-11-2009 |
| 20090141548 | MEMORY AND METHOD FOR DISSIPATION CAUSED BY CURRENT LEAKAGE - Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed. | 06-04-2009 |
| 20090122599 | WRITING SYSTEM AND METHOD FOR PHASE CHANGE MOMORY - An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched. | 05-14-2009 |
| 20090103381 | ASYNCHRONOUS SENSE AMPLIFIER FOR READ ONLY MEMORY - The asynchronous sense amplifier for a ROM comprises a current-mirror circuit, a first negative feedback inverter, a second negative feedback inverter, a first transistor group, a second transistor group and a feedback transistor. The feedback transistor connects the junction of the first transistor group and the first set of the current-mirror circuit and/or the junction of the second transistor group and the second set of the current-mirror circuit to ground, where the feedback transistor is controlled by the output of the first negative feedback inverter and/or the second negative feedback inverter, and the feedback transistor is smaller than one transistor of the second transistor group. | 04-23-2009 |
| 20090101884 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer. | 04-23-2009 |
| 20090101880 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the first dielectric layer and covered a portion of the first conductive contact and the insulating layer in a first direction, contacting to the first conductive contact and a first side of the PCM. A second electrode is disposed over the first dielectric layer and covered a portion of the insulating layer in a second direction, contacting to a second side of the PCM. A second dielectric layer is disposed over the first dielectric layer to cover the first electrode, the second electrode, the insulating layer and the PCM, including a second conductive contact connected to the second electrode. | 04-23-2009 |
| 20090091389 | LVDS RECEIVER CIRCUIT - The LVDS receiver circuit comprises a differential-input transistor pair, a control transistor pair, a current-mirror-load circuit, a first feedback inverter and a second feedback inverter. The first feedback inverter, the second feedback inverter and the control transistor pair constitute a feedback loop. The voltage change of the input voltage of the first feedback inverter is suppressed, and the input voltage is controlled around the threshold voltage of the first feedback inverter. | 04-09-2009 |
| 20090080243 | DEVICE CONTROLLING PHASE CHANGE STORAGE ELEMENT AND METHOD THEREOF - Devices controlling a phase change storage element and methods for increasing reliability of a phase change storage element. The invention introduces a first operation mode and a second operation mode. A reference phase change storage element is forced a write current for an ideal conduction period in the first operation mode. In the second operation mode, the invention generates a proper conduction period based on the resistance of the reference phase change storage element, and forces the write current into the controlled phase change storage element for the proper conduction period. | 03-26-2009 |
| 20090078926 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed. | 03-26-2009 |
| 20090065758 | PHASE CHANGE MEMORY ARRAY AND FABRICATION THEREOF - A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the second cell are disposed at different layers. | 03-12-2009 |
| 20090059454 | CURRENT LIMIT PROTECTION APPARATUS AND METHOD FOR CURRENT LIMIT PROTECTION - A current limit protection apparatus and a method for current limit protection are provided. The current limit protection apparatus includes a MOS transistor, a current detecting unit, and a current limit circuit. Two source/drain of the MOS transistor are used for receiving a first-voltage and outputting a second-voltage respectively. A gate of the MOS transistor is used for receiving a gate driving signal to determine a conducting current of the MOS transistor. The current detecting unit is used for detecting the conducting current, so as to generate a detecting result. The current limit circuit has a plurality of current threshold values. The current limit circuit selects one of the current threshold values according to an indicating signal and generates the gate driving signal according to a difference between the selected current threshold value and the detecting result. | 03-05-2009 |
| 20090057643 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second conductive spacer, wherein the second conductive spacer is electrically connected to the first conductive spacer through the second portion of the phase change layer. | 03-05-2009 |
| 20090057640 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element and fabrication method thereof is provided. The phase-change memory element comprises an electrode. A first dielectric layer is formed on the substrate. An opening passes through the first dielectric layer exposing the electrode. A heater with an extended part is formed in the opening, wherein the extended part protrudes the opening. A second dielectric layer surrounds the extended part of the heater exposing the top surface of the extended part. A phase-changed material layer is formed on the second dielectric layer to directly contact the top of the extended part. | 03-05-2009 |
| 20090045386 | Phase-change memory element - A phase-change memory element. The phase-change memory element comprises a first electrode and a second electrode. A first phase change layer is electrically coupled to the first electrode. A second phase change layer is electrically coupled to the second electrode. A conductive bridge is formed between and electrically coupled to the first and second phase change layers. | 02-19-2009 |
| 20090043521 | TRANSISTOR CIRCUIT WITH ESTIMATING PARAMETER ERROR AND TEMPERATURE SENSING APPARATUS USING THE SAME - A transistor circuit with estimating parameter error and temperature sensing apparatus using the same are provided. The temperature sensing apparatus measures and calculates a parameter error of transistor which is driven by different currents in advance. And the temperature sensing apparatus compensates an error occurred during temperature measurement using the acquired the parameter error so as to obtain an accurate environment temperature. | 02-12-2009 |
| 20090036030 | POLISHING HEAD AND CHEMICAL MECHANICAL POLISHING PROCESS USING THE SAME - A polishing head for a chemical mechanical polishing process is provided. The polishing head includes an inner circle part and an outer circle part. The outer circle part is a ring-like structure that is connected to the inner circle part. The inner circle part and the outer circle part are an integrated structure. There is a level difference between the respective surfaces of the outer circle part and the inner circle part. Further, the surface of the outer circle part is higher than that of the inner circle part. | 02-05-2009 |
| 20090032794 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A first dielectric layer having a sidewall is provided. A bottom electrode is adjacent to the sidewall of the first dielectric layer, wherein the bottom electrode comprises a seed layer and a conductive layer. A second dielectric layer is adjacent to a side of the bottom electrode opposite the sidewall of the first dielectric layer. A top electrode couples the bottom electrode through a phase change layer. | 02-05-2009 |
| 20090014705 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A phase change memory device is provided. The phase change memory device comprises a substrate. A first conductive layer is formed on the substrate. A heating electrode is formed on the first conductive layer, and electrically connected to the first conductive layer, wherein the heating electrode comprises a carbon nanotube (CNT). A phase change material layer covers the heating electrode. A second conductive layer is formed on the phase change material layer, and electrically connected to the phase change material layer. | 01-15-2009 |
| 20090010047 | WRITING CIRCUIT FOR A PHASE CHANGE MEMORY - A phase change memory writing circuit is provided. The circuit comprises a writing path and a fast write control unit. The writing path further comprises a current driving unit, a first switch device and a phase change memory cell. The current driving unit is coupled to a high voltage source and outputs a driving current. The first switch device is controlled by a first control signal. The fast write control unit is coupled to the writing path to provide a writing voltage to the writing path. When the first switch device is turned off, the fast write control unit outputs the writing voltage to the writing path. When the first switch device is turned on, the fast write control unit stops outputting the writing voltage to the writing path. | 01-08-2009 |
| 20090008621 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element is provided. The phase-change memory element of an embodiment of the invention comprises a phase-change material layer with a concave, and a heater with an extended part, wherein the extended part of the heater is wedged in the concave of the phase-change material layer. Specifically, the extended part of the heater has a length of 10˜5000 Å. | 01-08-2009 |
| 20080316847 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a storage capacitor and a reference capacitor, a storage memory device and a reference memory device, a storage discharge switch and a reference discharge switch, and an arbitrator. First terminals of the storage capacitor and the reference capacitor are respectively coupled to a pre-charge voltage via first switches. First terminals of the storage memory device and the reference memory device are respectively coupled to the first terminals of the storage capacitor and the reference capacitor. The storage discharge switch and the reference discharge switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The arbitrator is coupled to the first terminals of the storage memory device and the reference memory device and provides an output as a read result of the storage memory device. | 12-25-2008 |
| 20080316803 | SENSING CIRCUIT OF A PHASE CHANGE MEMORY AND SENSING METHOD THEREOF - A sensing circuit of a phase change memory. The sensing circuit comprises a data current source and a reference current source, a storage memory device and a reference memory device, a storage switch and a reference switch, an auxiliary current source and a comparator. First terminals of the storage memory device and the reference memory device are respectively coupled to the data current source and the reference current source. The storage switch and the reference switch are respectively coupled to second terminals of the storage memory device and the reference memory device. The auxiliary current source is dynamically coupled to the first terminals of the storage memory device and the reference memory device. The comparator is coupled to the first terminals of the storage memory device and the reference memory device. | 12-25-2008 |
| 20080311699 | PHASE-CHANGE MEMORY AND FABRICATION METHOD THEREOF - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 12-18-2008 |
| 20080307236 | METHOD AND APPARATUS FOR PASSWORD OUTPUT - A method and an apparatus for account and/or password output are disclosed. In the present invention, a hot-key corresponding to an account and/or a password is set in advance. By entering the hot-key, the related account and/or password is transferred and login automatically, thus the purpose of making login more conveniently is achieved. Besides, the present invention combines various input device to make the way of setting hot-key become more diversely, therefore security of password login is also enhanced. | 12-11-2008 |
| 20080296554 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device includes an array of phase change memory cells. Each phase change memory cell includes a selecting transistor disposed on a substrate. An upright electrode structure is electrically connected to the selecting transistor. An upright phase change memory layer is stacked on the upright electrode structure with a contact area therebetween, wherein the contact area serves as the location where phase transition takes place. | 12-04-2008 |
| 20080296552 | PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory cell structures and methods for fabricating the same are provided. An exemplary embodiment of a phase change memory cell structure includes a first electrode formed over a first dielectric layer. A second dielectric layer is formed over the first electrode. A conductive member is formed through the second dielectric layer and electrically contacting the first electrode, wherein the conductive member comprises a lower element and an upper element sequentially stacking over the first electrode, and the lower and upper elements comprises different materials. A phase change material layer is formed over the second dielectric layer, electrically contacting the conductive member. A second electrode is formed over the phase change material layer. | 12-04-2008 |
| 20080290335 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A phase change memory device comprising a substrate. A plurality of bottom electrodes isolated from each other is on the substrate. An insulating layer crosses a portion of the surfaces of any two of the adjacent bottom electrodes. A pair of phase change material spacers is on a pair of sidewalls of the insulating layer, wherein the pair of the phase change material spacers is on any two of the adjacent bottom electrodes, respectively. A top electrode is on the insulating layer and covers the phase change material spacers. | 11-27-2008 |
| 20080283814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material. | 11-20-2008 |
| 20080283812 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element. The phase-change memory comprises first and second electrodes. A phase-change material layer is formed between the first and second electrodes. And a carbon-doped oxide dielectric layer is formed to surround the phase-change material layer, wherein the first electrode electrically connects the second electrodes via the phase-change material layer. | 11-20-2008 |
| 20080272358 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer. | 11-06-2008 |
| 20080265849 | CONTROL APPARATUS OF POWER CONVERSION CIRCUIT AND CONTROL METHOD THEREOF - A control apparatus for a power conversion circuit and a control method thereof are provided. The method of the control apparatus includes producing a first control signal and a second control signal; modulating the first control signal according to an output voltage of the power conversion circuit; detecting the output voltage of the power conversion circuit to attain a detecting result; if the detecting result exhibits the input voltage of the power conversion circuit below a normal operating level, using the second control signal to control the power conversion circuit; or if the detecting result exhibits the input voltage of the power conversion circuit above the normal operating level, using the first control signal to control the power conversion circuit. The duty cycle of the fist control signal is greater than that of the second control signal. | 10-30-2008 |
| 20080265238 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto. | 10-30-2008 |
| 20080258834 | PULSE WIDTH MODULATION CIRCUIT - A pulse width modulation (PWM) circuit includes a turn on/off switch and a PWM controller. The first terminal of the turn on/off switch is coupled to a turn off voltage. The control terminal of the turn on/off switch receives a turn on/off signal to decide whether the circuit between the first terminal and the second terminal of the turn on/off switch is turned on or not. The PWM controller includes a PWM pin and a turn on/off device. The PWM pin is coupled to the second terminal of the turn on/off switch to output a PWM signal. The turn on/off device is coupled to the PWM pin to decide the turn on/off of the PWM controller according to a signal swing state of the PWM pin. | 10-23-2008 |
| 20080258223 | ESD PROTECTION DEVICE - An ESD protection device is provided. The ESD protection device of the present invention includes a semiconductor substrate/well, a first doped region, a second doped region and a third doped region. The first doped region doped with a first dopant is disposed in the semiconductor substrate/well. The second doped region doped with a second dopant is disposed in the semiconductor substrate/well, wherein a predetermined distance is maintained between the second doped region and the first doped region. The third doped region doped with the second dopant is disposed in the first doped region. The ESD protection device of the present invention is adapted for solving the reverse recovery problem of the conventional diode during the bipolar type ESD stressing. | 10-23-2008 |
| 20080251498 | PHASE CHANGE MEMORY DEVICE AND FABRICATIONS THEREOF - A method for forming a memory device is disclosed. A dielectric layer is formed on a substrate. A Sn doped phase change layer is formed on the dielectric layer. A patterned mask layer is formed on the Sn doped phase change layer. The Sn doped phase change layer is etched by an etchant comprising fluorine-based etchant added with chlorine using the patterned mask layer as a mask to pattern the Sn doped phase change layer. An electrode is formed, electrically connecting the patterned Sn doped phase change layer. | 10-16-2008 |
| 20080241741 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer. | 10-02-2008 |
| 20080239798 | Compensation circuit and memory with the same - One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal. | 10-02-2008 |
| 20080237562 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSi | 10-02-2008 |
| 20080219046 | Writing method and system for a phase change memory - A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature. | 09-11-2008 |
| 20080203374 | Phase-change memory and fabrication method thereof - A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material. | 08-28-2008 |
| 20080197335 | Semiconductor device and fabrications thereof - A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure. A bottom electrode electrically connects the first electrode layer of the pillar structure. A top electrode electrically connects the second electrode layer of the pillar structure. | 08-21-2008 |
