| Wafer-Level Packaging Portfolio LLC Patent applications |
| Patent application number | Title | Published |
|---|
| 20120003791 | Method for Packaging Electronic Devices and Integrated Circuits - The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits. | 01-05-2012 |
| 20110169171 | Dual Interconnection in Stacked Memory and Controller Module - A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package. | 07-14-2011 |
| 20100327448 | Semiconductor with Bottom-Side Wrap-Around Flange Contact - A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact. | 12-30-2010 |
| 20100270668 | Dual Interconnection in Stacked Memory and Controller Module - A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package. | 10-28-2010 |
