| VNS PORTFOLIO LLC Patent applications |
| Patent application number | Title | Published |
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| 20110013467 | System and Method for Reading Memory - A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die. | 01-20-2011 |
| 20100268911 | Method and Apparatus for Dynamic Partial Reconfiguration on an Array of Processors - A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including the number and identity of all processors to be modified, executing native machine code in the port of a processing device, and modifying a segment of the internal memory of said single processing device. Additional embodiments allow modification of multiple processors in the array, including the modification of all processors on a die or system. The apparatus includes a processor array having a first group of processors connected together for performing a first task, and a second group of processors connected together for performing a second task with at least one processor connected to said first group of processors and said second group of processors for facilitating communications between said first group of processors and said second group of processors without participating in said first task and said second task. In an embodiment of the apparatus, this one processor dynamically reconfigures the array. Additional embodiments allow additional processors to aid in the reconfiguration. | 10-21-2010 |
| 20100254197 | Latch Pulse Delay Control - A novel memory circuit includes a pulse line, a memory latch including an enable port, and a pulse delay element interposed between the pulse line and the enable port of the memory latch. In a particular embodiment, the pulse delay element includes a series of logic gates. In a more particular embodiment, the series of logic gates include a feedback line for disconnecting the enable port from the pulse line. In another particular embodiment, the enable ports of two different memory latches are connected to the same pulse line via two different latch pulse delay elements, each having different delay times. In a more particular embodiment, the data output port of the first latch is connected to the data input port of the second latch. | 10-07-2010 |
| 20100191787 | Sequential Multiplier - A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second logic circuit generates a partial product based on the control signal and the multiplicand. A full adder generates a partial sum and a partial carry in each of a sequence of cycles. In the first cycle the partial sum and the partial carry are both initialized to zero. In each said cycle the partial sum, the partial carry, and the partial product are added to generate a new partial sum and a new partial carry. After a last cycle, the partial sum is the final product. | 07-29-2010 |
| 20100158076 | Direct Sequence Spread Spectrum Correlation Method for a Multiprocessor Array - A method and apparatus for correlation of a received DSSS signal with a PN sequence, thus significantly reducing the processing time and operating power needed to acquire phase information for DSSS de-spreading and demodulation. The apparatus utilizes a multiprocessor array | 06-24-2010 |
| 20100138618 | Priority Encoders - A priority encoder and a processing device having the priority encoder. The priority encoder includes a port selector for generating a plurality of prioritized read requests based on a plurality of write requests from a plurality of processing devices and a predetermined priority assigned to each of the plurality of processing devices, one of the plurality of processing devices being selected based on the plurality of prioritized read requests; and a port latch for holding the values of the prioritized read requests to enable one of a plurality of communication ports unless the prioritized read requests are changed, each communication port for communicating with one of the processing devices to read data from the processing device. | 06-03-2010 |
| 20100138207 | Method and Apparatus for Circuit Simulation - An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete. | 06-03-2010 |
| 20100125441 | Method and Apparatus for Circuit Simulation - An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete. | 05-20-2010 |
| 20100125440 | Method and Apparatus for Circuit Simulation - A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one-dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached. | 05-20-2010 |
| 20100123570 | Localized Control Method and Apparatus - A zoned interactive control area ( | 05-20-2010 |
| 20100123414 | Variable Lighting Zones - A zoned lighting space ( | 05-20-2010 |
| 20100100389 | System for Signal Sample Rate Conversion - An apparatus and method for converting a source signal at a first rate to a re-sampled signal at a second rate using an array of processors. A decoder decomposes the source signal into left and right source values and sends an aperture signal to a coefficient control unit upon decomposition completion. A transfer unit controllably receives and passes the left and right source values on to a re-sampler. The coefficient control unit calculates a polyphase offset based on the aperture signal and a clock signal. A coefficient server selectively passes coefficients to the re-sampler based on the polyphase offset. And the re-sampler generates the re-sampled signal based on the left and right source values and the coefficients. | 04-22-2010 |
| 20100088083 | Method and Apparatus for Circuit Simulation - A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a transistor temperature value for all transistors in the active transistor list. | 04-08-2010 |
| 20100085078 | Digital Logic Voltage Level Shifter - A digital logic level shifter having three stages. An initial stage includes a conventional 4-terminal bridge-type inverter circuit. A middle stage includes a 5-terminal first logic reversing circuit that has two middle stage inputs that are not connected in common. And a final stage includes a 5-terminal second logic reversing circuit that has two final stage inputs that are not connected in common. | 04-08-2010 |
| 20100064118 | Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups - A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed at a rate faster than expected. A simple apparatus for accomplishing this method is illustrated. | 03-11-2010 |
| 20100023733 | Microprocessor Extended Instruction Set Precision Mode - A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits of precision when executing the plus instruction. An additional bit position is added to the program counter register. When this bit is set, the microprocessor is in extended instruction set mode. In addition, a new one bit latch is provided. The latch may be changed only when the microprocessor is in extended instruction set mode. The latch is defined as holding a true carry bit. A significant bit of a register holding a sum is saved in the carry latch at the end of the plus instruction. | 01-28-2010 |
| 20100023730 | Circular Register Arrays of a Computer - The invention provides a method and apparatus for eliminating the stack overflow and underflow in a dual stack computer | 01-28-2010 |
| 20090319755 | Method and Apparatus for High Speed Data Stream Splitter on an Array of Processors - A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors | 12-24-2009 |
| 20090300334 | Method and Apparatus for Loading Data and Instructions Into a Computer - A computer array ( | 12-03-2009 |
| 20090259892 | Method and Apparatus for Producing a Metastable Flip Flop - The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus | 10-15-2009 |
| 20090259826 | Microprocessor Extended Instruction Set Mode - Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits in the P-register from 9 to 10. A tenth bit signals an extended instruction mode. When the tenth bit is not set, microprocessor instructions perform legacy functions. When the tenth bit is set, the extended instruction mode is active and instructions perform different or enhanced functions. | 10-15-2009 |
| 20090259770 | Method and Apparatus for Serializing and Deserializing - A method and apparatus for serialization of a transmitted data stream and deserialization of data on a single die chip | 10-15-2009 |
| 20090257263 | Method and Apparatus for Computer Memory - A method and apparatus for forming computer memory | 10-15-2009 |
| 20090138677 | System for Native Code Execution - A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that includes native code instructions of the executer node. A token is loaded from the memory and executed in the agent node based on its type. In particular, if the token is an optional stop type execution ends and if the token is a run type the native code instructions in the token are sent to the executor node. The native code instructions are executed in the executor node as received from the agent node. And such loading and execution continues in this manner indefinitely or until a stop type token is executed. | 05-28-2009 |
| 20090033536 | Method and Apparatus for Digital to Analog Conversion - The apparatus described is a multi-core processor | 02-05-2009 |
