VIRTIUM TECHNOLOGY, INC. Patent applications |
Patent application number | Title | Published |
20150092487 | Solving MLC NAND paired page program using reduced spatial redundancy - Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage. | 04-02-2015 |
20140181595 | ESTIMATING LIFESPAN OF SOLID-STATE DRIVE USING REAL USAGE MODEL - An embodiment is a technique to estimate lifespan of a solid-state drive (SSD). Real environmental information from an environmental processor is received. The real environmental information corresponds to an environment of a solid-state drive (SSD). The lifespan of the SSD is estimated using the real environmental information and an internal data usage model. The estimated lifespan is made available for retrieval. | 06-26-2014 |
20140181585 | REAL USAGE MODEL FOR SOLID-STATE DRIVE - An embodiment is a technique to generate failure mode information for solid-state drive (SSD) in real environment. An environmental acquisition module acquires environmental information from an environmental sensor. A learning and update module generates an environmental profile based on the acquired environmental information. A failure acquisition module associates failure information from an SSD controller that controls an SSD with the environmental profile. An operation analyzer analyzes the associated failure information using pre-determined information provided by a database to generate failure mode information. A decision module decides if the failure mode information is valid. | 06-26-2014 |
20140181434 | INTEGRATED AND NATURALIZED STATIC WEAR-LEVELING FOR BLOCK MAPPING - An embodiment is a technique to perform static wear leveling in a flash device. A first static block is popped from front of a first-in-first-out (FIFO) static pool when a static wear leveling condition is met. Data are copied from the first static block into an erased block to form a new block. The new block is pushed to end of the FIFO static pool. The static pool is part of a current static set and a next static set. | 06-26-2014 |
20140181363 | ADAPTING BEHAVIOR OF SOLID-STATE DRIVE USING REAL USAGE MODEL - An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained. | 06-26-2014 |
20140173369 | CLASSIFYING FLASH DEVICES USING ECC - An embodiment is a technique to classify a flash device. Test data to a flash device are accessed in unscramble and scramble modes under a test mode. Error correcting code (ECC) results are recorded on the test data for the unscramble and scramble modes. A device quality figure is calculated based on the ECC results for the unscramble and scramble modes. The flash device is classified using the device quality figure. | 06-19-2014 |
20140173176 | HEAP-BASED MECHANISM FOR EFFICIENT GARBAGE COLLECTION BLOCK SELECTION - N page counters are associated with N blocks in the flash subsystem. Each of the N page counters indicates a count of invalid pages in each corresponding block in the N blocks. A max heap structure is formed over the N page counters. At least one of the N page counters is updated each time the count changes. The max heap structure is updated each time the at least one of the N page counters is updated. | 06-19-2014 |
20140173175 | NAND COMMAND AGGREGATION - An embodiment is a method and apparatus to provide an optimization of commands in a flash device. Commands sent by at least a top-level processor to a flash device are buffered in a buffer. The buffered commands are analyzed for an optimizing condition. The commands are aggregated if the optimizing condition is met. The aggregated commands are sent to the flash device. | 06-19-2014 |
20140172325 | LIFE MONITORING IN SOLID-STATE DRIVE - An embodiment is a method and apparatus for a technique to report remaining life information of a non-volatile memory array. Information on expected life of a non-volatile memory array is received from a solid-state drive (SSD) processor. The information is converted into remaining life information according to a pre-defined format. The remaining life information is transmitted to an indicator or a communication device. | 06-19-2014 |
20110126046 | SAVING INFORMATION TO FLASH MEMORY DURING POWER FAILURE - An embodiment is a method and apparatus to save data during power failure. A power supply generator generates operating voltages to a circuit from a generator supply source. A power monitor monitors a normal supply voltage and a backup supply voltage to provide a normal supply voltage to the generator supply source in a normal mode and to provide a backup supply voltage to the generator supply source in a power failure mode. A data transfer circuit transfers data from a volatile memory in the circuit to a non-volatile memory during the power failure mode. | 05-26-2011 |
20110074002 | STACKING DEVICES AT FINISHED PACKAGE LEVEL - An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly. | 03-31-2011 |
20100291736 | STACKING MULTIPLE DEVICES USING SINGLE-PIECE INTERCONNECTING ELEMENT - An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads. | 11-18-2010 |
20100251543 | MULTI-FUNCTION MODULE - An embodiment is a method and apparatus to provide a multi-function module. A circuit board has a form factor and a connector edge corresponding to a first interface standard. The connector edge includes first and second groups of pin-outs that are mapped to pin-out assignments compatible with the first interface standard and a second interface standard, respectively. A first interface is provided on the circuit board for a first set of devices connected to the first group of pin-outs to operate according to the first interface standard. A second interface is provided on the circuit board for a second set of devices connected to the second group of pin-outs to operate according to the second interface standard. | 10-07-2010 |
20100167557 | MULTI-FUNCTION MODULE - An embodiment is a method and apparatus to provide a multi-function module. A circuit board has a form factor and a connector edge corresponding to a first interface standard. The connector edge includes first and second groups of pin-outs that are mapped to pin-out assignments compatible with the first interface standard and a second interface standard, respectively. A first interface is provided on the circuit board for a first set of devices connected to the first group of pin-outs to operate according to the first interface standard. A second interface is provided on the circuit board for a second set of devices connected to the second group of pin-outs to operate according to the second interface standard. | 07-01-2010 |