| VirtenSys Limited Patent applications |
| Patent application number | Title | Published |
|---|
| 20110069710 | Switching Method - A method for providing identifiers for virtual devices in a network. The method comprises receiving a discovery data packet directed to a physical network node associated with a physical endpoint device. A response to the discovery data packet directed to a physical network node is provided, the response comprising an identifier of a virtual device. At least one further discovery data packet directed at least to said virtual device is received. A response to a first one of the further discovery data packets is provided, the response comprising an identifier of a virtual endpoint device. At least some functionality of the virtual endpoint device is provided by the physical endpoint device. | 03-24-2011 |
| 20090150563 | Control path I/O virtualisation - There is disclosed a data switch in combination with a proxy controller, the data switch being configured for routing data traffic and control traffic between at least one input/output (I/O) device and at least one server including a memory having an address space including set of data buffers and a list of command/status descriptors. The data switch is configured to:
| 06-11-2009 |
| 20090103556 | DATA SWITCH - A data switch for an integrated circuit comprising at least one link for receiving input data packets from an independently modulated spread spectrum clock (SSC) enabled source having predetermined spread spectrum link clock frequency characteristics, and at least one output for transmitting the data packets after passage through the switch, the switch further comprising at least one receive buffer having a link side and a core side for receiving the SSC modulated input data packets from the link, at least one transmit buffer and a core clock, wherein the core clock operates at a given frequency between predetermined error limits determined by oscillation accuracy alone and is not SSC-enabled, the core clock frequency being set at a level at least as high as the highest link clock frequency such that the receive buffer cannot be filled faster from its link side than it can be emptied from its core side. | 04-23-2009 |
