| VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120081826 | Poly Fuse Burning System - This invention provides a poly fuse burning system comprising a poly fuse, a controllable power source supplying power for burning the poly fuse, and a monitor circuit monitoring the burning state of the poly fuse, wherein when a targeted burning state is reached, a control signal is output to shut down the controllable power source to stop the burning. | 04-05-2012 |
| 20120056295 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 03-08-2012 |
| 20120001225 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 01-05-2012 |
| 20110117709 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively. | 05-19-2011 |
| 20110101453 | LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR - The invention provides a lateral double-diffused metal oxide semiconductor (LDMOS). The pre-metal dielectric layer (PMD) of the LDMOS is a silicon rich content material. Additionally, the inter-layer dielectric layer (ILD), inter-metal dielectric layer (IMD), or protective layer of the LDMOS may be formed of a silicon rich content material. | 05-05-2011 |
| 20110095391 | SCHOTTKY DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A Schottky diode device is provided, including a p-type semiconductor structure. An n drift region is disposed over the p-type semiconductor structure, wherein the n drift region comprises first and second n-type doping regions having different n-type doping concentrations, and the second n-type doping region is formed with a dopant concentration greater than that in the first n-type doping region. A plurality of isolation structures is disposed in the second n-type doping region of the n drift region, defining an anode region and a cathode region. A third n-type doping region is disposed in the second n-type doping region exposed by the cathode region. An anode electrode is disposed over the first n-type doping region in the anode region. A cathode electrode is disposed over the third n-type doping region in the cathode region. | 04-28-2011 |
| 20110070709 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - The invention provides a method for forming a semiconductor structure. A substrate is provided. A conductive layer is formed on the substrate. A first patterned mask layer is formed on the conductive layer. The conductive layer exposed by the first patterned mask layer is removed to expose a first sidewall of the conductive layer. A doped region is formed in the substrate by a doping step using the first patterned mask layer as a mask. The first patterned mask layer is removed. A second patterned mask layer is formed on the conductive layer. The conductive layer exposed by the second patterned mask layer is removed to expose a second sidewall opposite to the first sidewall of the conductive layer. The second patterned mask layer is removed. | 03-24-2011 |
| 20110062500 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 03-17-2011 |
| 20110012204 | TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N | 01-20-2011 |
| 20100315852 | MEMORY AND STORAGE DEVICE UTILIZING THE SAME - A storage device including a memory and a reading circuit is disclosed. The memory includes a plurality of word lines, a first bit line, a second bit line, a third bit line, and a plurality of cells. The word lines are sequentially disposed in parallel. The first, the second, and the third bit lines are sequentially disposed in parallel and vertical with the word lines. Each cell corresponds to one word line and one bit line. The word line, which corresponds to the cell corresponding to the first bit line, differs from the word line, which corresponds to the cell corresponding to the second bit line. The read circuit is coupled to the memory for reading the data stored in the memory. | 12-16-2010 |
| 20100301388 | SEMICONDUCTOR DEVICE AND LATERAL DIFFUSED METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - The invention provides a semiconductor device and a lateral diffused metal-oxide-semiconductor transistor. The semiconductor device includes a substrate having a first conductive type. A gate is disposed on the substrate. A source doped region is formed in the substrate, neighboring with a first side of the gate, wherein the source doped region has a second conductive type different from the first conductive type. A drain doped region is formed in the substrate, neighboring with a second side opposite to the first side of the gate. The drain doped region is constructed by a plurality of first doped regions with the first conductive type and a plurality of second doped regions with the second conductive type, wherein the first doped regions and the second doped regions are alternatively arranged. | 12-02-2010 |
| 20100301385 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device including a substrate, a first doped region, a first gate electrode, a second doped region, a second gate electrode, and a third doped region is disclosed. The substrate has a first conductive type. The first doped region has a second conductive type and is formed in the substrate. The first gate electrode is formed on the substrate. The second doped region has the second conductive type and is formed in the substrate. A transistor is constituted by the first doped region, the first gate electrode, and the second doped region. The second gate electrode is formed on the substrate. The first and the second gate electrodes are separated. The third doped region has the first conductive type and is formed in the substrate. A discharge element is constituted by the first doped region, the second gate electrode, and the third doped region. | 12-02-2010 |
| 20100276810 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. A substrate is provided. A buried layer is formed in the substrate. The buried layer comprises an insulating region. A deep trench contact structure is formed in the substrate. The deep trench contact structure comprises a conductive material and a liner layer formed on a side wall of the conductive material. The conductive material is electrically connected with the substrate. | 11-04-2010 |
| 20100270615 | METHOD FOR INCREASING BREAKING DOWN VOLTAGE OF LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR - A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region. | 10-28-2010 |
| 20100210113 | METHOD FOR FORMING VIA - The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step. | 08-19-2010 |
| 20100208398 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEFRATED CIRCUIT UTILIZING THE SAME - An ESD protection circuit coupled between a first power line and a second power line to avoid damage to an integrated circuit by an ESD event is disclosed. The ESD protection circuit includes a detection unit, a trigger unit, and a discharging unit. The detection unit asserts a detection signal when the ESD event occurs. The trigger unit asserts a first trigger signal and a second trigger signal when the detection is asserted. The discharging unit provides a discharge path to release an ESD current caused by the ESD event when the first and the second trigger signals are asserted. | 08-19-2010 |
| 20100207174 | SEMINCONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region. | 08-19-2010 |
| 20100202219 | BURN-IN METHODS FOR STATIC RANDOM ACCESS MEMORIES AND CHIPS - A burn-in method for SRAMs and chips. For a memory cell of the SRAM, the SRAM burn-in method controls the control signals of the memory cell to generate current paths to pass through the memory cell, the corresponding bit-line and the corresponding bit-line-bar. The contacts/vias in the current paths are tested by providing burn-in currents to flow through the current paths, so that mismatched contacts/vias are burned by the burn-in currents. SRAMs that fail the burn-in test are abandoned after the burn-in procedure. | 08-12-2010 |
| 20100195358 | VOLTAGE REGULATOR AND AC-DC CONVERTER - A voltage regulator is provided. An input node receives an input voltage. An output node provides a supply voltage. A first transistor is coupled between the input node and a node. A first resistor is coupled between the input node and a gate of the first transistor. A second transistor is coupled between the node and the output node. An amplifier includes a non-inverting input terminal for receiving a reference voltage and an inverting input terminal. A second resistor is coupled between the inverting input terminal and a ground. A third transistor is coupled between the second resistor and a gate of the second transistor, wherein the third transistor is controlled by an output of the amplifier. A fourth transistor is coupled between the third transistor and the first node, wherein a gate of the fourth transistor is coupled to the gate of the second transistor. | 08-05-2010 |
| 20100187566 | INSULATED GATE BIPOLAR TRANSISTOR (IGBT) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES - Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P | 07-29-2010 |
| 20100185998 | METHOD FOR OPC CORRECTION - An optical proximity correction method is disclosed, comprising establishing an optical proximity correction (OPC) model, and performing an OPC correction step to correct segments of a layout pattern. The OPC correction comprises the step of defining an edge of the layout pattern neighboring a hot-spot location on a mask to locate a target point and a dissection point. The step of locating the target point and the dissection point includes setting a plurality of pre-target points and pre-dissection points, and electing a target point and a dissection point for correcting the segments of the layout pattern from the pre-target points and pre-dissection points according to image quality of the pre-target points and pre-dissection points. | 07-22-2010 |
| 20100181639 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices. | 07-22-2010 |
| 20100177556 | ASYMMETRIC STATIC RANDOM ACCESS MEMORY - An asymmetric static random access memory (SRAM) device that includes at least one SRAM cell is provided. The SRAM cell includes the first inverter and the second inverter. The first inverter is coupled between a first power and a ground power, and includes a first output terminal coupled to a first node and a first input terminal coupled to a second node. The second inverter is coupled between the first power and the ground power, and includes a second input terminal coupled to the first node and a second output terminal coupled to the second node. When the first inverter and the second inverter receive current from the first power, the SRAM cell is programmed to a predetermined value in advance according to different conductance levels of the first inverter and the second inverter. | 07-15-2010 |
| 20100176515 | CONTACT PAD SUPPORTING STRUCTURE AND INTEGRATED CIRCUIT - The invention provides a contact pad supporting structure. The contact pad supporting structure includes an underlying first conductive plate and an overlying second conductive plate, wherein the first and second conductive plates are separated by a first dielectric layer. A plurality of circular ring-shaped via plug groups comprising a plurality of circular ring-shaped via plugs is through the first dielectric layer, electrically connecting to the first and second conductive plates. All of the circular ring-shaped via plugs of each of the circular ring-shaped via plug groups are disorderly arranged. | 07-15-2010 |
| 20100163989 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 07-01-2010 |
| 20100148256 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) DEVICES WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION CAPABILITY IN INTEGRATED CIRCUIT - Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N | 06-17-2010 |
| 20100102794 | BANDGAP REFERENCE CIRCUITS - A bandgap reference circuit is provided. An input node receives a supply voltage. An output node provides a reference voltage. A first transistor is coupled between the input node and the output node and has a first control terminal. A resistor is coupled between the input node and the first control terminal. A second transistor is coupled to the first control terminal and has a second control terminal coupled to the output node. A third transistor is coupled between the second transistor and a ground terminal and has a third control terminal. A voltage dividing unit provides a first voltage and a second voltage according to the reference voltage. A differential amplifier provides a signal to the third control terminal according to a difference between the first and second voltages. | 04-29-2010 |
| 20100087054 | METHOD FOR FORMING DEEP WELL OF POWER DEVICE - The invention provides a method for forming a deep well region of a power device, including: providing a substrate with a first sacrificial layer thereon; forming a first patterned mask layer on the first sacrificial layer exposing a first open region; performing a first doping process to the first open region to form a first sub-doped region; removing the first patterned mask layer and the first sacrificial layer; forming an epitaxial layer on the substrate; forming a second sacrificial layer on the epitaxial layer; forming a second patterned mask layer on the second sacrificial layer exposing a second open region; performing a second doping process to the second open region to form a second sub-doped region; removing the second patterned mask layer; performing an annealing process to make the first and the second sub-doped regions form a deep well region; and removing the second sacrificial layer. | 04-08-2010 |
| 20100041233 | FABRICATION METHODS FOR INTEGRATION CMOS AND BJT DEVICES - Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device. | 02-18-2010 |
| 20090321875 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer. | 12-31-2009 |
| 20090321825 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME, BIPOLAR-CMOS-DMOS AND METHOD FOR FABRICATING THE SAME - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions. | 12-31-2009 |
| 20090261409 | SEMICONDUCTOR DEVICES FOR HIGH POWER APPLICATION - Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region. | 10-22-2009 |
| 20090238023 | MEMORY SYSTEM - A memory system is provided, comprising at least one memory unit and a source power supply circuit. Each memory unit is coupled between a source voltage and a ground voltage and accesses digital data according to a word line signal and a bit line signal. The source power supply circuit provides the source voltage to the memory units. When the memory unit is in a writing status, the source voltage is the first power voltage. When the memory unit is in a reading status, the source voltage is the second power voltage. The second power voltage equals to the first power voltage subtracted by a specific voltage for avoiding rewriting error. | 09-24-2009 |
| 20090236681 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 09-24-2009 |
| 20090212436 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and method for forming the same are provided. The semiconductor structure comprises a semiconductor substrate, a plurality of top metallizations on the semiconductor substrate, a high density plasma layer filling gaps between the top metallizations and having a substantially planar upper surface overlying the top metallizations, and a passivation layer overlying the high density plasma layer. A metal bump can be formed overlying the top metallizations through the passivation layer and HDPCVD layer for subsequent bonding. | 08-27-2009 |
| 20090142918 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer. | 06-04-2009 |
| 20090141534 | DETECTION APPARATUS AND METHOD FOR SEQUENTIALLY PROGRAMMING MEMORY - A detection apparatus for sequentially programming a memory is provided. The detection apparatus comprises a current sensor and a programming controller. The current sensor is coupled to a programming source and a memory cell. The current sensor detects change of a programming current between the programming source and the memory cell and generates a control signal according to the detection result. The programming controller is coupled to the current sensor. The programming controller receives the control signal and generates a programming state signal. | 06-04-2009 |
| 20090135532 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS - An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad. | 05-28-2009 |
| 20090134478 | SEMICONDUCTOR STRUCTURE - A semiconductor structure including a substrate, a first well, a second well, a third well, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the first well. The third well includes the first conductive type, is formed in the substrate, and neighbors the first well. The first doped region includes the first conductive type and is formed in the first well. The second doped region includes the first conductive type and is formed in the first well. The first well surrounds all surfaces of the first and the second doped regions. | 05-28-2009 |
| 20090134455 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device including a substrate, a first well, a second well, a gate, a first doped region, and a second doped region. The substrate includes a first conductive type. The first well includes a second conductive type and is formed in the substrate. The second well includes the second conductive type and is formed in the substrate. The gate is formed on the substrate and overlaps the first and the second wells. The first doped region includes the second conductive type. The first doped region is formed in the first well and self-aligned with the gate. The second doped region includes the second conductive type. The second doped region is formed in the second well and self-aligned with the gate. The gate, the first and the second doped regions constitute a transistor. | 05-28-2009 |
| 20090033310 | VOLTAGE REGULATOR - A voltage regulator. A pass element has a control gate and outputs an output voltage according to an input voltage and a control signal received from the control gate. A feedback circuit generates a feedback signal according to the output voltage. A bandgap circuit generates a reference voltage according to the output voltage. An amplifier generates a first signal according to the feedback signal and the reference voltage. A start-up circuit generates the control signal according to the reference voltage and the first signal. | 02-05-2009 |
