UTAC THAI LIMITED Patent applications |
Patent application number | Title | Published |
20140015117 | VERY EXTREMELY THIN SEMICONDUCTOR PACKAGE - A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. | 01-16-2014 |
20130337609 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 12-19-2013 |
20130302944 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS - A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages. | 11-14-2013 |
20130299980 | PROTRUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE - A semiconductor package includes terminals extending from a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. Each terminal includes a first plated section, a second plated section, and a portion of a sheet carrier from which the semiconductor package is built upon, wherein the portion is coupled between the first and second plated sections. Each interconnection routing is electrically coupled with a terminal and can extend planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes at least one intermediary layer, each including a via layer and an associated routing layer. The semiconductor package includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals. | 11-14-2013 |
20130299979 | PLATED TERMINALS WITH ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE - A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals. | 11-14-2013 |
20130243893 | MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE - A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound. | 09-19-2013 |
20130234307 | LEAD FRAME LAND GRID ARRAY - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 09-12-2013 |
20130210197 | LEADFRAME BASED MULTI TERMINAL IC PACKAGE - A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound. | 08-15-2013 |
20120094438 | APPARATUS FOR AND METHODS OF ATTACHING HEAT SLUGS TO PACKAGE TOPS - A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more parallel passes across the frame. Each heat slug pad has a top exposed surface and a bottom interfacing surface. The bottom interfacing surface typically interfaces with a package. In some embodiments, the top exposed surface is modified. | 04-19-2012 |
20120066899 | QFN PROCESS FOR STRIP TEST - A process for assembling semiconductor devices comprises encapsulating a leadframe matrix having semiconductor die mounted thereon in a mold compound. The leadframe matrix is partially singulated to electrically isolate each individual leadframe unit. A plurality of leadframe units is tested simultaneously. The leadframe matrix is completely singulated. Non compliant units are discarded. | 03-22-2012 |
20120006528 | METHOD OF AND SYSTEM FOR COOLING A SINGULATION PROCESS - A system for cooling at least one singulation saw used to singulate components from a substrate. The system is comprised of a coolant loop having at one or more coolant delivery means, a coolant collection means, one or more recycle tanks for contaminate particles to settle out of the captured coolant, a mixing tank configured after the recycle tanks within the loop to produce and replace lost coolant, and a means to cool the coolant. The system can all so include filters within the loop to remove particles not removed by the settling tank. Further, the system is able to be configured with a holding tank configured to prevent any bubbles from getting to the coolant delivery means. | 01-12-2012 |
20110241189 | APPARATUS FOR AND METHODS OF ATTACHING HEAT SLUGS TO PACKAGE TOPS - A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages. | 10-06-2011 |
20110232693 | METALLIC SOLDERABILITY PRESERVATION COATING ON METAL PART OF SEMICONDUCTOR PACKAGE TO PREVENT OXIDE - Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication. | 09-29-2011 |
20110221051 | LEADFRAME BASED MULTI TERMINAL IC PACKAGE - A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound. | 09-15-2011 |
20110198752 | LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 08-18-2011 |
20110147931 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 06-23-2011 |
20110133319 | AUXILIARY LEADFRAME MEMBER FOR STABILIZING THE BOND WIRE PROCESS - A semiconductor package comprises a die attach pad and an auxiliary support member at least partially circumscribing the die attach pad. A set of contact leads is formed extending outward from the die attach pad. A first set of contact pads is formed on the bottom surface of the distal ends of the contact leads. An optional second set of contact pads is formed at the bottom surface of the proximal end. The auxiliary support member prevents damage to the contact leads and prevents the leads from bending during the manufacturing process. | 06-09-2011 |
20110076805 | MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE - A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound. | 03-31-2011 |
20110039371 | FLIP CHIP CAVITY PACKAGE - A process for forming a semiconductor package. The process comprises forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip. The semiconductor device has conductive masses attached thereon to effectuate electrical contact between the semiconductor device and the molded leadframe. The conductive masses can be substantially spherical or cylindrical. Liquid encapsulant is dispensed on the semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between the semiconductor device and the molded leadframe. The molded leadframe strip, the semiconductor device, and the conductive masses are at least partially encased in a second mold compound. The second mold compound can be molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed or molded to produce a globular form on the flip chip semiconductor device. The molded leadframe strip is singulated to form discrete semiconductor packages. | 02-17-2011 |
20110018111 | LEADFRAME FEATURE TO MINIMIZE FLIP-CHIP SEMICONDUCTOR DIE COLLAPSE DURING FLIP-CHIP REFLOW - A support feature on a leadframe to support a semiconductor die during placement of the die on the leadframe and minimize the collapsing effect of the connector bumps of the die after reflowing. In some embodiments, the support features are formed from material that is different from the leadframe, such as by a ball drop process or a plating process. In some embodiments, the support features are formed from the leadframe material, such as by etching. In some embodiments, the support features are covered with a coating material. | 01-27-2011 |
20100327432 | PACKAGE WITH HEAT TRANSFER - A semiconductor package includes an encapsulant, a semiconductor device within the encapsulant, and one or more terminals for electrically coupling the semiconductor device to a node exterior to the package. The package further includes bonding means coupling the semiconductor device to the one or more terminals. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a thermally conductive layer is coupled to the semiconductor device, and the layer is exposed at a surface of the package. | 12-30-2010 |
20100311208 | METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE - A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern. | 12-09-2010 |
20100233854 | METALLIC SOLDERABILITY PRESERVATION COATING ON METAL PART OF SEMICONDUCTOR PACKAGE TO PREVENT OXIDE - Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication. | 09-16-2010 |
20100230802 | METALLIC SOLDERABILITY PRESERVATION COATING ON METAL PART OF SEMICONDUCTOR PACKAGE TO PREVENT OXIDE - Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication. | 09-16-2010 |
20100140081 | Method and apparatus for plating a semiconductor package - A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices. | 06-10-2010 |
20090241329 | SIDE RAIL REMOVER - Side rail removal apparatus and method for removal of side rails are provided. The side rail removal apparatus includes a side rail removal assembly, side rail removal pins, a turn-table, and upper and lower holders for the removal pins. Hence, the user can remove the side rails of UV tape without causing scratching to an IC package. | 10-01-2009 |
20080299756 | METHOD AND APPARATUS FOR PLATING A SEMICONDUCTOR PACKAGE - A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices. | 12-04-2008 |