| UNITED MICROELECTRONICS CORP. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120122035 | PATTERNING METHOD AND METHOD FOR FABRICATING DUAL DAMASCENE OPENING - A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed. | 05-17-2012 |
| 20120112782 | METHOD FOR PREDICTING TOLERABLE SPACING BETWEEN CONDUCTORS IN SEMICONDUCTOR PROCESS - A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd| 05-10-2012 | |
| 20120112276 | ANTI PUNCH-THROUGH LEAKAGE CURRENT METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND MANUFACTURING METHOD THEREOF - An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate. | 05-10-2012 |
| 20120091536 | CMOS STRUCTURE AND LATCH-UP PREVENTING METHOD OF SAME - A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants. | 04-19-2012 |
| 20120090648 | CLEANING METHOD FOR SEMICONDUCTOR WAFER AND CLEANING DEVICE FOR SEMICONDUCTOR WAFER - A cleaning method of a semiconductor wafer includes the following steps. A semiconductor wafer is provided. A cleaning solution is sprayed to the semiconductor wafer. The semiconductor wafer is driven to spin along a first direction for a first time. The semiconductor wafer is driven to spin along a second direction for a second time. The cleaning method can effectively clean the semiconductor wafer. A cleaning device for cleaning a semiconductor wafer is also provided. | 04-19-2012 |
| 20120088368 | METHOD OF SELECTIVELY REMOVING PATTERNED HARD MASK - A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask. | 04-12-2012 |
| 20120071004 | STRESS-ADJUSTING METHOD OF MOS DEVICE - A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress. | 03-22-2012 |
| 20120070952 | REMOVING METHOD OF A HARD MASK - A removing method of a hard mask includes the following steps. A substrate is provided. At least two MOSFETs are formed on the substrate. An isolating structure is formed in the substrate and located between the at least two MOSFETs. Each of the MOSEFTs includes a gate insulating layer, a gate, a spacer and a hard mask on the gate. A protecting structure is formed on the isolating structure and the hard mask is exposed from the protecting structure. The exposed hard mask is removed to expose the gate. | 03-22-2012 |
| 20120070948 | ADJUSTING METHOD OF CHANNEL STRESS - An adjusting method of channel stress includes the following steps. A substrate is provided. A metal-oxide-semiconductor field-effect transistor is formed on the substrate. The MOSFET includes a source/drain region, a channel, a gate, a gate dielectric layer and a spacer. A dielectric layer is formed on the substrate and covers the metal-oxide-semiconductor field-effect transistor. A flattening process is applied onto the dielectric layer. The remaining dielectric layer is removed to expose the source/drain region. A non-conformal high stress dielectric layer is formed on the substrate having the exposed source/drain region. | 03-22-2012 |
| 20120058634 | METHOD OF FABRICATING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE - A method of fabricating a CMOS device having high-k dielectric layer and metal gate electrode is provided. First, an isolation structure is formed in a substrate to define a first-type and a second-type MOS regions; an interfacial layer and a high-k dielectric layer are sequentially formed over the substrate; a first and a second cover layers are respectively formed over a portion of the high-k dielectric layer at the first-type MOS region and another portion of the high-k dielectric layer at the second-type MOS region; afterwards, an in-situ etching step is performed to sequentially etch the first and second cover layers using a first etching solution and to etch both the high-k dielectric layer and the interfacial layer using a second etching solution until the substrate is exposed. Wherein, the second etching solution is a mixed etching solution containing the first etching solution. | 03-08-2012 |
| 20120040535 | Semiconductor process - A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted. | 02-16-2012 |
| 20120034747 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively. | 02-09-2012 |
| 20120019279 | METHOD AND PATTERN CARRIER FOR OPTIMIZING INSPECTION RECIPE OF DEFECT INSPECTION TOOL - A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool. | 01-26-2012 |
| 20120018795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening. | 01-26-2012 |
| 20120009788 | CLEANING SOLUTION, CLEANING METHOD AND DAMASCENE PROCESS USING THE SAME - A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH | 01-12-2012 |
| 20120007249 | SILICON BASED SUBSTRATE AND MANUFACTURING METHOD THEREOF - A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided. | 01-12-2012 |
| 20120007198 | BACKSIDE ILLUMINATED IMAGE SENSOR - A backside illuminated (BSI) image sensor including a substrate, a plurality of photosensitive regions, a back-end-of-line (BEOL), a pad, a color filter array, a plurality of micro-lenses and a protection layer is provided. The substrate has a first surface and a second surface. The substrate has a pad opening therein through the first surface and the second surface. The photosensitive regions are disposed in the substrate. The BEOL is disposed on the first surface of the substrate. The pad is disposed in the BEOL and exposed by the pad opening. The color filter array is disposed on the second surface of the substrate. The micro-lenses are disposed on the color filter array. The protection layer at least covers the top corner and the sidewall of the pad opening. | 01-12-2012 |
| 20120003835 | METHOD OF ETCHING SACRIFICIAL LAYER - An exemplary method of etching sacrificial layer includes steps of: providing a substrate formed with a sacrificial layer and defined with a first region and a second region, the sacrificial layer disposed in both the first and second regions; forming a hard mask covering the first region while exposing the second region; performing a first etching process on the sacrificial layer to thin the sacrificial layer while forming a byproduct film overlying the thinned sacrificial layer; performing a second etching process on the byproduct film to remove a portion of the byproduct layer for exposing a portion of the thinned sacrificial layer, while another portion of the byproduct film disposed on sidewalls of the thinned sacrificial layer being remained; and performing a third etching process on the thinned sacrificial layer, to remove the portion of the thinned sacrificial layer exposed in the second etching process. | 01-05-2012 |
| 20110305977 | OPTICAL PROXIMITY CORRECTION PROCESS - An optical proximity correction process for designing a mask according to a target exposure intensity of each edge of a pattern is provided. Each edge is at a corresponding current edge position which corresponds to a current exposure intensity. The process comprises repeating a convergence process on each edge to determine an adjusted position for the edge until an adjusted exposure intensity of the edge is equal to the target exposure intensity. For each edge, the convergence process comprises comparing the target exposure intensity with the current exposure intensity to determine an in-position correlating to a first exposure intensity and an out-position correlating to a second exposure intensity, wherein the target exposure intensity is within a range between the first and the second exposure intensities. An interpolation is performed to obtain the adjusted position according to the target exposure intensity. The pattern is updated according to the adjusted position. | 12-15-2011 |
| 20110294287 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE - A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate. | 12-01-2011 |
| 20110294075 | PATTERNING METHOD - A patterning method of the present invention is described as follows. A mask layer and a patterned photoresist layer are formed on a target layer in sequence, wherein an etching rate of the mask layer is different from an etching rate of the target layer. A plurality of spacers is formed on sidewalls of the patterned photoresist layer respectively, wherein an etching rate of the spacers is different from the etching rate of the mask layer. The patterned photoresist layer is removed to form an opening between any two adjacent spacers. A portion of the mask layer is removed by using the spacers as a mask so as to form a patterned mask layer. A portion of the target layer is removed by using the patterned mask layer as a mask. | 12-01-2011 |
| 20110292565 | CAPACITOR STRUCTURE - A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level. | 12-01-2011 |
| 20110284035 | METHOD OF CLEANING TURBO PUMP AND CHAMBER/TURBO PUMP CLEAN PROCESS - A method of cleaning a turbo pump is described. The turbo pump is coupled with a CVD chamber of depositing a material and thus accumulates the material therein. The method includes switching off the turbo pump and using another pump to pump a reactive gas, which can react with the material to form gaseous products, through the turbo pump. Thereby, the turbo pump is cleaned up and is prevented from being a particle source in subsequent CVD operations. | 11-24-2011 |
| 20110264256 | PROCESS CONTROL METHOD AND PROCESS CONTROL SYSTEM - A process control method is provided for controlling a tool which processes a deposition process on a plurality of wafers for a process time. The process control method comprises receiving a quantity of the wafers and calculating a deposition compensation time necessary for the deposition process performed on the wafers by the tool according to the quantity of the wafers and a deposition loading effect coefficient corresponding to the deposition process. The deposition loading effect coefficient is retrieved from a database according to a process program of the deposition process. According to the deposition compensation time, the process time is adjusted to be an adjusted process time. The deposition process is performed on the wafers for the adjusted process time by the tool. | 10-27-2011 |
| 20110254064 | SEMICONDUCTOR DEVICE WITH CARBON ATOMS IMPLANTED UNDER GATE STRUCTURE - An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer. | 10-20-2011 |
| 20110244678 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased. | 10-06-2011 |
| 20110244642 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device utilizes a substrate including a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. A first well of a first conductivity type is formed. Two separate second wells of a second conductivity type are formed in the first well and two separate isolation structures are formed respectively in the second wells in each of the high voltage circuit area and the medium voltage circuit area. A first gate dielectric layer is formed in the high voltage circuit area. A second gate dielectric layer that is thinner than the first gate dielectric layer is formed in each of the medium voltage circuit area and the low voltage circuit area. A gate is formed. Two source and drain regions of the second conductivity type are respectively formed. The method is simple and low-cost and meets the market requirement. | 10-06-2011 |
| 20110244398 | Patterning method - A patterning method is provided. First, a first mask layer, a second mask layer and a patterned photoresist layer are sequentially formed on a target layer. Thereafter, the second mask layer is etched by using the patterned photoresist layer as a mask, so as to form a patterned second mask layer. Afterwards, a trimming process is performed to the patterned second mask layer. Further, the first mask layer is etched by using the trimmed patterned second mask layer as a mask, so as to form a patterned first mask layer. The patterned photoresist layer is then removed. Next, the target layer is etched by using the patterned first mask layer as a mask. | 10-06-2011 |
| 20110241212 | STRESS LAYER STRUCTURE - A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The active stress portion includes first and second active stress patterns in a region where active devices are formed. The first and second active stress patterns coverrespective active regions, and are separated from each other. The dummy stress portion includes a first dummy stress pattern formed directly on the substrate and disposed between and separated from the first and second active stress patterns. | 10-06-2011 |
| 20110198727 | ESD PROTECTION DEVICE - An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region. | 08-18-2011 |
| 20110198678 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event. | 08-18-2011 |
| 20110195571 | SEMICONDUCTOR PROCESS - A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer. | 08-11-2011 |
| 20110187487 | INDUCTOR FORMED ON A SEMICONDUCTOR SUBSTRATE - An inductor formed on a semiconductor substrate, comprising a coil formed with at least a single metal layer having a plurality of slots and an insulator layer filled in the plurality of slots, wherein the insulator layer is encompassed in the single metal layer and the insulator layer does not cover the top surface of the single metal layer. | 08-04-2011 |
| 20110186945 | MEMS DIAPHRAGM - A microelectromechanical system (MEMS) diaphragm is provided. The MEMS diaphragm includes a first conductive layer, a second conductive layer and a first dielectric layer. The first conductive layer is disposed on a substrate and having a plurality of openings. The openings have the same dimension, and the distance between the adjacent openings is gradually increased toward the edge of the first conductive layer. The second conductive layer is disposed between the first conductive layer and the substrate. The first dielectric layer is partially disposed between the first conductive layer and the second conductive layer, so that a portion of the first conductive layer is suspended. | 08-04-2011 |
| 20110169110 | MEMS DIAPHRAGM - A microelectromechanical system (MEMS) diaphragm is provided. The MEMS diaphragm includes a first conductive layer, a second conductive layer and a first dielectric layer. The first conductive layer is disposed on a substrate and having a plurality of openings. The openings having a first dimension and the openings having a second dimension are arranged alternately, and the first dimension is not equal to the second dimension. The second conductive layer is disposed between the first conductive layer and the substrate. The first dielectric layer is partially disposed between the first conductive layer and the second conductive layer, so that a portion of the first conductive layer is suspended. | 07-14-2011 |
| 20110158581 | OPTOELECTRONIC DEVICE AND METHOD OF FORMING THE SAME - An optoelectronic device including a substrate, a half-boat-shaped material layer, a deep trench isolation structure, and an optical waveguide is provided. The substrate has a first area. The half-boat-shaped material layer is disposed in the substrate within the first area. The refractive index of the half-boat-shaped material layer is lower than that of the substrate. A top surface of the half-boat-shaped material layer is coplanar with the surface of the substrate. The deep trench isolation structure is disposed in the substrate within the first area and located at one side of a bow portion of the half-boat-shaped material layer. The optical waveguide is disposed on the substrate within the first area. The optical waveguide overlaps a portion of the deep trench isolation structure and at least a portion of the half-boat-shaped material layer. | 06-30-2011 |
| 20110156161 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device. | 06-30-2011 |
| 20110156156 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor. | 06-30-2011 |
| 20110154929 | WAFER TRANSFER APPARATUS AND SHIELDING MECHANISM - A wafer transfer apparatus includes a main body, a wafer carrier, a linkage and a shielding mechanism. The linkage includes a first connecting rod and a pair of second connecting rods. The wafer carrier connects with a first side of the first connecting rod. A first terminal of each second connecting rod pivotedly connects with two ends of the first connecting rod. The shielding mechanism on the first connecting rod includes a shielding part and two fixing parts. The shielding part is configured at the first side of the first connecting rod for shielding a pivot joint between the first connecting rod and each second connecting rod. The fixing parts connect with both sides of the shielding part, and are respectively configured at a second and a third sides of the first connecting rod so as to fix the shielding part at the first side of the first connecting rod. | 06-30-2011 |
| 20110151597 | Analysis method for semiconductor device - An analysis method for a semiconductor device is described. The semiconductor device having an abnormal region is provided. Thereafter, a focused ion beam microscope analysis process is performed to the abnormal region, wherein the result of the focused ion beam microscope analysis process shows that the abnormal region has a defect therein. After the focused ion beam microscope analysis process, an electrical property measurement step is performed to the abnormal region, so as to determine whether the defect in the abnormal region is a device failure root cause or not. | 06-23-2011 |
| 20110147948 | FORMING METHOD AND STRUCTURE OF POROUS LOW-K LAYER, INTERCONNECT PROCESS AND INTERCONNECT STRUCTURE - A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer. | 06-23-2011 |
| 20110140206 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, a gate structure, a spacer and source/drain regions is provided. The gate structure is on the substrate, wherein the gate structure includes, from bottom to top, a high-k layer, a work function metal layer, a wetting layer and a metal layer. The spacer is on a sidewall of the gate structure. The source/drain regions are in the substrate beside the gate structure. | 06-16-2011 |
| 20110097033 | FOCUSING MEMBER AND OPTOELECTRONIC DEVICE - A focusing member and an optoelectronic device having the same are provided. The focusing member includes multiple levels of conductive plugs and multiple levels of conductive layers that together form an inversed half-boat shape. The optoelectronic device includes a bottom layer, an optical waveguide above the bottom layer, a dielectric layer covering the optical waveguide, and the above focusing member disposed at an edge of the optoelectronic device and located in the dielectric layer above the optical waveguide. A wider end of the inversed half-boat shape of the focusing member faces the outside of the optoelectronic device. The refractive indexes of the bottom layer and the dielectric layer are smaller than that of the optical waveguide. | 04-28-2011 |
| 20110079854 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively. | 04-07-2011 |
| 20110076601 | MONITORING METHOD OF EXPOSURE APPARATUS - In a monitoring method of an exposure apparatus, a top critical dimension (TCD) and a bottom critical dimension (BCD) of the test pattern formed on a photo-sensitive material layer are measured. A dose deviation (ΔE) and a focus deviation (ΔF) are calculated by following equations: | 03-31-2011 |
| 20110070702 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. A high dielectric constant (high-k) layer and a work function metal layer are formed in sequence on a substrate. A hard mask layer is formed on the work function metal layer, where the material of the hard mask layer is lanthanum oxide. The work function metal layer is patterned by using the hard mask layer as a mask. The hard mask layer is then removed. Afterwards, a gate structure is formed on the substrate. | 03-24-2011 |
| 20110068374 | INTEGRATED CIRCUIT HAVING MICROELECTROMECHANICAL SYSTEM DEVICE AND METHOD OF FABRICATING THE SAME - An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect. | 03-24-2011 |
| 20110061031 | METHOD FOR PRODUCING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT WITH RADIO FREQUENCY DEVICES - A method for producing a layout of a device in an integrated circuit before actually fabricated is provided. The method includes inputting at least one fixed parameter for the device for fabrication. And then, a first part of a set of variable parameters of a layout of the device is input. The complete set of the variable parameters is generated. It is checked whether or not the layout with the parameters is satisfying a requirement, wherein an end step is reached if the layout is accepted by the requirement, and a new part of the set of variable parameters as the first part being looping in the foregoing steps if the layout is not accepted by the requirement. | 03-10-2011 |
| 20110057288 | MEMS DEVICE AND METHOD FOR FABRICATING THE SAME - A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode. | 03-10-2011 |
| 20110053371 | SEMICONDUCTOR PROCESS - A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein. | 03-03-2011 |
| 20110053309 | METHOD FOR FABRICATING IMAGE SENSOR - A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array. | 03-03-2011 |
| 20110043268 | LEVEL SHIFTER WITH NATIVE DEVICE - A level shifter includes an inverter, a first native device, a second native device, a first transistor, and a second transistor. First ends of the first and the second transistors are coupled to a first voltage. A second end and a control end of the first transistor are respectively coupled to the first ends of the first and the second native devices. A second end and a control end of the second transistor are respectively coupled to the first ends of the second and the first native devices. A second end and a control end of the first native device are respectively coupled to an output end and an input end of the inverter. A second end and a control end of the second native device are respectively coupled to the input end and the output end of the inverter. | 02-24-2011 |
| 20110021021 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE - A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed. | 01-27-2011 |
| 20110020994 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer. | 01-27-2011 |
| 20110014784 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. First, a substrate having a dielectric layer formed thereon is provided. Thereafter, an interconnection structure including copper is formed in the dielectric layer. Afterwards, a metal layer is formed on the dielectric layer. The metal layer is then patterned to form a pad. An annealing process is performed, wherein the gas source for the annealing process includes hydrogen in a concentration of 50% to 90%. | 01-20-2011 |
| 20110012229 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND METHOD OF FABRICATING THE SAME - A capacitor, comprising a substrate, a first electrode and a second electrode is provided. The first electrode is located over a substrate. The second electrode is located over the first electrode and overlapping with a portion of the first electrode. The dielectric layer is located between the first electrode and the second electrode and a portion of the first electrode, a portion of the dielectric layer and a portion of the second electrode, which overlap each other, are together form the capacitor. The first electrode is electrically connected to a first metal interconnects, the second electrode is electrically connected to a second metal interconnects underneath the second electrode and no via for being electrically connected to the second electrode is located over the second electrode. | 01-20-2011 |
| 20110008960 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer. | 01-13-2011 |
| 20110001196 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate of a first conductive type, a first doped region of a second conductive type, at least one second doped region of the first conductive type, a third doped region of the second conductive type, a gate structure, and at least one contact. The first and the second doped regions are configured in the substrate, and each second doped region is surrounded by the first doped region. The third doped region is configured in the substrate outside of the first doped region. The gate structure is disposed on the substrate between the first and third doped regions. The contact is disposed on the substrate. Each contact connects, in a direction parallel to the gate structure, the first and second doped regions alternately. | 01-06-2011 |
| 20100327378 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area. | 12-30-2010 |
| 20100317138 | METHOD FOR FABRICATING MEMS STRUCTURE - A method for fabricating a MEMS is described as follows. A substrate is provided, including a circuit region and an MEMS region separated from each other. A first metal interconnection structure is formed on the substrate in the circuit region, and simultaneously a first dielectric structure is formed on the substrate in the MEMS region. A second metal interconnection structure is formed on the first metal interconnection structure, and simultaneously a second dielectric structure, at least two metal layers and at least one protection ring are formed on the first dielectric structure. The metal layers and the protection ring are formed in the second dielectric structure and the protection ring connects two adjacent metal layers to define an enclosed space between two adjacent metal layers. The first dielectric structure and the second dielectric structure outside the enclosed space are removed to form an MEMS device in the MEMS region. | 12-16-2010 |
| 20100295157 | ESD PROTECTION DEVICE - An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure. | 11-25-2010 |
| 20100289117 | SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING SECOND LINER COVERING CORNER OF TRENCH AND FIRST LINER - A STI structure disposed in a trench of a substrate is provided. The STI structure includes a first liner, a second liner and an insulation layer. The first liner is disposed on sidewalls of the trench, and a top of the first liner is lower than a surface of the substrate. The second liner covers the trench and the first liner. The second liner and the first liner may constitute with different materials. The insulation layer is disposed on the second liner to fill up the trench. | 11-18-2010 |
| 20100271750 | CAPACITOR STRUCTURE - A capacitor structure is provided. The capacitor structure comprises a plurality of parallel conductive line levels and a plurality of vias. Each conductive line level comprises first conductive lines parallel to each other and second conductive lines parallel to each other. Also, the first conductive lines on different conductive line levels are aligned to each other and the second conductive lines on different conductive line levels are aligned to each other so as to form first conductive line co-planes and second conductive line co-planes. The vias are located on the conductive line co-planes and between the conductive line levels for connecting the conductive lines on the neighboring conductive line levels. The vias, on a height level of each of the conductive line co-planes, are arranged only on one of the neighboring conductive line co-planes. | 10-28-2010 |
| 20100240190 | METHOD FOR FABRICATING DEEP TRENCH CAPACITOR - A method for fabricating the deep trench capacitor is described as follows. A substrate of a first conductivity type is provided, which includes a deep band region of a second conductivity type therein. A deep trench is formed in the substrate and through the deep band region. A collar oxide is then formed in an upper portion of the trench, wherein at least a portion of the deep band region is exposed. A bottom electrode, a capacitor dielectric layer and a top electrode are formed in the trench sequentially. | 09-23-2010 |
| 20100240181 | Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage - First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc. | 09-23-2010 |
| 20100227131 | TEST PATTERN STRUCTURE - A test pattern structure including a first conductive layer and a second conductive layer is provided. The second conductive layer is directly disposed on the first conductive layer and connected to the first conductive layer through a plurality of connection interfaces. The test pattern structure of the present invention can detect the interconnection failure quickly and correctly without SEM identification. | 09-09-2010 |
| 20100211372 | METHOD AND SIMULATOR FOR GENERATING PHASE NOISE IN SYSTEM WITH PHASE-LOCKED LOOP - A method and simulator for generating phase noise in a system with a phase-locked loop are disclosed. Each simulation block of the system with the PLL has its own predefined phase noise vector whose elements are injected consecutively at a trigger event. An element selection of the predefined noise vector of is steered from the master element block, which is usually the voltage or current-controlled oscillator. Some simulation blocks, called semi-master element blocks, are self-triggered and determines their own injection frequency rates, or are reset-steered and aligned with the master element block a capturing data phase starts; while other simulation blocks, called slave element blocks, are directly steered with the master element block. | 08-19-2010 |
| 20100207686 | VOLTAGE GENERATING APPARATUS - A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET). | 08-19-2010 |
| 20100190272 | REWORK METHOD OF METAL HARD MASK - A rework method of a metal hard mask layer is provided. First, a material layer is provided. A dielectric layer, a first metal hard mask layer, and a patterned first dielectric hard mask layer have been sequentially formed on the material layer. There is a defect on a region of the first metal hard mask layer, and therefore the region of the first metal hard mask layer is not able to be patterned. After that, the patterned first dielectric hard mask layer and the first metal hard mask layer are removed. A planarization process is then performed on the dielectric layer. Next, a second metal hard mask layer and a second dielectric hard mask layer are sequentially formed on the dielectric layer. | 07-29-2010 |
| 20100184293 | PLANARIZATION PROCESS FOR PRE-DAMASCENE STRUCTURE INCLUDING METAL HARD MASK - A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask. | 07-22-2010 |
| 20100171165 | NON-VOLATILE MEMORY - A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region. | 07-08-2010 |
| 20100170530 | METHOD FOR CLEANING SEMICONDUCTOR EQUIPMENT - A method for cleaning a semiconductor equipment is provided. First, a first cleaning step is performed to the process chamber. The first cleaning step includes conducting a cleaning gas into the process chamber via a short processing gas injector for generating a plasma of the cleaning gas in the process chamber. Then, a cleaning step is performed to a long cleaning gas injector. The cleaning step performed to the long cleaning gas injector includes conducting the cleaning gas into the process chamber via the long processing gas injector. Then, a second cleaning step is performed to the process chamber. The second cleaning step includes conducting the plasma of the cleaning gas into the process chamber via the short processing gas injector. | 07-08-2010 |
| 20100148265 | ESD PROTECTION DEVICE - An ESD protection device includes a substrate of a first conductivity type, a well region of a second conductivity type, a first doped region of the second conductivity type, a second doped region of the first conductivity type, a third doped region of the second conductivity type, a fourth doped region of the first conductivity type. The well region is configured in the substrate. The first doped region is configured in the well region. The second doped region is configured in the well region and surrounding the first doped region. The third doped region is configured in the well region and surrounding the first doped region and the second doped region. The fourth doped region is configured in the well region and under the first doped region and the second doped region. The fourth doped region is coupled with the first doped region and with the second doped region, respectively. | 06-17-2010 |
| 20100148264 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING THE SAME - An ESD protection device including a substrate, a gate structure, a source region, a drain region and a first implanted region is provided. The gate structure includes a gate dielectric layer and a gate sequentially disposed on the substrate. The source region and the drain region are disposed in the substrate beside the gate structure. The first implanted region has the same conductivity type as the drain region. The first implanted region is disposed below the drain region, and the border thereof does not exceed the border of the drain region. | 06-17-2010 |
| 20100148263 | SEMICONDUCTOR DEVICE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate. | 06-17-2010 |
| 20100148250 | METAL OXIDE SEMICONDUCTOR DEVICE - A metal oxide semiconductor device comprising a substrate, at least an isolation structure, a deep N-type well, a P-type well, a gate, a plurality of N-type extension regions, an N-type drain region, an N-type source region and a P-type doped region is provided. The N-type extension regions are disposed in the substrate between the isolation structures and either side of the gate, while the N-type drain region and the N-type source region are respectively disposed in the N-type extension regions at both sides of the gate. The P-type well surrounds the N-type extension regions, and the P-type doped region is disposed in the P-type well of the substrate and is isolated from the N-type source region by the isolation structure. | 06-17-2010 |
| 20100140741 | STRUCTURE OF CAPACITOR SET - A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array. | 06-10-2010 |
| 20100136759 | METHOD OF FABRICATING A DYNAMIC RANDOM ACCESS MEMORY - A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area. | 06-03-2010 |
| 20100135093 | OPERATING VOLTAGE TUNING METHOD FOR STATIC RANDOM ACCESS MEMORY - An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution. | 06-03-2010 |
| 20100133594 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure including a substrate, a gate dielectric layer, a gate, a source region and a drain region is provided. The gate dielectric layer is disposed on the substrate. At least one recess is disposed in the substrate. The gate is disposed on the gate dielectric layer and in the recess. The source and drain regions are respectively disposed in the substrate beside the gate. | 06-03-2010 |
| 20100133503 | PHASE CHANGE MEMORY - A phase change memory is provided, which includes a semiconductor substrate having a first conductive type, buried word lines having a second conductive type, doped semiconductor layers having the first conductive type, memory cells, metal silicide layers, and bit lines. The buried word lines are disposed in the semiconductor substrate. Each buried word line includes a line-shaped main portion extended along a first direction and protrusion portions. Each protrusion portion is connected to one long side of the line-shaped main portion. Each doped semiconductor layer is disposed on one protrusion portion. Each memory cell includes a phase change material layer and is disposed on and electrically connected to one of the doped semiconductor layers. Each metal silicide layer is disposed on one of the line-shaped main portions. Each bit line is connected to memory cells disposed on the word lines in a second direction substantially perpendicular to the first direction. | 06-03-2010 |
| 20100109081 | SEMICONDUCTOR DEVICE AND IC CHIP - A semiconductor device and an IC chip are described. The deep N-well region is configured in a substrate. The P-well region surrounds a periphery of the deep N-well region. The gate structure is disposed on the substrate of the deep N-well region. The P-body region is configured in the deep N-well region at one side of the gate structure. The first N-type doped region is configured in the P-body region. The second N-type doped region is configured pin the deep N-well region at the other side of the gate structure. The first isolation structure is disposed between the gate structure and the second N-type doped region. The N-type isolation ring is configured in the deep N-well region and corresponding to an edge of the deep N-well region, wherein a doping concentration of the N-type isolation ring is higher than that of the deep N-well region. | 05-06-2010 |
| 20100105205 | CLEANING SOLUTION AND SEMICONDCUTOR PROCESS USING THE SAME - A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. | 04-29-2010 |
| 20100105157 | PROCESS OF MICRO-DISPLAY - A process of a micro-display is provided. First, a substrate having a pixel region and a periphery circuit region is provided, in which a metal reflection layer is formed in the pixel region, and a periphery circuit is formed in the periphery circuit region. Next, a dielectric layer is formed on the substrate to cover the pixel region and the periphery circuit region. Then, a patterned mask layer exposing the dielectric layer on the metal reflection layer is formed on the dielectric layer. Thereafter, a portion of the exposed dielectric layer is removed by using the patterned mask layer as a mask. Next, the patterned mask layer is removed. And then, a portion of the dielectric layer is removed to expose the metal reflection layer. | 04-29-2010 |
| 20100102379 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - A LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, two body regions of the first conductivity type, a body connection region of the first conductivity type, two source regions of the second conductivity type, a drain region of the second conductivity type, a channel region, and a gate electrode. The body regions are disposed in the deep well region configured in the substrate. The body connection region is disposed in the deep well region to connect the body regions. Each of the source regions is disposed in the body region. The drain region is disposed in the deep well between the source regions. The channel region is disposed in a portion of the body region. The gate electrode is disposed on the deep well region between the source regions and the drain region and covers the channel region. | 04-29-2010 |
| 20100096702 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage device, the medium voltage device and the low voltage device are respectively disposed in the high voltage circuit area, the medium voltage circuit area and the low voltage circuit area. The medium voltage device and the high voltage device have the same structure while the medium voltage device and the low voltage device have different structures. Further, the high voltage device, the medium voltage device and the low voltage device respectively include a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer. | 04-22-2010 |
| 20100093169 | THROUGH SUBSTRATE VIA PROCESS - A through substrate via (TSV) process is provided. A substrate having a first side and a second side opposite the first side is provided. A plurality of holes is formed in the substrate at the first side. A first dielectric layer is formed on a sidewall and a bottom of the holes. A second dielectric layer is formed in the holes, wherein a material of the second dielectric layer is different from that of the first dielectric layer. A semiconductor device and an interconnect are formed on the substrate at the first side. At least a portion of the substrate at the second side is removed to expose the second dielectric layer in the holes. The second dielectric layer is removed. A conductive layer is formed in the holes. | 04-15-2010 |
| 20100090749 | MULTI-FUNCTION CHIP - A multi-function chip including a circuit and at least one control circuit is provided. The circuit having multiple functions includes an interconnection. The interconnection has at least one resistance-variable segment. The control circuit is electronically connected to the resistance-variable segment. One of the functions is carried out by adjusting the resistance of the resistance-variable segment with the control circuit. | 04-15-2010 |
| 20100090298 | MEMS DIAPHRAGM - A microelectromechanical system (MEMS) diaphragm is provided. The MEMS diaphragm includes a first conductive layer, a second conductive layer and a dielectric layer. The first conductive layer is disposed on a substrate and having a plurality of openings. The dimenisons of the openings are gradually reduced toward the edge of the first conductive layer. The second conductive layer is disposed between the first conductive layer and the substrate. The dielectric layer is partially disposed between the first conductive layer and the second conductive layer, so that a portion of the first conductive layer is suspended. | 04-15-2010 |
| 20100086862 | MASK PATTERN CORRECTION AND LAYOUT METHOD - A mask pattern correction method is provided. The method comprises the following steps. An original layout, which has a plurality of device patterns, is provided. Then, a simulation process is performed on the device patterns to correspondingly form a plurality of simulated patterns. Thereafter, the simulated patterns are analyzed to select a plurality of unsaturated patterns from the simulated patterns. Finally, the device patterns in the original layout corresponding to the unsaturated patterns respectively are rotated. | 04-08-2010 |
| 20100085033 | ION CURRENT MEASUREMENT DEVICE - The invention provides an ion current measurement device for a tool having an ion source. The ion current measurement device comprises an ion collecting cup and a replaceable liner. The ion collecting cup is disposed in the tool and the ion collecting cup possesses a cup opening facing the ion source. The replaceable liner is disposed in the ion collecting cup and the replaceable liner entirely covers a continuous inner sidewall of the ion collecting cup. | 04-08-2010 |
| 20100076584 | SAMPLING INSPECTION METHOD - A sampling inspection method is provided. The sampling inspection method is adapted for a multi-product production line including a plurality of tools. The sampling inspection method includes the steps of: providing a tool record, which records a sampling data of each of the tools; then checking each sampling data recorded in the tool record, and finding out at least one unsampled tool from the tools; then defining a plurality of product lots as being performed with process operations by at least one of the at least one unsampled tool; and determining at least one of the product lots for performing a sampling inspection. | 03-25-2010 |
| 20100074458 | STRUCTURE OF MEMS ELECTROACOUSTIC TRANSDUCER AND FABRICATING METHOD THEREOF - A structure of a micro-electro-mechanical systems (MEMS) electroacoustic transducer includes a substrate, a diaphragm, a silicon material layer, and a conductive pattern. The substrate includes an MEMS device region. The diaphragm has openings, and is disposed in the MEMS device region. A first cavity is formed between the diaphragm and the substrate. The silicon material layer is disposed on the diaphragm and seals the diaphragm. The conductive pattern is disposed beneath the diaphragm in the MEMS device region. | 03-25-2010 |
| 20100072624 | METAL INTERCONNECTION - A metal interconnection including a substrate, a first conductive structure, a second conductive structure, a complex plug and a plug is provided. The substrate includes a first region and a second region. The first conductive structure is disposed on the first region. The second conductive structure is disposed on the second region. The complex plug is disposed on the first conductive structure and includes a tungsten layer and a plurality of insulator columns, wherein an extended direction of each of the insulator columns is perpendicular to a surface of the substrate and the tungsten layer is electrically connected with the first conductive structure. The plug is disposed on the second conductive structure and electrically connected with the second conductive structure. | 03-25-2010 |
| 20100070944 | METHOD FOR CONSTRUCTING OPC MODEL - A method for constructing an optical proximity correction (OPC) model is described. A test pattern is provided, and the test pattern is then written on a mask. The pattern on the mask is measured to obtain a modified pattern. An OPC model is constructed according to the modified pattern. | 03-18-2010 |
| 20100067728 | MICROELECTROMECHANICAL SYSTEM MICROPHONE STRUCTURE AND MICROELECTROMECHANICAL SYSTEM MICROPHONE PACKAGE STRUCTURE - A microelectromechanical system microphone structure including a substrate, a first device and at least one second device is provided. The first device is disposed on the substrate and including a first upper electrode and a first lower electrode disposed between the first upper electrode and the substrate. The second device is disposed on the substrate, surrounding the first device and including a second upper electrode and a second lower electrode disposed between the second upper electrode and the substrate. The second upper electrode includes a plurality of first conductive layers and first plugs. The first conductive layers are arranged in steps, and the first plug is disposed between the adjacent first conductive layers. The second lower electrode includes a plurality of second conductive layers and a plurality of second plugs. The second conductive layers are arranged in steps, and the second plug is disposed between the adjacent second conductive layers. | 03-18-2010 |
| 20100052179 | MEMS STRUCTURE AND METHOD FOR FABRICATING THE SAME - A microelectromechanical system (MEMS) structure and a fabricating method thereof are described. The MEMS structure includes a fixed part and a movable part. The fixed part is disposed on and connects with a substrate. The movable part including at least two first metal layers, a first protection ring and a first dielectric layer is suspended on the substrate. The first protection ring connects two adjacent first metal layers, so as to define a first enclosed space between the two adjacent first metal layers. The first dielectric layer is disposed in the enclosed space and connects the two adjacent first metal layers. | 03-04-2010 |
| 20100044147 | MICROELECTROMECHANICAL SYSTEM DIAPHRAGM AND FABRICATING METHOD THEREOF - A microelectromechanical system diaphragm is provided. The microelectromechanical system diaphragm includes a substrate, a first conductive layer, a second conductive layer, a first dielectric layer, and a second dielectric layer. The first conductive layer is disposed on the substrate. The first conductive layer has a flexible portion in which a plurality of trenches is formed. The second conductive layer is disposed between the first conductive layer and the substrate, in which the flexible portion is located above the second conductive layer. The first dielectric layer is disposed between the second conductive layer and the substrate. The second dielectric layer is disposed between the substrate and a portion of the first conductive layer so as to suspend the flexible portion. Furthermore, at least one first opening is formed in the first conductive layer. | 02-25-2010 |
| 20100043701 | BUFFER APPARATUS AND THIN FILM DEPOSITION SYSTEM - A buffer apparatus and a thin film deposition system are provided. The buffer apparatus is connected between a liquid material supply apparatus and a deposition machine. The buffer apparatus includes a container and a baffle. The container is used for containing a liquid material supplied from the liquid material supply apparatus. The top of the container has an input hole and an output hole. The baffle is disposed in the container and located under the input hole. | 02-25-2010 |
| 20100043160 | WAFER CLEANING ROLLER - A wafer cleaning roller including a tube body and a plurality of first protrusions is provided. The tube body has a longitudinal direction. The first protrusions are disposed on the outside surface of the tube body. Each of the first protrusions is shaped as a stripe having a first extension direction. The included angle between the first extension direction and the longitudinal direction is an oblique angle. | 02-25-2010 |
| 20100032758 | LDMOS DEVICE FOR ESD PROTECTION CIRCUIT - A LDMOS device for an ESD protection circuit is provided. The LDMOS device includes a substrate of a first conductivity type, a deep well region of a second conductivity type, a body region of the first conductivity type, first and second doped regions of the second conductivity type, and a gate electrode. The deep well region is disposed in the substrate. The body region and the first doped region are respectively disposed in the deep well region. The second doped region is disposed in the body region. The gate electrode is disposed on the deep well region between the first and second doped regions. It is noted that the body region does not include a doped region of the first conductivity type having a different doped concentration from the body region. | 02-11-2010 |
| 20100020991 | DIAPHRAGM OF MEMS ELECTROACOUSTIC TRANSDUCER - A diaphragm of an MEMS electroacoustic transducer including a first axis-symmetrical pattern layer is provided. Because the layout of the first axis-symmetrical pattern layer can match the pattern of the sound wave, the vibration uniformity of the diaphragm can be improved. | 01-28-2010 |
| 20100019318 | DEVICE FOR ESD PROTECTION CIRCUIT - A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region. | 01-28-2010 |
| 20100018944 | PATTERNING METHOD - A patterning method is provided. A patterned photoresist layer is formed on a bottom anti-reflective coating (BARC), having therein an opening exposing a portion of the BARC. The patterned photoresist layer is treated with a first plasma-generating gas including a fluorocarbon species to form a polymer layer on the surface of the PR layer and the sidewall of the opening. The patterned photoresist layer is used as a mask to etch the BARC with a second plasma-generating gas, which includes Ar and H | 01-28-2010 |
| 20100013105 | METHOD OF MANUFACTURING PHOTOMASK AND METHOD OF REPAIRING OPTICAL PROXIMITY CORRECTION - A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data. | 01-21-2010 |
| 20100003623 | METHOD OF PATTERNING MULTIPLE PHOTOSENSITIVE LAYERS - A method of patterning multiple photosensitive layers is provided. A first photosensitive layer is formed on a substrate. The first photosensitive layer is exposed by using a first mask. A second photosensitive layer is formed on the first photosensitive layer. The second photosensitive layer is exposed by using a second mask, wherein the second mask is different from the first mask. A first development process is performed to the exposed first and second photosensitive layers to form a plurality of patterns on the substrate. | 01-07-2010 |
| 20100003403 | PHOTORESIST COATING PROCESS - A photoresist coating process including a first step and a second step is provided. In the first step, a wafer is accelerated by a first average acceleration. In the second step, the wafer is accelerated by a second average acceleration. The first acceleration and the second acceleration are both larger than zero, and photoresist material is provided to the wafer only in the second step. | 01-07-2010 |
| 20090325086 | COLOR FILTER AND METHOD OF FABRICATING THE SAME - A method of fabricating a color filter having a target transmittance distribution is provided. First, a substrate having a first photodetector thereon is provided. Thereafter, a first pixel having a first transmittance distribution is formed on the substrate. The method of forming the first pixel includes forming a first organic color photoresist layer on the first photodetector, and then forming a second organic color photoresist layer on the first organic color photoresist layer, wherein the first and second organic color photoresist layers have different transmittance distributions. | 12-31-2009 |
| 20090321870 | SHUTTLE WAFER AND METHOD OF FABRICATING THE SAME - A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the wafer. After that, a shuttle mask having a number of IC designs is provided. A first IC design corresponds to a first die of each of the shots. A portion of the IC designs on the shuttle mask is covered for exposing the first IC design. Thereafter, the first IC designs of the shuttle mask are transferred onto the material layer, so as to form at least an effective IC pattern on the first die of each of the shots and to form an ineffective IC pattern on each of the other dies of each of the shots. | 12-31-2009 |
| 20090321862 | IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method for fabricating an image sensor, which includes the following steps, is provided. A semiconductor substrate including a sensor array, a pad and a passivation layer is provided, and the passivation layer covers the sensor array and the pad. An opening, which comprises tapered sidewalls not perpendicular to a bared surface of the pad, is formed in the semiconductor substrate to expose the pad. An under layer is formed on the semiconductor substrate, and covers the pad and the passivation layer. A color filter array is formed on the under layer and over the corresponding sensor array. A planar layer is formed on the color filter array. A portion of the under layer is removed to expose the pad. A plurality of U-lenses is formed on the planar layer. | 12-31-2009 |
| 20090305451 | MANUFACTURING METHOD OF WAFER LEVEL CHIP SCALE PACAKGE OF IMAGE-SENSING MODULE - A manufacturing method of a wafer level chip scale package of an image-sensing module is provided. The method includes providing. a wafer having a plurality of die regions, and a plurality of sensing units is formed on a surface of the wafer in each die region. A plurality of lens units is formed on the sensing units, wherein each lens unit includes a lens and an edge wall that are integrally formed. A light-shielding film is also formed on a surface of at least one edge wall of at least one lens units. A dicing process is then performed on the wafer to form a plurality of image sensor chips. | 12-10-2009 |
| 20090298294 | METHOD FOR CLEARING NATIVE OXIDE - A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF | 12-03-2009 |
| 20090298216 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. First, a first electrode is formed over a first region of a substrate. Then, a dielectric layer covering the first electrode is formed over the substrate. After that, a plurality of openings is formed on the first region of the substrate. Thereafter, a conductive layer covering the dielectric layer and the openings is formed over the substrate. Then, the conductive layer in the bottom of the openings is removed to form second electrodes. After that, the dielectric layer between the second electrode and the first electrode is removed. | 12-03-2009 |
| 20090294994 | BOND PAD STRUCTURE - A bond pad structure located over an active circuit structure is disclosed. The bond pad structure includes a bond pad, a passivation layer and a topmost metal layer in the active circuit structure. The passivation layer covers the bond pad and has an opening, and the opening exposes a part of the bond pad. The part of the topmost metal layer located under the opening serves as a supporting layer. The supporting layer has at least a slot, and the topmost metal layer is electrically connected to the bond pad through a plurality of via plugs. | 12-03-2009 |
| 20090294903 | ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME - An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer. | 12-03-2009 |
| 20090285419 | MICROELECTROMECHANICAL SYSTEM MICROPHONE - A microelectromechanical system microphone is provided. The microelectromechanical system microphone includes a first electrode, a second electrode and a first dielectric layer. The first electrode is disposed on a substrate and has a first flexible portion. The second electrode is disposed between the first electrode. A material of the second electrode includes polysilicon or polycide. The first dielectric layer is at least partially disposed between the first and second electrodes so as to suspend the first flexible portion. | 11-19-2009 |
| 20090283916 | CHIP STRUCTURE AND METHOD OF REWORKING CHIP - A method of reworking a chip includes providing a first chip and a second chip. The first and second chips have at least one first module and at least one second module, respectively. The first and second modules electrically connect with each other. The first module of the first chip has a defect. The second module of the second chip has a defect. The first module having a defect of the first chip is opened with the second module of the first chip, and the second module having a defect of the second chip is opened with the first module of the second chip. The first and second chips are stacked, and the second module of the first chip is electrically connects with the first module of the second chip. | 11-19-2009 |
| 20090278168 | STRUCTURE OF SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure is provided in a substrate having a first conductive type. A well region formed within the substrate has a second conductive type. A first dopant region formed within the substrate and the well region has the first conductive type. A second dopant region formed within the substrate and a portion of the well region has the second conductive type. A third dopant region formed under the second dopant region has the first conductive type, in which the second and the third regions form a vertical Zener diode. A fourth dopant region formed within the substrate and separated from the second dopant region by a separation structure has the second conductive type. A fifth dopant region is formed within the substrate in a manner that the fourth dopant region is between the isolation structure and the fifth dopant region, and has the first conductive type. | 11-12-2009 |
| 20090261401 | NON-VOLATILE MEMORY CELL AND METHOD OF FABRICATING THE SAME - A non-volatile memory cell is described, including a semiconductor substrate, two separate charge trapping structures on the substrate, first spacers at least on the opposite sidewalls of the two charge trapping structures, a gate dielectric layer on the substrate between the two charge trapping structures, a gate on the two charge trapping structures and the gate dielectirc layer, and two doped regions in the substrate beside the gate. | 10-22-2009 |
| 20090261393 | COMPOSITE TRANSFER GATE AND FABRICATION THEREOF - A composite transfer gate is described, which is disposed over a semiconductor substrate between an electron reservoir and a floating node in the semiconductor substrate. The composite transfer gate includes at least one N-type portion and a P-type portion that are arranged laterally. | 10-22-2009 |
| 20090259330 | METHOD OF CONTROLLING RESULT PARAMETER OF IC MANUFACTURING PROCEDURE - A method of controlling a result parameter of an IC manufacturing procedure is described. The value of at least one first variable of a process correlated with the result parameter is acquired, and the difference between the predicted value and the target value of the result parameter is calculated from the same using a correlation equation of the first variable and the result parameter. A correcting action is then performed to a subsequent process including at least one second variable correlated with the result parameter, which is based on a correlation equation of the second variable and the result parameter to control the subsequent process and adjust the second variable such that the difference is reduced due to the affect of the second variable to the result parameter. The at least one first variable and the at least one second variable include two or more different physical quantities. | 10-15-2009 |
| 20090256160 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure. | 10-15-2009 |
| 20090250754 | PARTIALLY DEPLETED SILICON-ON-INSULATOR METAL OXIDE SEMICONDUCTOR DEVICE - A partially depleted silicon-on-insulator metal oxide semiconductor (PD-SOI MOS) device is provided. The PD-SOI MOS device includes a gate structure on a silicon-on-insulator substrate, source and drain regions in the silicon-on-insulator substrate beside the gate structure and a silicon dislocation leakage path in an interface of the source region and the silicon-on-insulator substrate. | 10-08-2009 |
| 20090243030 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - A method of fabricating an isolation structure and the structure thereof is provided. The method is compatible with the embedded memory process and provides the isolation structure with a poly cap thereon to protect the top corners of the isolation structure, without using an extra photomask. | 10-01-2009 |
| 20090242997 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 10-01-2009 |
| 20090239347 | METHOD OF FORMING MOS DEVICE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 09-24-2009 |
| 20090224336 | SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of doped regions, a metal layer and a polysilicon layer is provided. The doped regions are disposed in a substrate. The metal layer includes a plurality of metal line patterns. The polysilicon layer disposed between the substrate and the metal layer includes a gate pattern and at least one guard ring pattern. The at least one guard ring pattern connects to the gate pattern and surrounds at least one of the metal line patterns. One of the metal line patterns connects to the gate pattern. The others of the metal line patterns connect to one of the doped regions in the substrate. | 09-10-2009 |
| 20090218679 | CHIP PACKAGE AND PROCESS THEREOF - A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside. The bond pads are disposed on the active surface and the bond pads are arranged to be corresponding to the recesses respectively. The connecting lines are disposed on surfaces of the recesses respectively at the edge of the chip. For each of the connecting lines, a first end of the connecting line is connected to one of the bond pads and a second end of the connecting line extends to the backside to be a terminal pad. The rigid cover is located on the active surface without covering the bond pads on the active surface. | 09-03-2009 |
| 20090212868 | LOW POWER COMSUMPTION, LOW NOISE AND HIGH POWER GAIN DISTRIBUTED AMPLIFERS FOR COMMUNICATION SYSTEMS - Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed. | 08-27-2009 |
| 20090212368 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same. | 08-27-2009 |
| 20090212335 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method of fabricating a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. First, an isolation structure is formed in a substrate with a photo-sensitive region and a transistor device region in the substrate. The transistor device region includes at least a region for forming a transfer transistor. A dielectric layer and a conductive layer are sequentially formed on the substrate. An ion implantation process is performed to implant a dopant into the substrate below the position for forming a gate of the transfer transistor and in the photo-sensitive region through the conductive layer and the dielectric layer. The conductive layer and the dielectric layer are patterned to at least form the gate structure of the transfer transistor on the transistor device region. Thereafter, a photo diode is formed in the substrate in the photo-sensitive region. | 08-27-2009 |
| 20090206384 | ILLUMINATING EFFICIENCY-INCREASABLE AND LIGHT-ERASABLE MEMORY - An illuminating efficiency-increasable and light-erasable memory including a substrate, a memory device, many dielectric layers, and many cap layers is provided. The substrate includes a memory region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have an opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively. | 08-20-2009 |
| 20090205686 | WAFER CLEANING APPARATUS - A wafer cleaning apparatus used for cleaning a first uncleaned surface of a wafer is provided. The wafer cleaning apparatus includes a case, a spin device, a cover, at least one first spray bar, and at least one exhaust device. The spin device is disposed in the case and used for carrying the wafer and spinning perpendicularly to the ground. The cover is disposed in the case and used for covering the spin device. The first spray bar is disposed at one side of the spin device and used for spraying a volatile cleaning solution onto the first uncleaned surface of the wafer, in which the sprayed volatile cleaning solution is of a bar shape. The exhaust device is disposed on the sidewall of the case. | 08-20-2009 |
| 20090190703 | SAMPLING METHOD AND DATA RECOVERY CIRCUIT USING THE SAME - A sampling method and a data recovery circuit using the same are provided. The sampling method includes following steps. First, a first strobe, a second strobe, a third strobe, and a fourth strobe are provided, wherein the second strobe lags the first strobe a first predetermined phase, the third and the fourth strobe respectively lag the first and the second strobe a second predetermined phase, and the second predetermined phase is half of the first predetermined phase. Then, a digital signal is respectively sampled with the first and the second strobe. Thereafter, the positions of data transition points of the digital signal are determined according to the sampling results of the first and the second strobe. Next, the third or the fourth strobe is selected as a preferable sampling strobe according to the determination result. Finally, the digital signal is sampled with the preferable sampling strobe. | 07-30-2009 |
| 20090186428 | METHOD FOR CONSTRUCTING MODULE FOR OPTICAL CRITICAL DIMENSION (OCD) AND MEASUREING METHOD OF MODULE FOR OPTICAL CRITICAL DIMENSION USING THE MODULE - An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve. | 07-23-2009 |
| 20090184834 | SYSTEM AND METHOD FOR MONITORING STEP MOTOR - A method for monitoring a step motor is provided, wherein the step motor rotates from a start position to an end position and then back to the start position repeatedly. The monitoring method includes: detecting a status signal of the step motor and a command signal received by the step motor in real time; recording a variation of the difference between the command signal and the status signal vs. time as an error data; and determining whether the step motor is starting from the start position, in action, reaching the end position, or returning to the start position according to the status signal and the command signal. If it is determined that the step motor is in action, the error data is recorded as a tracking error, and whether an alarm is issued is determined according to the tracking error. | 07-23-2009 |
| 20090184402 | METHOD OF FABRICATING A SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING FORMING A SECOND LINER COVERING THE CORNER OF THE TRENCH AND FIRST LINER. - A method of fabricating a shallow trench isolation structure is provided. First, a pad oxide layer and a mask layer are formed sequentially on a substrate. Then, the mask layer and the pad oxide layer are patterned and the substrate is etched to form a trench. After that, a first liner is formed in the trench. Thereafter, a portion of the first liner is removed to expose corners of the trench. Then, a second liner is formed over the substrate to cover the corners of the trench and the first liner. The material of the second liner is different from that of the first liner. An insulation layer is further formed over the substrate to fill up the trench. The insulation layer, the second liner, the mask layer and the pad oxide layer outside the trench are eventually removed. | 07-23-2009 |
| 20090184368 | IC CHIP - An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values. | 07-23-2009 |
| 20090183380 | CALIBRATION DEVICE FOR NOZZLE AND CALIBRATION METHOD FOR NOZZLE - A calibration device for a nozzle suitable for calibrating a nozzle of a semiconductor apparatus is provided. The semiconductor apparatus includes a chuck with a center hole with radius R | 07-23-2009 |
| 20090179222 | SILICON CONTROLLED RECTIFIER - A silicon controlled rectifier structure of polygonal layouts is provided. The polygonal first conductive type doped region is located in the middle of the polygonal second conductive type well. The first conductive type well shaped as a polygonal ring surrounds the second conductive type well and the second conductive type doped region is located within the first conductive type well and shaped as a polygonal ring concentric to the first conductive type well. | 07-16-2009 |
| 20090176378 | MANUFACTURING METHOD OF DUAL DAMASCENE STRUCTURE - A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer. | 07-09-2009 |
| 20090174945 | CONTIGUOUS MICROLENS ARRAY, METHOD OF FABRICATING THE SAME AND PHOTOMASK FOR DEFINING THE SAME - A contiguous microlens array including a plurality of contiguous microlenses is described. Each microlens has substantially circular contours at the heights higher than the connection sections of the microlens with neighboring microlenses, and has substantially partially circular contours at the heights on the connection sections adjacent to the neighboring microlenses. The shape of the curved surface of a microlens in the microlens array is selectively adjusted according to its position in the array and the incident angle of light incident thereto. | 07-09-2009 |
| 20090171495 | METHOD OF CONTROLLING STATUSES OF WAFERS - A method of controlling statuses of a plurality of wafers is described. A status of a wafer among the wafers is determined. An action related to the status is taken, according to the status determined, to the wafer and/or other wafers to improve a yield or yields thereof. | 07-02-2009 |
| 20090170039 | EXPOSURE METHOD - The invention provides an exposure method for manufacturing a device. The method includes providing a wafer having several exposure regions with a photoresist layer covering thereon. A feedback parameter map with several exposure-region feedback parameter sets respectively corresponds to the exposure regions of the wafer. At least one of the exposure-region feedback parameter sets is different from the rest of the exposure-region feedback parameter sets. According to the feedback parameter map, an exposure process is sequentially performed on each of the exposure regions of the wafer through an exposure tool to pattern the photoresist layer on the wafer. While the exposure tool performs the exposure process on each of the exposure regions, an exposure process parameter set of the exposure tool is adjusted based on the exposure-region feedback parameter sets corresponding to the exposure region in the feedback parameter map. | 07-02-2009 |
| 20090169767 | METHOD FOR INCREASING THE REMOVAL RATE OF PHOTORESIST LAYER - A method for increasing the removal rate of a photoresist layer is provided. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer. | 07-02-2009 |
| 20090166625 | MOS DEVICE STRUCTURE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 07-02-2009 |
| 20090166567 | METHOD OF PERFORMING ION IMPLANTATION - A method of performing an ion implantation is provided. A workpiece is installed in the ion implanter. A wafer is provided in a receiving space within an ion implanter. An ion beam is generated by an ion source of the ion implanter. The bombard of the ion beam is blocked and particles generated during or after conducting the step of generating the ion beam are collected by the workpiece. | 07-02-2009 |
| 20090155999 | METHOD FOR FABRICATING METAL SILICIDE - A method for fabricating a metal silicide film is described. After providing a silicon material layer, a metal alloy layer is formed to cover the silicon material layer. A thermal process is performed to form a metal alloy silicide layer in a self-aligned way. A wet etching process is performed by using a cleaning solution including sulfuric acid and hydrogen peroxide to remove the residual metals and unreacted metal alloy. | 06-18-2009 |
| 20090146311 | INTERCONNECT STRUCTURE - An interconnect structure is disposed on a substrate with a conductive part thereon and includes a first porous low-k layer on the substrate, a damascene structure in the first porous low-k layer, a second porous low-k layer over the first porous low-k layer and the damascene structure, and a first UV cutting layer at least between the first porous low-k layer and the second porous low-k layer. The damascene structure is electrically connected with the conductive part. The UV cutting layer is a UV reflection layer or a UV reflection-absorption layer. | 06-11-2009 |
| 20090145877 | METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES - A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio. | 06-11-2009 |
| 20090137097 | METHOD FOR DICING WAFER - A method for dicing a wafer including the following steps is provided. First, a carrier tape is attached to a first side of the wafer. Then, a patterned photoresist layer exposing a scribe line region of the wafer is formed on a second side of the wafer, in which the second side is the opposite side of the first side. After that, a cutting process is performed to the scribe line region from the second side of the wafer to the first side of the wafer through non-mechanical force. | 05-28-2009 |
| 20090134484 | Image sensor with correcting lens and fabrication thereof - An image sensor with at least one correcting lens and a method for fabricating the same are described. The image sensor includes a substrate with an array of microlenses thereon and at least one correcting lens disposed over the substrate covering the microlens array. In the fabricating method, a substrate having formed with a microlens array thereon is provided, and then at least one correcting lens is disposed over the substrate covering the microlens array. The at least one correcting lens can, in use of the image sensor, shift the incident direction of light to a microlens in edge parts of the array of microlenses toward the normal line direction of the image sensor. | 05-28-2009 |
| 20090134464 | STATIC RANDOM ACCESS MEMORY AND FABRICATING METHOD THEREOF - A static random access memory at least includes: pluralities of transistors disposed on a substrate, each transistor at least includes a gate, a gate dielectric layer, a source doped region and a drain doped region, in which some of the source doped regions are used for connecting with a Vss voltage or a Vdd voltage, and a salicide layer disposed on the gates, the source doped regions except those source doped regions used for connecting a Vss voltage and a Vdd voltage and the drain doped regions. | 05-28-2009 |
| 20090124095 | METHOD FOR FORMING PATTERNED PHOTORESIST LAYER - A method for forming a patterned photoresist is provided, which is applicable to a substrate. The method includes: performing an implantation process over the substrate; next, performing a surface treatment process; then, forming a photoresist layer over the substrate; and thereafter, patterning the photoresist layer. | 05-14-2009 |
| 20090124056 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure. | 05-14-2009 |
| 20090124037 | METHOD OF PREVENTING COLOR STRIATION IN FABRICATING PROCESS OF IMAGE SENSOR AND FABRICATING PROCESS OF IMAGE SENSOR - A fabricating process of an image sensor is provided. A substrate having thereon a circuit of the image sensor and an insulating layer is provided, wherein the insulating layer has therein a pad opening exposing a metal pad of the circuit. A filling layer is formed in the pad opening, and a color filter array is formed over the insulating layer. A planarization layer is formed over the substrate covering the color filter array, and a microlens array is formed on the planarization layer. The filling layer is then removed. | 05-14-2009 |
| 20090121278 | STRUCTURE AND FABRICATION METHOD OF FLASH MEMORY - A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency. | 05-14-2009 |
| 20090120785 | METHOD FOR FORMING METAL FILM OR STACKED LAYER INCLUDING METAL FILM WITH REDUCED SURFACE ROUGHNESS - A method for forming a stacked layer with a reduced surface roughness that includes at least a metal film and an anti-reflection coating thereon is described. A sputtering process is conducted using a metal target to deposit a layer of metal on a substrate, wherein the DC power density over the sputtered surface of the metal target is set higher than 5 W/inch | 05-14-2009 |
| 20090119045 | METHOD OF INSPECTING PHOTOMASK DEFECT - A method of inspecting defect of a mask is provided. In this method, a database for storing a plurality of virtual simulation models is created. The virtual simulation models are determined by a plurality of factors including an optical effect and a chemical effect during the transferring the pattern of a mask to the photoresist layer on a wafer. A mask defect image is acquired. A simulation contour of the mask defect image is generated from at least one virtual simulation model in the database. Next, the acceptability of the mask is determined. | 05-07-2009 |
| 20090111361 | METHOD OF SUPPLYING POLISHING LIQUID - The present invention relates to a method of supplying the polishing liquid by periodically interrupt the supply of the polishing liquid, thus avoid over-supply or wastage of the polishing liquid. Hence, the consumption of the polishing liquid can be decreased and the production cost can be lower. | 04-30-2009 |
| 20090111272 | METHOD OF FORMING STRAIN-CAUSING LAYER FOR MOS TRANSISTORS AND PROCESS FOR FABRICATING STRAINED MOS TRANSISTORS - A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate. The non-conformal stressed film is then etched, without an etching mask thereon, to remove portions thereof between the gate structures and disconnect the stressed film between the gate structures. At least one extra stressed film may be further formed over the substrate, wherein each extra stressed film has the same type of stress as the above stressed film and is connected or disconnected between the gate structures. | 04-30-2009 |
| 20090111252 | METHOD FOR FORMING DEEP WELL REGION OF HIGH VOLTAGE DEVICE - A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions. | 04-30-2009 |
| 20090108348 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d | 04-30-2009 |
| 20090108291 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device including a gate structure, two doped regions, and two buffer layers is provided. The gate structure is disposed on a substrate. The two doped regions are made of boron doped silicon germanium (SiGeB) and are disposed in the substrate at both sides of the gate structure. The two buffer layers are made of carbon doped silicon germanium (SiGeC) and are respectively disposed between the two doped regions and the substrate. | 04-30-2009 |
| 20090107954 | METHOD FOR CONTROLLING ADI-AEI CD DIFFERENCE RATIO OF OPENINGS HAVING DIFFERENT SIZES - A method for controlling ADI-AEI CD difference ratios of openings having different sizes is provided. First, a first etching step using a patterned photoresist layer as a mask is performed to form a patterned Si-containing material layer and a polymer layer on sidewalls thereof. Next, a second etching step is performed with the patterned photoresist layer, the patterned Si-containing material layer and the polymer layer as masks to at least remove an exposed portion of a etching resistive layer to form a patterned etching resistive layer. A portion of a target material layer is removed by using the patterned etching resistive layer as an etching mask to form a first and a second openings in the target material layer. The method is characterized by controlling etching parameters of the first and second etching steps to obtain predetermined ADI-AEI CD difference ratios. | 04-30-2009 |
| 20090107527 | METHOD OF CLEANING TRANSPARENT DEVICE IN A THERMAL PROCESS APPARATUS, THERMAL PROCESS APPARATUS AND PROCESS USING THE SAME THERMAL PROCESS APPARATUS - A method of cleaning a transparent device in a thermal process apparatus, wherein the transparent device is disposed in a chamber of a thermal process apparatus, and the transparent device includes a wafer holder for carry a wafer disposed under the transparent device, and an energy source output device disposed above the transparent device in the chamber, is provided. The method of the present invention includes performing a surface treatment step to clean a surface of the transparent device. | 04-30-2009 |
| 20090104773 | METHOD OF FORMING CONTACT - A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact. | 04-23-2009 |
| 20090098734 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF POLISHING SEMICONDUCTOR STRUCTURE - A method of forming an STI structure is described. A patterned mask layer is formed over a substrate of a wafer. A portion of the substrate exposed by the patterned mask layer is removed to form trenches. A dielectric layer is formed over the substrate filling the trenches. A first CMP process is performed to remove a portion of the dielectric layer. A second CMP process is performed to remove a further portion of the dielectric layer and a portion of the patterned mask layer, such that the surface of the dielectric layer is lower than that of the patterned mask layer. The polishing rate in the second CMP process is lower than that in the first one. The polishing selectivity of the dielectric layer to the mask layer in the second CMP process is higher than that in the first one. The patterned mask layer is then removed. | 04-16-2009 |
| 20090096039 | HIGH-VOLTAGE DEVICE AND MANUFACTURING METHOD OF TOP LAYER IN HIGH-VOLTAGE DEVICE - A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the substrate, and the well is disposed in the substrate at one side of the gate. The source region is disposed in the substrate at the other side of the gate. The drain region is disposed in the well of the substrate. The conductive layers are disposed on the substrate between the gate and the drain region. The top layer is disposed in the well of the substrate, and the well is below the conductive layers. One portion of the top layer near the gate has a thickness greater than that of the other portion of the top layer away from the gate. | 04-16-2009 |
| 20090090395 | METHOD OF REMOVING PARTICLES FROM WAFER - A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed. | 04-09-2009 |
| 20090087807 | METHOD OF SEMICONDUCTOR PROCESS AND SEMICONDUCTOR APPARATUS SYSTEM - A method of a semiconductor process is provided. The semiconductor process at least includes a first high temperature furnace process and a second high temperature furnace process. In the method, the first high temperature furnace process is performed on a first wafer boat carrying at least a wafer. Then, the second high temperature furnace process is performed on a second wafer boat carrying at least the same wafer. In addition, before the second high temperature furnace process is implemented, a moving step is performed, such that a relative position of the wafer in the first wafer boat is different from that of the wafer in the second wafer boat. | 04-02-2009 |
| 20090081817 | PATTERNING METHOD - A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile. | 03-26-2009 |
| 20090079439 | EFUSE SYSTEM AND TESTING METHOD THEREOF - An eFuse system and a method for testing the eFuse system are provided. The eFuse system includes an eFuse, a sensing circuit, and an offset resistor. The sensing circuit has a trigger point resistance and is coupled to a first end of the eFuse for sensing the resistance of the eFuse, wherein the resistance depends on whether the eFuse is blown or not. Accordingly, the sensing circuit outputs a first signal if the sensed resistance is greater than the trigger point resistance and outputs a second signal if the sensed resistance is less than the trigger point resistance. The offset resistor is coupled to a second end of the eFuse for compensating a shift on the trigger point resistance of the sensing circuit due to temperature change. | 03-26-2009 |
| 20090079083 | INTERCONNECT STRUCTURE AND FABRICATING METHOD OF THE SAME - A fabricating method of an interconnect structure is provided. A first dielectric layer is formed on a substrate for covering an air gap region and a non-air gap region. Next, interconnects are formed in the first dielectric layer on the air gap region and in the first dielectric layer on the non-air gap region. Then, a cap layer is formed on the first dielectric layer. Thereafter, on the air gap region, a portion of the cap layer and a portion of the first dielectric layer are removed for forming first openings, and thereby a portion of the first dielectric layer are left between the interconnects for forming support pillars. After that, a second dielectric layer is formed over the substrate for covering the cap layer and the first openings, so as to form an air gap in each of the first openings. | 03-26-2009 |
| 20090079029 | CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF - A capacitor structure including a substrate, a butting conductive layer, a second dielectric layer, a plurality of openings, a bottom electrode layer, a capacitor dielectric layer, a top electrode layer, and a second metal interconnect layer is provided. The substrate has a first dielectric layer and a first metal interconnect layer located in the first dielectric layer in a non-capacitor region. The butting conductive layer is disposed over the first dielectric layer in a capacitor region. The second dielectric layer is disposed over the first dielectric layer and covers the butting conductive layer. The openings include a first opening exposing a portion of the butting conductive layer and a second opening exposing the first metal interconnect layer. The bottom electrode layer, the capacitor dielectric layer, and the top electrode layer are conformally stacked in the first opening sequentially. The second metal interconnect layer is disposed in the openings. | 03-26-2009 |
| 20090068854 | SILICON NITRIDE GAP-FILLING LAYER AND METHOD OF FABRICATING THE SAME - A method for fabricating a silicon nitride gap-filling layer is provided. A pre-multi-step formation process is performed to form a stacked layer constituting as a dense film on a substrate. Then, a post-single step deposition process is conducted to form a cap layer constituting as a sparse film on the stacked layer, wherein the cap layer has a thickness of at least 10% of the total film thickness. | 03-12-2009 |
| 20090068824 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor substrate is provided. A substrate having a region adjacent to a surface of the substrate as a channel region is provided. An ion implantation process is performed to form an amorphized silicon layer in the substrate below the channel region. A thermal treatment process is performed to re-crystallize the amorphized silicon layer so as to form an epitaxial material layer. The epitaxial material layer may enhance the stress on the channel region in the substrate. | 03-12-2009 |
| 20090068810 | METHOD OF FABRICATION OF METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR - A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved. | 03-12-2009 |
| 20090068785 | MANUFACTURING METHOD OF IMAGE SENSOR DEVICE - A manufacturing method of image sensor device is provided. The image sensor device is suitable for a substrate having at least one bonding pad. A plurality of photodiode sensing areas is formed on the substrate, at least a dielectric layer is formed over the substrate and the bonding pad is disposed in the dielectric layer. The method includes forming a cover layer on the dielectric layer. Next, the cover layer is patterned to form an opening in a first portion of the cover layer on the bonding pad. A second portion of the cover layer in the opening is retained to cover a portion of the surface of the bonding pad. A plurality of color filters is formed on the cover layer, and then a planarization layer is formed on the cover layer and the color filters. Thereafter, a plurality of micro lenses is formed on the planarization layer. | 03-12-2009 |
| 20090065879 | HIGH VOLTAGE DEVICE AND METHOD OF FABRICATING THE SAME - A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer. | 03-12-2009 |
| 20090065833 | CMOS IMAGE SENSOR - A CMOS image sensor is described, based on a substrate and including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, a photodiode and a floating node structure. The substrate includes a floating node area between the transfer transistor and the reset transistor. The floating node structure includes a P-well in the substrate within the floating node area, an N-well in the substrate outside of the floating node region, a lightly N-doped region having a portion in the P-well and another portion connected with the N-well, a heavily N-doped region in the N-well, and a contact plug for coupling the heavily N-doped region to the source follower transistor. | 03-12-2009 |
| 20090065775 | TEST-KEY FOR CHECKING INTERCONNECT AND CORRESPONDING CHECKING METHOD - A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages. | 03-12-2009 |
| 20090064084 | PREDICTION MODEL AND PREDICTION METHOD FOR EXPOSURE DOSE - A prediction model for exposure dose is indicated by the following formula, E=E | 03-05-2009 |
| 20090061623 | METHOD OF FORMING ELECTRICAL CONNECTION STRUCTURE - A method of forming an electrical connection structure is described. A dielectric layer is formed covering a first conductor on a substrate, and then an opening is formed in the dielectric layer exposing the first conductor. A first cleaning step is conducted using fluorine-containing plasma to clean the surfaces of the dielectric layer and the exposed first conductor, and then at least one low-temperature annealing step is conducted. A second cleaning step is conducted using argon plasma to clean the above surfaces. A second conductor is then formed in the opening. | 03-05-2009 |
| 20090061201 | ULTRA LOW DIELECTRIC CONSTANT (K) DIELECTRIC LAYER AND METHOD OF FABRICATING THE SAME - A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gradient density on a barrier layer over a substrate. | 03-05-2009 |
| 20090056625 | SHIELDING MEMBER OF PROCESSING SYSTEM - A shielding member applicable in a deposition apparatus is provided. The shielding member includes a base metal and an adhesion promoter layer arc-sprayed on the base metal, wherein adhesion promoter layer has a thickness gradient increasing from an upper end of the shielding member to a lower end of the shielding member. More preferably, no adhesion promoter layer is formed in the upper 10 cm of the shielding member, adjacent to a target layer. | 03-05-2009 |
| 20090051884 | PROJECTION APPARATUS - A projection apparatus including an illumination system, a reflective light valve, a projection lens, and a color filter is provided. The illumination system has a light source for providing an illumination beam, and the reflective light valve is disposed on the transmission path of the illumination beam. The reflective light valve has a plurality of pixels arranged in an array for converting the illumination beam into an image, and the projection lens is disposed on the transmission path of the image. The color filter is disposed between the light source and the reflective light valve and on the transmission path of the illumination beam. Moreover, the color filter includes a transparent substrate and a color filter array disposed on a first surface of the transparent substrate. The color filter array includes a plurality of filter patterns, and each of the filter patterns corresponds to one of the pixels, respectively. | 02-26-2009 |
| 20090045456 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method includes forming a gate structure on a substrate. The gate structure includes a patterned gate dielectric layer, a patterned gate conductor layer, a cap layer and a spacer. Next, a first and a second recesses are formed in the substrate on the two sides of the gate structure. Thereafter, a protection layer is formed on the bottom surfaces of the first and the second recesses, and then a etching process is performed to laterally enlarge first and the second recesses towards the direction of the gate structure. Thereafter, a material layer is respectively formed in the first recess and the second recess. Afterward, two source/drain contact regions are respectively formed in the material layers of the first recess and the second recess. | 02-19-2009 |
| 20090035915 | METHOD OF HIGH DENSITY PLASMA GAP-FILLING WITH MINIMIZATION OF GAS PHASE NUCLEATION - A method of high density plasma (HDP) gap-filling with a minimization of gas phase nucleation (GPN) is provided. The method includes providing a substrate having a trench in a reaction chamber. Next, a first deposition step is performed to partially fill a dielectric material in the trench. Then, an etch step is performed to partially remove the dielectric material in the trench. Thereafter, a second deposition step is performed to partially fill the dielectric material in the trench. A reaction gas used in the second deposition step includes a carrier gas, an oxygen-containing gas, a silicon-containing gas, and a hydrogen-containing gas. After the carrier gas and oxygen-containing gas are introduced into the reaction chamber and a radio frequency (RF) power is turned on for a period of time, the silicon-containing gas and hydrogen-containing gas are introduced into the reaction chamber. | 02-05-2009 |
| 20090032900 | METHOD OF PROTECTING SHALLOW TRENCH ISOLATION STRUCTURE AND COMPOSITE STRUCTURE RESULTING FROM THE SAME - A method of protecting a shallow trench isolation structure is described, which is applied to a semiconductor device process that includes a first process causing a recess in the STI structure and a second process after the first process. The method includes forming a silicon nitride layer in the recess along the profile of the same during the second process. | 02-05-2009 |
| 20090032490 | METHOD OF FABRICATING COLOR FILTER - Methods for fabricating color filters are provided. Firstly, a substrate having a first region and a second region is provided. Then, a first dichroic layer and a first mask layer are formed on the first region sequentially. Next, a second dichroic layer is formed on the substrate to cover the first mask layer and the surface of the second region of the substrate. Thereafter, a second mask layer is formed on the second dichroic layer on the second region. Afterwards, the second dichroic layer on the first region and between the first mask layer and the second mask layer is etched. Then, the first mask layer and the second mask layer are removed. | 02-05-2009 |
| 20090029541 | METHOD OF FABRICATING ANTI-FUSE AND METHOD OF PROGRAMMING ANTI-FUSE - A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer. | 01-29-2009 |
| 20090026576 | ANTI-FUSE - An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions. | 01-29-2009 |
| 20090023368 | POLISHING HEAD AND EDGE CONTROL RING THEREOF, AND METHOD OF INCREASING POLISHING RATE AT WAFER EDGE - A polishing head used for CMP is described, including a retaining ring that is for engaging with a wafer, a membrane and an edge control ring. The membrane includes a bottom part for engaging with the wafer, and a lip part contiguous with the bottom part. The edge control ring is disposed between the retaining ring and the membrane, including a bottom part that has an abutting surface. The abutting surface of the edge control ring contacts with the external surface of the lip part of the membrane when the membrane is not inflated. | 01-22-2009 |
| 20090023287 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 01-22-2009 |
| 20090023283 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 01-22-2009 |
| 20090014870 | SEMICONDUCTOR CHIP AND PACKAGE PROCESS FOR THE SAME - A semiconductor chip is provided. The semiconductor chip includes a chip and chip bump pads thereon. The chip bump pads include at least two chip bump pads that are physically connected. | 01-15-2009 |
| 20090014717 | TEST IC STRUCTURE - A test IC structure is described, which is disposed in a scribe line region of a wafer and includes first and second test keys, first and second conductive plugs, first and second test pads, and a passivation layer over the scribe line region. The first/second test key includes a first/second active device and a first/second interconnect structure electrically connected thereto, wherein the second test key is arranged substantially parallel with the first one. The first/second plug is disposed over the first/second interconnect structure and contacts with the upmost metal layer thereof. The first/second test pad is disposed over the first and the second test keys and contacts with the first/second conductive plug. The passivation layer has therein a first opening exposing a portion of the first test pad and a second opening exposing a portion of the second test pad. | 01-15-2009 |
| 20090011612 | METHOD OF SHORTENING PHOTORESIST COATING PROCESS - A method of shortening a photoresist coating process for a plurality of wafers is provided, wherein the photoresist coating process includes a first coating operation to a first wafer using a first photoresist liquid and a second coating operation to a second wafer using a second photoresist liquid. The method includes performing a dummy dispense operation of the second photoresist liquid within the period of the backend part of the first coating operation that needs no nozzle. | 01-08-2009 |
| 20090008803 | LAYOUT OF DUMMY PATTERNS - A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads. | 01-08-2009 |
