| Unimicron Technology Corp. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120124830 | PROCESS FOR FABRICATING CIRCUIT BOARD - A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad. | 05-24-2012 |
| 20120073867 | CIRCUIT STRUCTURE - A circuit structure suitable for being disposed on a carrier board. The circuit structure comprises a first patterned conductive layer, a second patterned conductive layer, and a solder mask. The first patterned conductive layer is disposed on the carrier board. The second patterned conductive layer is disposed on a part of the first patterned conductive layer. A part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar. The patterned solder mask covers a part of the first patterned conductive layer and has at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer. | 03-29-2012 |
| 20120067630 | CIRCUIT STRUCTURE OF CIRCUIT BOARD - A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits. | 03-22-2012 |
| 20120031652 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board includes a metal pattern layer, a thermally conductive plate, an electrically insulating layer, and at least one electrically insulating material. The thermally conductive plate has a plane. The electrically insulating layer is disposed between the metal pattern layer and the plane and partially covers the plane. The electrically insulating material covers the plane where is not covered by the electrically insulating layer and touches the thermally conductive plate. The electrically insulating layer exposes the electrically insulating material, and a thermal conductivity of the electrically insulating material is larger than a thermal conductivity of the electrically insulating layer. | 02-09-2012 |
| 20120031651 | CIRCUIT BOARD - A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material. | 02-09-2012 |
| 20120024584 | CONNECTOR AND MANUFACTURING METHOD THEREOF - A method of manufacturing a connector is provided. Firstly, a substrate having a first surface, a second surface opposite to the first surface and a through hole is provided. Next, a first conductive layer covering the inside wall of the through hole is formed on the substrate. Then, a filler is filled in the through hole to form a filler post. Next, a conductive elastic cantilever is formed over the first surface and electrically connected to the first conductive layer. Then, a gold layer is formed on the conductive elastic cantilever and over the first surface. A solder ball electrically connected to the first conductive layer is formed over the second surface. | 02-02-2012 |
| 20120006478 | FABRICATING METHOD OF CIRCUIT BOARD - A fabricating method of a circuit board including the following steps. First, a liquid material is adhered between a first substrate and a second substrate by using an atmospheric pressure difference. Then, a plurality of conductive columns are formed in the first substrate and the second substrate. Next, a patterning process is performed, so as to form two circuit layers. Next, two lamination structures are formed respectively on the circuit layers. Then, the first substrate and the second substrate are separated. Finally, another patterning process is performed, so as to finish the fabrication of the circuit board. | 01-12-2012 |
| 20110303442 | SUBSTRATE STRIP WITH WIRING AND METHOD OF MANUFACTURING THE SAME - A substrate strip with wiring is provided. The substrate strip includes a plurality of wiring blocks, a carrying substrate, and an adhesive layer. Each of the wiring blocks includes at least one wiring board unit, and each of the wiring board unit includes an insulating layer and a wiring layer disposed on the insulating layer. The carrying substrate has a carrying surface. The adhesive layer is disposed between the carrying surface and the wiring layers, and adheres to the wiring blocks and the carrying substrate. When the adhesive layer is separated from the wiring blocks, the wiring layers are kept on the insulating layers. Further, a manufacturing method for the substrate is provided. | 12-15-2011 |
| 20110284267 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board having a cavity is provided. The circuit board includes a first core layer, a second core layer, and a central dielectric layer. The first core layer includes a core dielectric layer and a core circuit layer, wherein the core circuit layer is disposed on the core dielectric layer. The second core layer is disposed on the first core layer. The central dielectric layer is disposed between the first core layer and the second core layer. The cavity runs through the second core layer and the central dielectric layer and exposes a portion of the core circuit layer. | 11-24-2011 |
| 20110253435 | MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE - A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure. | 10-20-2011 |
| 20110155441 | CIRCUIT BOARD AND PROCESS FOR FABRICATING THE SAME - A process for fabricating a circuit board is provided. A circuit substrate having a first surface and a first circuit layer is provided. A first dielectric layer having a second surface is formed on the circuit substrate and covers the first surface and the first circuit layer. An antagonistic activation layer is formed on the second surface. The antagonistic activation layer is irradiated by a laser beam to form at least a blind via extended from the antagonistic activation layer to the first circuit layer and an intaglio pattern. A first conductive layer is formed inside the blind via. A second conductive layer is formed in the intaglio pattern and the blind via. The second conductive layer covers the first conductive layer and is electrically connected with the first circuit layer through the first conductive layer. The antagonistic activation layer is removed to expose the second surface. | 06-30-2011 |
| 20110155440 | CIRCUIT BOARD AND PROCESS FOR MANUFACTURING THE SAME - A circuit board including a circuit substrate, a dielectric layer, a first conductive layer and a second conductive layer is provided. The circuit substrate has a first surface and a first circuit layer. The dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The dielectric layer has a second surface, at least a blind via extended from the second surface to the first circuit layer and an intaglio pattern. The first conductive layer is disposed inside the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer through the first conductive layer. | 06-30-2011 |
| 20110155428 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer. | 06-30-2011 |
| 20110155427 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer. | 06-30-2011 |
| 20110154664 | STRUCTURE OF CIRCUIT BOARD AND METHOD FOR FABRICATING THE SAME - A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices. | 06-30-2011 |
| 20110147342 | METHOD FOR FABRICATING WIRING STRUCTURE OF WIRING BOARD - A method for fabricating a wiring structure of a wiring board is provided. First, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, an intaglio pattern exposing the insulation layer is formed on an outer surface of the film. The intaglio pattern is formed by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern. The activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the film and the activated layer on the outer surface are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by chemical deposition method. | 06-23-2011 |
| 20110147339 | METHOD FOR MANUFACTURING WIRING STRUCTURE OF WIRING BOARD - A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed. | 06-23-2011 |
| 20110147056 | CIRCUIT BOARD AND PROCESS FOR FABRICATING THE SAME - A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer. | 06-23-2011 |
| 20110139494 | EMBEDDED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different. | 06-16-2011 |
| 20110114373 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate. | 05-19-2011 |
| 20110100543 | MANUFACTURING METHOD OF CIRCUIT STRUCTURE - A manufacturing method of circuit structure is described as follows. Firstly, a composite dielectric layer, a circuit board and an insulating layer disposed therebetween are provided. The composite dielectric layer includes a non-platable dielectric layer and a platable dielectric layer between the non-platable dielectric layer and the insulating layer wherein the non-platable dielectric layer includes a chemical non-platable material and the platable dielectric layer includes a chemical platable material. Then, the composite dielectric layer, the circuit board and the insulating layer are compressed. Subsequently, a through hole passing through the composite dielectric layer and the insulating layer is formed and a conductive via connecting a circuit layer of the circuit board is formed therein. Then, a trench pattern passing through the non-platable dielectric layer is formed on the composite dielectric layer. Subsequently, a chemical plating process is performed to form a conductive pattern in the trench pattern. | 05-05-2011 |
| 20110094779 | CIRCUIT STRUCTURE - A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer. | 04-28-2011 |
| 20110076802 | EMBEDDED CHIP PACKAGE PROCESS - An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole. | 03-31-2011 |
| 20100319973 | PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR - A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. The first core circuit board has at least one metal layer, and the first core circuit board has at least one first conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the first core circuit board and connected to the metal layer. The second core circuit board has at least one wiring layer, and the second core circuit board has at least one second conductive through hole connected to the wiring layer. The dielectric layer is laminated between the first core circuit board and the second core circuit board. | 12-23-2010 |
| 20100319970 | PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR - A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole. | 12-23-2010 |
| 20100294553 | PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR - A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. The core circuit board has at least one metal layer, and the core circuit board has at least one conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the core circuit board and connected to the metal layer. At least one dielectric layer covers the core circuit board, and the dielectric layer has an embedded hole. At least one wiring layer covers the dielectric layer and connected to the embedded hole. | 11-25-2010 |
| 20100288549 | Coreless packaging substrate and method for manufacturing the same - Disclosed are a coreless packaging substrate and a manufacturing method thereof. The substrate includes a built-up structure and a first wiring layer. The built-up structure has a first outside and an opposite second outside, and includes one or more second dielectric layers and second wiring layers, and a plurality of conductive vias. The second dielectric layers have first and second surfaces respectively facing the first and second outsides. The second wiring layers are disposed on the second surface. The conductive vias are disposed in the second dielectric layer. The outermost second wiring layer at the second outside has a plurality of second conductive pads. The first wiring layer is embedded into and exposed from the first surface of the outermost second dielectric layer at the first outside, and has a plurality of first conductive pads. The conductive vias electrically connect the first wiring layer and the second wiring layer. | 11-18-2010 |
| 20100279452 | IMAGE SENSOR CHIP PACKAGE METHOD - In an image sensor chip package method, a transparent substrate having an upper surface, a lower surface, and through holes is provided. The through holes pass through the transparent substrate. Conductive posts are formed in the through holes. A sealing ring is formed on the lower surface of the transparent substrate. A chip having an active surface, an image sensitive area, and die pads is provided. The image sensitive area and the die pads are located on the active surface. Conductive bumps are formed and respectively disposed on the die pads for respectively connecting the conductive posts. At the time the active surface of the chip is turned to face toward the lower surface of the transparent substrate. The chip is assembled to the transparent substrate and electrically connected with the conductive posts via the die pads. The sealing ring surrounds the image sensitive area and the die pads. | 11-04-2010 |
| 20100264534 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire. | 10-21-2010 |
| 20100252303 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board having a removing area is provided. The circuit board includes a first dielectric layer, a first laser resistant structure disposed on the first dielectric layer and located at the periphery of the removing area, a second dielectric layer disposed on the first dielectric layer, a circuit layer disposed on the second dielectric layer, a second laser resistant structure disposed on the second dielectric layer and located at the periphery of the removing area, and a third dielectric layer disposed on the second dielectric layer. The second laser resistant structure is insulated from the circuit layer. There is a gap between the second laser resistant structure and the circuit layer, and the vertical projection of the gap on a first surface overlaps the first laser resistant structure. The third dielectric layer exposes the portion of the circuit layer within the removing area. | 10-07-2010 |
| 20100215927 | COMPOSITE CIRCUIT SUBSTRATE STRUCTURE - A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure. | 08-26-2010 |
| 20100200154 | FABRICATING PROCESS OF CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT - A process for fabricating a circuit board with an embedded passive component is provided. An electrode-patterned layer having electrodes is formed on a surface of a conductive layer. A passive component material is filled in the intervals between the electrodes. The conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. The conductive layer is patterned to form a circuit layer. | 08-12-2010 |
| 20100193466 | METHOD OF MANUFACTURING CIRCUIT BOARD - A method of manufacturing a circuit board is provided. Firstly, a substrate is provided, and a first conductive layer is disposed on the substrate. Next, a barrier layer is formed on the first conductive layer. Thereafter, a through hole passing through the substrate, the first conductive layer, and the barrier layer is formed. A second conductive layer including a conductive rod disposed in the through hole is formed on an inside wall of the through hole and the barrier layer. After that, parts of the second conductive layer located outside the through hole are removed. Next, the barrier layer is removed, and a circuit layer is formed on the first conductive layer and the conductive rod. Parts of the first conductive layer exposed by the circuit layer are then removed. | 08-05-2010 |
| 20100164092 | SEMICONDUCTOR PROCESS, AND SILICON SUBSTRATE AND CHIP PACKAGE STRUCTURE APPLYING THE SAME - A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed. | 07-01-2010 |
| 20100101083 | METHOD FOR FABRICATING CIRCUIT BOARD STRUCTURE WITH CONCAVE CONDUCTIVE CYLINDERS - A method of fabricating a circuit board structure with concave conductive cylinders is provided. Firstly, a conductive layer is provided and a dielectric layer is formed on a surface of the conductive layer. Next, a plurality of vias is formed in the dielectric layer, where the vias are exposed on the surface of the conductive layer. A conductive material is then filled in the vias to form a plurality of conductive cylinders on the surface of the conductive layer, so that the tips of the conductive cylinders are exposed on a surface of the dielectric layer relatively far away from the conductive layer. The exposed tips of the conductive cylinders are removed, so that the height of the conductive cylinders is lower than the dielectric layer and the conductive cylinders sunk into the dielectric layer. | 04-29-2010 |
| 20100089627 | MULTILAYER THREE-DIMENSIONAL CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure. | 04-15-2010 |
| 20100077610 | METHOD FOR MANUFACTURING THREE-DIMENSIONAL CIRCUIT - A method for manufacturing a three-dimensional circuit is described as follows. Firstly, a three-dimensional insulating structure having at least one uneven surface is provided. Secondly, a self-assembly film is formed on the uneven surface for completely covering the uneven surface. Next, a catalytic film is formed on the self-assembly film. Afterward, the self-assembly film and the catalytic film are patterned. Then, a three-dimensional circuit structure is formed on the catalytic film by chemical deposition. | 04-01-2010 |
| 20100065319 | WIRING BOARD AND PROCESS FOR FABRICATING THE SAME - A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed. | 03-18-2010 |
| 20100059256 | CIRCUIT STRUCTURE OF CIRCUIT BOARD AND PROCESS FOR MANUFACTURING THE SAME - A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits. | 03-11-2010 |
| 20100044082 | WIRING BOARD - A wiring board including two wiring layers and a flexible core layer is provided. The flexible core layer is disposed between the wiring layers, and the flexible core layer is an insulator. A flexure of the wiring board is between 0 degree and 170 degrees. | 02-25-2010 |
| 20100043962 | FABRICATION METHOD OF RIGID-FLEX CIRCUIT BOARD - A fabrication method of a rigid-flex circuit board is described as follows. Firstly, a flexible circuit board and at least a cover layer are provided. The cover layer covers a surface of the flexible circuit board. A protection layer is then formed on the cover layer. Next, a substrate is laminated to the surface of the flexible circuit board. The substrate has a conductive layer and a prepreg disposed between the conductive layer and the cover layer. The prepreg has an opening for accommodating the protection layer. Thereafter, the conductive layer is patterned for forming a patterned conductive layer. Afterwards, the protection layer is removed. | 02-25-2010 |
| 20100031502 | METHOD FOR FABRICATING BLIND VIA STRUCTURE OF SUBSTRATE - A method for fabricating a blind via structure of a substrate is provided. First, a substrate is provided, which includes a conductive layer, a metal layer, and a dielectric layer disposed between the conductive layer and the metal layer. Next, a cover layer is formed on the conductive layer. Finally, the substrate formed with the cover layer is irradiated by a laser beam to form at least one blind via structure extending from the cover layer to the metal layer. The blind via structure includes a first opening, a second opening, and a third opening linking to one another. The first opening passes through the cover layer. The second opening passes through the conductive layer. The third opening passes through the dielectric layer. For example, a size of the first opening is greater than a size of the second opening and a size of the third opening. | 02-11-2010 |
| 20100025794 | IMAGE SENSOR CHIP PACKAGE STRUCTURE AND METHOD THEREOF - An image sensor chip package structure includes a transparent substrate, a chip, a sealing ring, a number of conductive posts, and a number of conductive bumps. The transparent substrate has a number of through holes. The through holes pass through the transparent substrate. The chip has an active surface, an image sensitive area, and a number of die pads. The image sensitive area and the die pads are located on the active surface. The sealing ring is disposed between the chip and the transparent substrate and surrounds the image sensitive area and the die pads. The conductive posts are disposed in the through holes, respectively. Here, the chip is electrically connected with the conductive posts via the die pads. The conductive bumps are disposed on the die pads, respectively. The conductive bumps are connected with the conductive posts, respectively. | 02-04-2010 |
| 20100013068 | CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF - A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad. | 01-21-2010 |
| 20090314095 | PRESSURE SENSING DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF - A pressure sensing device package including a circuit substrate, a pressure sensing device, a molding compound, and a flexible protection layer is provided. The circuit substrate has an opening. The pressure sensing device is flip chip bonded to the circuit substrate and has a sensing region facing toward the opening. The molding compound encapsulates the pressure sensing device but exposes the sensing region. The flexible protection layer is disposed on the sensing region and exposed by the opening of the circuit substrate. | 12-24-2009 |
| 20090301997 | FABRICATING PROCESS OF STRUCTURE WITH EMBEDDED CIRCUIT - A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed. | 12-10-2009 |
| 20090288858 | CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer. | 11-26-2009 |
| 20090284935 | STRUCTURE AND MANUFACTURING PROCESS FOR CIRCUIT BOARD - A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density. | 11-19-2009 |
| 20090282674 | ELECTRICAL INTERCONNECT STRUCTURE AND PROCESS THEREOF AND CIRCUIT BOARD STRUCTURE - An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core. | 11-19-2009 |
| 20090273907 | CIRCUIT BOARD AND PROCESS THEREOF - A circuit board and process thereof are provided. The circuit board includes a dielectric layer, an active circuit, and two shielding circuits. The dielectric layer has an active surface. The active circuit is disposed on the active surface, and the shielding circuits are respectively disposed on two sides of the active circuit. The height of the shielding circuits is larger than the height of the active circuit. | 11-05-2009 |
| 20090250247 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A circuit board including a first dielectric layer having a first surface and a second surface, a first circuit layer, a second dielectric layer, and a second circuit layer is provided. At least one trench is formed on the first surface, and the first circuit layer is formed on an inside wall of the trench. In addition, the second dielectric layer is disposed in the trench, and covers the first circuit layer. The second circuit layer is disposed in the trench, and the second dielectric layer is located between the first circuit layer and the second circuit layer. A manufacturing method of the circuit board is further provided. | 10-08-2009 |
| 20090205852 | CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed. | 08-20-2009 |
| 20090197364 | METHOD OF FABRICATING SUBSTRATE - A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel. | 08-06-2009 |
| 20090166059 | CIRCUIT BOARD AND PROCESS THEREOF - A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit. | 07-02-2009 |
| 20090144972 | CIRCUIT BOARD AND PROCESS FOR FABRICATING THE SAME - A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad. | 06-11-2009 |
| 20090117262 | METHOD OF FABRICATING CIRCUIT BOARD - A method of fabricating a circuit board includes the following steps. First, a patterned metal board is provided. The patterned metal board includes a patterned circuit having at least a pad. Next, a dielectric layer is formed on the patterned metal board to cover the patterned circuit. Thereafter, a processing treatment is preformed on a surface of the patterned metal board in which the surface is opposite to the patterned circuit, such that at least a conductive joint column disposed on the pad and a circuit layer having the patterned circuit are formed. Afterwards, a solder mask layer is formed on the dielectric layer to cover the circuit layer, such that the solder mask layer is in contact with the conductive joint column, the conductive joint column passes through the solder mask layer, and a height of the conductive joint column exceeds a thickness of the solder mask layer. | 05-07-2009 |
| 20090104772 | PROCESS OF FABRICATING CIRCUIT STRUCTURE - A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad. | 04-23-2009 |
| 20090025210 | CIRCUIT BOARD STRUCTURE WITH CONCAVE CONDUCTIVE CYLINDERS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a circuit board structure with concave conductive cylinders is provided. Firstly, a conductive layer is provided; a plurality of conductive cylinders are formed on a surface of the conductive layer; a dielectric layer is formed on the surface of the conductive layer with the conductive cylinders; the tips of the conductive cylinders are exposed on a surface of the dielectric layer far away from the conductive layer; removing the exposed tips of the conductive cylinders such that the height of the conductive cylinders is lower than the height of the dielectric layer, and the conductive cylinders sunk into the dielectric layer. | 01-29-2009 |
| 20090023246 | EMBEDDED CHIP PACKAGE PROCESS - An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer. | 01-22-2009 |
| 20090008145 | EMBEDDED CIRCUIT STRUCTURE AND FABRICATING PROCESS OF THE SAME - A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively. | 01-08-2009 |
| 20090008135 | CIRCUIT SUBSTRATE - A surface treatment process for a substrate is provided. There are a plurality of first conductive patterns on a top surface of the substrate and a plurality of second conductive patterns on a bottom surface of the substrate and a plurality of inner circuits electrically connected with the first conductive patterns and the second conductive patterns. The process includes the following steps. First, a conductive layer is formed on the second conductive patterns. Next, an insulating layer is formed on the conductive layer. After the insulating layer is formed, an anti-oxidizing layer is electroplated on the first conductive patterns using the conductive layer. Next, the insulating layer and the conductive layer are removed in sequence. The surface treatment process of the present invention has the advantage of low fabrication cost and does not need a plating bar to perform the electroplating process or a photolithographic process. | 01-08-2009 |
| 20080280032 | PROCESS OF EMBEDDED CIRCUIT STRUCTURE - A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure. | 11-13-2008 |
| 20080277141 | CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME - A circuit board including a dielectric layer, a circuit layer, at least one conductive joint column, and a solder mask layer is provided. The circuit layer having at least one pad is in contact with the dielectric layer. The conductive joint column is disposed on the pad. The solder mask layer is disposed on the dielectric layer and covers the circuit layer. The solder mask layer is in contact with the conductive joint column, and the conductive joint column penetrates the solder mask layer. A height of the conductive joint column is larger than a thickness of the solder mask layer. The enhanced reliability of bonding between another component and the conductive joint column will be provided. Further, a method of fabricating a circuit board is also provided. | 11-13-2008 |
| 20080244897 | APPARATUS FOR TRANSPLANTING MULTI-BOARD - An apparatus for transplanting a multi-board is provided. This apparatus includes an orientation device, a calibration device, and an image-adjusting device. The orientation device has a first movable platform, and the multi-board is fixed on the first movable platform. The calibration device has a second movable platform and is used for moving a substitution circuit board to a recombination position of the multi-board. The image-adjusting device captures image data of the multi-board and the substitution circuit board and compares the image data to obtain an error signal. The calibration device receives the error signal and moves the second movable platform according to the error signal in order to calibrate the relative position between the substitution circuit board and the multi-board. | 10-09-2008 |
| 20080223605 | EMBEDDED CIRCUIT BOARD AND PROCESS THEREOF - An embedded circuit board including a glass fiber layer, two dielectric layers, and two circuit layers is provided. The glass fiber layer has a first surface and a second surface corresponding to the first surface. The dielectric layers are disposed on the first surface and the second surface, respectively. The circuit layers are embedded in the dielectric layers above the first surface and the second surface, respectively. The outer surface of each circuit layer is coplanar with the outer surface of each dielectric layer, and a distance between the circuit layer and the glass fiber layer is greater than or equal to 3 μm. In addition, a process of the embedded circuit board is provided. | 09-18-2008 |
| 20080196934 | CIRCUIT BOARD PROCESS - A circuit board process is provided. First, multiple carriers is provided, and a first conductive layer having multiple concave structures is formed on each carrier. A dielectric layer is then provided, and the carriers with the first conductive layers are laminated on a first and a second surface of the dielectric layer respectively, wherein portions of the first conductive layers are embedded in the first and second surfaces. Next, the carriers are removed. Thereafter, the first conductive layer corresponding to at least one concave is removed to expose a portion of the dielectric layer. Next, the exposed dielectric layer is removed to form an opening. A second conductive layer is then formed on the inner wall of the opening, wherein the second conductive layer is electrically connected to the first conductive layers on both sides of the dielectric layer. | 08-21-2008 |
