| TRANSPHORM INC. Patent applications |
| Patent application number | Title | Published |
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| 20120132973 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 05-31-2012 |
| 20120126239 | LAYER STRUCTURES FOR CONTROLLING STRESS OF HETEROEPITAXIALLY GROWN III-NITRIDE LAYERS - A III-N layer structure is described that includes a III-N buffer layer on a foreign substrate, an additional III-N layer, a first III-N structure, and a second III-N layer structure. The first III-N structure atop the III-N buffer layer includes at least two III-N layers, each having an aluminum composition, and the III-N layer of the two III-N layers that is closer to the III-N buffer layer having the larger aluminum composition. The second III-N structure includes a III-N superlattice, the III-N superlattice including at least two III-N well layers interleaved with at least two III-N barrier layer. The first III-N structure and the second III-N structure are between the additional III-N layer and the foreign substrate. | 05-24-2012 |
| 20110249477 | BRIDGE CIRCUITS AND THEIR COMPONENTS - A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor. | 10-13-2011 |
| 20110193619 | SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS - An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package. | 08-11-2011 |
| 20110169549 | ELECTRONIC DEVICES AND COMPONENTS FOR HIGH EFFICIENCY POWER CIRCUITS - An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package. | 07-14-2011 |
| 20110140172 | REVERSE SIDE ENGINEERED III-NITRIDE DEVICES - Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a | 06-16-2011 |
| 20110127541 | SEMICONDUCTOR HETEROSTRUCTURE DIODES - Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG. | 06-02-2011 |
| 20110121314 | ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices. | 05-26-2011 |
| 20110101466 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 05-05-2011 |
| 20110049526 | Semiconductor Devices with Field Plates - A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer. | 03-03-2011 |
| 20100289067 | High Voltage III-Nitride Semiconductor Devices - A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a | 11-18-2010 |
| 20100201439 | III-Nitride Devices and Circuits - A III-nitride based high electron mobility transistor is described that has a gate-connected grounded field plate. The gate-connected grounded field plate device can minimize the Miller capacitance effect. The transistor can be formed as a high voltage depletion mode transistor and can be used in combination with a low voltage enhancement-mode transistor to form an assembly that operates as a single high voltage enhancement mode transistor. | 08-12-2010 |
| 20100073067 | Inductive Load Power Switching Circuits - Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor. | 03-25-2010 |
| 20090267078 | Enhancement Mode III-N HEMTs - A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate. | 10-29-2009 |
| 20090146185 | INSULATED GATE E-MODE TRANSISTORS - Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region. | 06-11-2009 |
| 20090072272 | ENHANCEMENT MODE GALLIUM NITRIDE POWER DEVICES - Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices. | 03-19-2009 |
| 20090072240 | III-Nitride Devices with Recessed Gates - III-nitride devices are described with recessed gates. In some embodiments, the material around the gates is formed by epitaxially depositing different III-nitride layers on a substrate and etching through at least the top two layers in the gate region. Because adjacent layers in the top three layers of the structure have different compositions, some of the layers act as etch stops to allow for precision etching. In some embodiments, a regrowth mask is used to prevent growth of material in the gate region. A gate electrode is deposited in the recess. | 03-19-2009 |
