Transitive Limited Patent applications |
Patent application number | Title | Published |
20100030975 | APPARATUS AND METHOD FOR HANDLING PAGE PROTECTION FAULTS IN A COMPUTING SYSTEM - Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit ( | 02-04-2010 |
20090210649 | MULTIPROCESSOR COMPUTING SYSTEM WITH MULTI-MODE MEMORY CONSISTENCY PROTECTION - Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary multiprocessor computing system provides memory and multiple processors, and a set of controller/translator units TX | 08-20-2009 |
20090100416 | DYNAMIC NATIVE BINDING - A native binding technique is provided for insetting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes. | 04-16-2009 |
20090094586 | METHOD AND APPARATUS FOR PERFORMING NATIVE BINDING - A native binding technique is provided for inserting calls to native functions during translation of subject code to target code, such that function calls in the subject program to subject code functions are replaced in target code with calls to native equivalents of the same functions. Parameters of native function calls are transformed from target code representations to be consistent with native code representations, native code calling conventions, and native function prototypes. | 04-09-2009 |
20090007085 | ARCHITECTURE FOR GENERATING INTERMEDIATE REPRESENTATIONS FOR PROGRAM CODE CONVERSION - An improved architecture for a program code conversion apparatus and method for generating intermediate representations for program code conversion. The program code conversion apparatus determines which types of IR nodes to generate in an intermediate representation (IR) of subject code ( | 01-01-2009 |
20080263342 | Apparatus and method for handling exception signals in a computing system - Described is method and apparatus for handling exception signals in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. An exception handling unit selectively handles some exception signals with respect to a target state and handles others with respect to a subject state derived from the target state. Signal handling sub-units are arranged to process the exception signal with respect to the target state and output a request either to return to execution or to pass on the exception signal. A delivery path selection unit is arranged to determine a delivery path of the exception signal to a selected group of the plurality of signal handling sub-units. A signal control unit is arranged to deliver the exception signal in turn to each of the selected group of signal handling sub-units. | 10-23-2008 |
20080244241 | HANDLING FLOATING POINT OPERATIONS - A computing system capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit. The computing system further comprises a translator unit arranged to receive subject code instructions including at least one instruction relating to a floating point operation and in response to generate corresponding target code for execution on said processor. To handle floating point operations a floating point status unit and a floating point control unit are provided within the translator. These units are cause the translator unit to generate either: target code for performing the floating point operations directly on the floating point unit; or target code for performing the floating point operations indirectly, for example using a combination of the integer unit and the floating point unit. In this way the efficiency of the computing system is improved. | 10-02-2008 |
20080209175 | Computer system and method of adapting a computer system to support a register window architecture - A target computing system | 08-28-2008 |