| TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120133044 | METAL CONTAINING SACRIFICE MATERIAL AND METHOD OF DAMASCENE WIRING FORMATION - According to one embodiment, a via and trench are formed in a semiconductor structure. The via and the trench are suitable for having a metal-based wire placed therein by damascene, dual damascene, plating and other suitable techniques. The via is etched into a dielectric layer of a semiconductor structure comprising a base cap layer, the dielectric layer formed over the base cap layer, and a hardmask formed over the dielectric layer. The via is filled with a sacrifice material, where the sacrifice material contains a metal or a metal compound, where the sacrifice material additionally forms a sacrifice layer over the hardmask layer. The sacrifice material placed in the via does not contain a material or film containing a Si—O bond. The sacrifice material is used as a support for a photomask that is placed over the sacrifice layer, where the photomask is developed to have a trench pattern formed therein. Then, one or more of the hardmask layer and the dielectric layer is etched with the trench pattern, and the sacrifice material and the sacrifice layer are removed by contact with a remover solution containing one or more selected from an acidic compound, water, a base compound, and an oxidant. | 05-31-2012 |
| 20120080777 | TRIPLE OXIDATION ON DSB SUBSTRATE - According to certain embodiments, a semiconductor structure is formed having a gate oxide formed over a semiconductor substrate. The gate oxide is formed as to have three different regions characterized by a different average thickness of gate oxide in each region. A first oxidation process is performed on a semiconductor substrate having both a Si (110) orientation region and a Si (100) orientation region on a surface thereof. Gate oxide is formed at a faster rate on the Si (110) orientation region of the semiconductor substrate relative to the Si (100) orientation region. A portion of the gate oxide is selectively removed and a second oxidation process is performed to form additional gate oxide. A triple oxide semiconductor substrate is recovered with the gate oxide having three different thickness formed thereon. The triple oxide semiconductor substrate is formed using a decreased number of processing acts. | 04-05-2012 |
| 20120068347 | METHOD FOR PROCESSING SEMICONDUCTOR STRUCTURE AND DEVICE BASED ON THE SAME - Methods for fabricating a device and related device structures are provided herein. According to one embodiment, a method for fabricating a device includes the acts of producing a substrate; forming a structure on the substrate having a lower dielectric layer, a metal layer, an upper dielectric layer, a planarizing layer, and a layer of photoresist material; developing the photoresist material according to a mask pattern; etching the planarizing layer and the upper dielectric layer according to the mask pattern; removing the photoresist material and the planarizing layer upon etching of the planarizing layer and the upper dielectric layer; applying a selective metal growth or metal/organic film to respective exposed portions of the metal layer following etching of the upper dielectric layer, thereby obtaining an inverted mask pattern; and etching at least the metal layer and the lower dielectric layer according to the inverted mask pattern. | 03-22-2012 |
| 20120061773 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×10 | 03-15-2012 |
| 20120045898 | Ru CAP METAL POST CLEANING METHOD AND CLEANING CHEMICAL - According to certain embodiments, Ru is removed from the surface of a semiconductor structure by contact with a cleaning solution comprising one or more selected from permanganate ion, orthoperiodic ion and hypochlorous ion, such that Ru is removed from surfaces of the semiconductor substrate where the presence of Ru is undesirable. In some embodiments, a semiconductor structure is formed or provided having at least one metalized layer formed over an underlying layering or semiconductor substrate. The metalized layer contains a dielectric material with one or more metal wires of copper-containing material formed in a trench and/or via in the dielectric material. A cap layer having Ru is formed on the surface of the copper-containing material forming the one or more metal wires. The semiconductor structure is contacted with the cleaning solution comprising one or more selected from permanganate ion, orthoperiodic ion and hypochlorous ion to remove a portion of the Ru present in the semiconductor structure. | 02-23-2012 |
| 20110298058 | FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET - FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds. | 12-08-2011 |
| 20110285024 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer. | 11-24-2011 |
| 20110266676 | METHOD FOR FORMING INTERCONNECTION LINE AND SEMICONDUCTOR STRUCTURE - A semiconductor structure is formed by placing a thin barrier metal layer in an interconnection trench or via in a manner such that the opening of the trench or via is not obstructed by an overhang that interferes with the placement of copper into the interconnection trench or via. The material for forming a copper interconnection line contains copper and manganese. Upon annealing, a manganese oxide layer is formed having barrier properties against copper diffusion. | 11-03-2011 |
| 20110260282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed. | 10-27-2011 |
| 20110246695 | CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS - Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology. | 10-06-2011 |
| 20110230030 | STRAIN-PRESERVING ION IMPLANTATION METHODS - An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized. | 09-22-2011 |
| 20110180309 | INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER - A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure. | 07-28-2011 |
| 20110147839 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region. | 06-23-2011 |
| 20110006349 | FIELD EFFECT TRANSISTOR HAVING CHANNEL SILICON GERMANIUM - Field effect transistors and methods of making field effect transistors are provided. The field effect transistor can contain a semiconductor substrate containing shallow trench isolations; a silicon germanium layer in a trench at an upper surface of the semiconductor substrate between the shallow trench isolations; a gate feature on the silicon germanium layer; and metal silicides on the upper potions of silicon germanium layer and semiconductor substrate that are not covered by the gate feature. The silicon germanium layer has a bottom surface and a top surface having a (100) plane and side surfaces having two or more planes. | 01-13-2011 |
| 20100327395 | SEMICONDUCTOR DEVICE ON DIRECT SILICON BONDED SUBSTRATE WITH DIFFERENT LAYER THICKNESS - A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices. | 12-30-2010 |
| 20100327364 | SEMICONDUCTOR DEVICE WITH METAL GATE - A semiconductor device includes: a substrate and an n-channel MIS transistor. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, wherein a first source/drain region is formed in the p-type semiconductor region and separated from each other. The n-channel MIS transistor includes a first gate insulating film on the p-type semiconductor region between the first source/drain regions. The n-channel MIS transistor further includes a first gate electrode having a stack structure formed with a gate dielectric, a first metal layer and a first compound layer, the first metal layer having a thickness less than 2 nm and having a work function of 4.3 eV or smaller, the first metal layer being formed on the metallic layer having a work function larger than 4.4 eV and the first compound layer containing Al and a second metal that is different from the first metal. | 12-30-2010 |
| 20100323514 | RESTORATION METHOD USING METAL FOR BETTER CD CONTROLLABILITY AND CU FILING - Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/or mitigate surface erosion of the sidewall surface. As a result, the methods can improve the controllability of critical dimensions of the via and trench. | 12-23-2010 |
| 20100320604 | APPLICATION OF MN FOR DAMAGE RESTORATION AFTER ETCHBACK - Back end of line interconnect structures and methods of making a back end of line interconnect structure are provided. The back end of line interconnect structure contains a first interconnect layer containing a first conductive feature and a first dielectric layer; a first cap layer over the first interconnect layer, and a second interconnect layer over the first cap layer. The second interconnect layer contains a second conductive feature, a second dielectric layer, and two or more barrier layers therebetween. The two or more barrier layers contain a first barrier layer over the second dielectric layer and a MnO | 12-23-2010 |
| 20100314692 | Structures Of SRAM Bit Cells - A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell. | 12-16-2010 |
| 20100276760 | SEMICONDUCTOR DEVICE WITH METAL GATE - Gate electrode structures having a thin layer of ReO | 11-04-2010 |
| 20100244207 | MULTIPLE THICKNESS AND/OR COMPOSITION HIGH-K GATE DIELECTRICS AND METHODS OF MAKING THEREOF - Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described. | 09-30-2010 |
| 20100224943 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS WITH USING NON-PLANAR TYPE OF TRANSISTORS - Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar. | 09-09-2010 |
| 20090289375 | Dual Stress Liner Device and Method - A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure. | 11-26-2009 |
| 20090206414 | Contact Configuration and Method in Dual-Stress Liner Semiconductor Device - A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate, and removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines. This method, along with other methods and various semiconductor devices, are described. | 08-20-2009 |
| 20090201719 | Method and System for Semiconductor Memory - Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells. | 08-13-2009 |
| 20090196588 | Oven for Semiconductor Wafer - An oven is described that can more evenly heat the semiconductor wafer, even though the wafer may warp during heating. The oven may provide relatively uniform heating even though the type and location of warping may be unpredictable for any given wafer. The oven may have a heating surface divided into a plurality of heating zones that may each independently provide a given amount of heat to the wafer. The amount of heat provided by each zone may be determined using signals from sensors that sense the warping of the wafer. | 08-06-2009 |
| 20090191720 | COATING PROCESS AND EQUIPMENT FOR REDUCED RESIST CONSUMPTION - A coating system and method of coating semiconductor wafers is disclosed that is able to maintain a wet condition on the outer portion of the semiconductor wafer to provide ease of spreading for a photo-resist or anti-reflective coating (ARC) that is being dispensed. The system can include a plurality of nozzles on a movable arm. A first nozzle dispenses a pre-wet solvent onto the semiconductor wafer. A second nozzle then dispenses the photo-resist or ARC coating onto the semiconductor wafer. A third nozzle dispenses additional pre-wet solvent onto the outer edge of the semiconductor wafer as the photo-resist or ARC coating is being dispensed. The nozzles dispense solutions onto the semiconductor wafer as it rotates. The system produces semiconductor wafers with few coating defects and uses less photo-resist or ARC coating. | 07-30-2009 |
| 20090190108 | METHOD AND SYSTEM FOR LEVELING TOPOGRAPHY OF SEMICONDUCTOR CHIP SURFACE - A system and method of leveling the topography of a semiconductor wafer surface is presented. The system may induce low-order lens aberration to control the focal plane dynamically. The system may include a leveling sensor which measures the changes in topography on the surface, as well as an analyzer to determine the aberration to be induced. In addition, the system may include a controller that dynamically adjusts at least one lens to induce such aberration. In another arrangement, the system may control the focal plane by dividing the exposure slit into smaller slits. In this arrangement, the analyzer may be used to determine the appropriate number of divisions to make to produce a focal plane that closely matches the surface of the wafer. In addition, the controller may adjust the stage height and tilt for each division to produce such a focal plane. | 07-30-2009 |
| 20090189227 | STRUCTURES OF SRAM BIT CELLS - A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell. | 07-30-2009 |
| 20090189198 | STRUCTURES OF SRAM BIT CELLS - An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are p-type field effect transistors. Each field effect transistor may be arranged on a substrate that will enhance performance. In one arrangement, the p-type field effect transistors may be arranged on a silicon ( | 07-30-2009 |
| 20090174036 | PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES - A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing. | 07-09-2009 |
| 20090173967 | STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER - This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer. This invention also provides a twist-bonded semiconductor layer on a polycrystalline base layer, as well as methods for fabricating the aforementioned FETs. | 07-09-2009 |
| 20090146290 | Interconnect Structure and Method for Semiconductor Device - An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device. | 06-11-2009 |
| 20090101943 | Reversely Tapered Contact Structure Compatible With Dual Stress Liner Process - A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer. | 04-23-2009 |
| 20090001466 | METHOD OF FORMING AN SOI SUBSTRATE CONTACT - A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening. | 01-01-2009 |
| 20080290456 | Electrical Fuse With Metal Silicide Pipe Under Gate Electrode - An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages. | 11-27-2008 |
| 20080284524 | Phase Locked Loop Circuit Having Regulator - Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator. | 11-20-2008 |
| 20080199596 | FLUID DISPENSE SYSTEM - A system and method for dispensing fluid onto a surface during a manufacturing process. A fluid storage container holds a chemical, such as resist, used in a semiconductor lithography process. When not dispensing the chemical over the surface of a wafer, a pump and nozzle dispense the chemical into a dedicated dispense receptacle. A drain and pump may return the contents of the dispense receptacle to the fluid storage container for reuse. | 08-21-2008 |
