Tianshui Huatian Technology Co., Ltd. Patent applications |
Patent application number | Title | Published |
20150102476 | QUAD FLAT NO LEAD PACKAGE AND PRODUCTION METHOD THEREOF - The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved. | 04-16-2015 |
20130334686 | CARRIER-FREE LAND GRID ARRAY IC CHIP PACKAGE AND PREPARATION METHOD THEREOF - A carrier-free land grid array (LGA) Integrated Circuit (IC) chip package and a preparation method thereof are provided. The IC chip package includes: an inner pin, an IC chip, a pad, a bonding wire, and a mold cap. The inner pin is designed to be a multi-row matrix form at a front side of the package, and is designed to be an exposed multi-row approximate square-shaped circular gold-plated contacts at a back side; the IC chip is provided on the inner pin, the inner pin is adhered to the IC chip with an adhesive film sheet, the pad on the IC chip is connected to the inner pin by the bonding wire, and the mold cap encircles the adhesive film sheet, the IC chip, the bonding wire, and edges of the inner pin, so as to form a whole circuit. The present invention adopts approximate square-shaped spherical array contacts, thereby having a simple and flexible structure, and achieving a desirable heat-dissipation effect. A cooper lead frame (L/F) has a high yield, and reduces the material cost. The L/F is used to replace a ceramic substrate, PCB substrate, or BT substrate, thereby saving the complicated layout design, shortening the designing and manufacturing cycle, accelerating the trial production course, and enabling the product to be early listed to obtain market opportunities. | 12-19-2013 |
20130223018 | HIGH-DENSITY SIM CARD PACKAGE AND PRODUCTION METHOD THEREOF - A high-density Subscriber Identity Module (SIM) card package and a production method thereof are provided. The SIM card package includes a substrate, an Integrated Circuit (IC) chip, a bonding wire, and a mold cap. The substrate is a two-layer, a four-layer, a six-layer or an eight-layer high-density interlinked and packaged organic laminated substrate that is manufactured through an etching-back process, and a passive device and a crystal oscillator are provided on the organic laminated substrate. Two IC chips are provided side by side, or one of the IC chips is stacked with a third IC chip, the third IC chip being respectively connected to the organic laminated substrate and the IC chip under the third IC chip by the bonding wire. The IC chip, the passive device, and the crystal oscillator are adhered to the organic laminated substrate, and the IC chip is connected to the organic laminated substrate by the bonding wire; the height and the shape of a wire arc is controlled, an injection procedure is controller by using multi-stage injection model software; then, marking and cutting are performed to obtain the SIM card package. The dimension of the package of the present invention is 12 mm×18 mm×0.63 mm, devices of multiple kinds are molded, thereby meeting use requirements for multiple functions. | 08-29-2013 |
20130214386 | SIP SYSTEM-INTEGRATION IC CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC). | 08-22-2013 |