| TEXAS INSTRUMENTS INCORPORATED Patent applications |
| Patent application number | Title | Published |
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| 20120131401 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 05-24-2012 |
| 20120131309 | HIGH-PERFORMANCE, SCALABLE MUTLICORE HARDWARE AND SOFTWARE SYSTEM - Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system in provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. | 05-24-2012 |
| 20120129456 | Systems and Methods for Silencing Wireless Devices - Embodiments provide systems and methods to optimize the time when to receive transmissions from dissimilar wireless networks, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimilar wireless network technologies. A receiver comprises at least two dissimilar network technology subsystems and is able to receive transmissions from dissimilar wireless network technology subsystems during a predetermined reception window. | 05-24-2012 |
| 20120128236 | METHOD AND APPARATUS FOR STEREO MISALIGNMENT ESTIMATION USING MODIFIED AFFINE OR PERSPECTIVE MODEL - A method and apparatus for estimating stereo misalignment using modified affine or perspective model. The method includes dividing a left frame and a right frame into blocks, comparing horizontal and vertical boundary signals in the left frame and the right frame, estimating the horizontal and the vertical motion vector for each block in a reference frame, selecting a reliable motion vectors from a set of motion vectors, dividing the selected block into smaller features, feeding the data to an affine or a perspective transformation model to solve for the model parameters, running the model parameters through a temporal filter, portioning the estimated misalignment parameters between the left frame and right frame, and modifying the left frame and the right frame to save some boundary space. | 05-24-2012 |
| 20120128168 | METHOD AND APPARATUS FOR NOISE AND ECHO CANCELLATION FOR TWO MICROPHONE SYSTEM SUBJECT TO CROSS-TALK - A method and apparatus for joint noise and echo cancellation of a two microphone system subject to cross-talk. The method includes estimating the reference output by removing the cross-talk and the estimated echo from the reference channel, when an echo is detected in the reference echo signal, adapting filters H | 05-24-2012 |
| 20120127783 | SRAM Cell for Single Sided Write - A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage. | 05-24-2012 |
| 20120127777 | METHOD TO IMPROVE FERROELECTRIC MEMORY PERFORMANCE AND RELIABILITY - One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the device comprising the chip. The external agent sends a command to the control circuitry that the data states are to be written to a particular data state. Upon receiving a signal the control circuitry writes all of the ferroelectric memory cells in the FRAM array to a preferred memory data state. The memory data states are held in the preferred data state for the entire duration of the event to minimize imprint of the FRAM memory cells. When the event ends the external agent sends a command to the control circuitry to resume normal memory operation. Other methods and circuits are also disclosed. | 05-24-2012 |
| 20120126781 | ON-CHIP IR DROP DETECTORS FOR FUNCTIONAL AND TEST MODE SCENARIOS, CIRCUITS, PROCESSES AND SYSTEMS - An integrated circuit includes a functional circuit ( | 05-24-2012 |
| 20120126624 | HIGH EFFICIENCY WIDE LOAD RANGE BUCK/BOOST/BRIDGE PHOTOVOLTAIC MICRO-CONVERTER - Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are partially shaded or when the modules are mismatched. The integrated multi-mode dc-dc converter includes a maximum power point tracking (MPPT) algorithm that can track the true MPP, even when a PV module becomes partially-shaded, without scanning the entire output voltage range. The algorithm compares power levels only at a voltage that occurs when a bypass diode bypasses a portion of an associated PV module, and multiples thereof. | 05-24-2012 |
| 20120126453 | PELLET LOADER WITH PELLET SEPARATOR FOR MOLDING IC DEVICES - A pellet loading apparatus includes a tablet pusher including a support surfaces including a pusher mechanism coupled thereto for vertical movement upon actuation. A tablet holder on the tablet pusher includes locations framed by sidewall members aligned in the vertical direction that form columns having open tops for holding a pellet stacks of mold component pellets. A pellet separator having a solid portion and apertures is sized to fit around a portion of a top mold pellet in the pellet stacks. The pellet separator includes a pellet drive for lateral moving the top mold pellets relative to under pellets so that after lateral movement the top mold pellets are laterally offset from the under pellets. A tablet lifter includes a pellet stopper having receiving positions for receiving top mold pellets upon receipt after a transfer actuation of the pusher mechanism. | 05-24-2012 |
| 20120126418 | INTEGRATED CIRCUIT DEVICE HAVING DIE BONDED TO THE POLYMER SIDE OF A POLYMER SUBSTRATE - An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads. | 05-24-2012 |
| 20120126385 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad. | 05-24-2012 |
| 20120126383 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different from the first metal on each surface. The first metal exposed at the sidewalls and at portions of the first surface of the pad. A semiconductor chip is assembled on the leadframe. Portions of the assembled chip and the leadframe are packaged in a polymeric encapsulation compound. | 05-24-2012 |
| 20120126298 | SELF-POWERED INTEGRATED CIRCUIT WITH PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the photovoltaic cell portion. | 05-24-2012 |
| 20120126247 | SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL - A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion. | 05-24-2012 |
| 20120124438 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 05-17-2012 |
| 20120123718 | METHOD AND APPARATUS FOR CONTROLLING TIME OF FLIGHT CONFIDENCE MAP BASED DEPTH NOISE AND DEPTH COVERAGE RANGE - A method and apparatus for fixing a depth map wrap-around error and a depth map coverage by a confidence map. The method includes dynamically determining a threshold for the confidence map threshold based on an ambient light environment, wherein the threshold is reconfigurable depending on LED light strength distribution in TOF sensor, extracting, via the digital processor, four phases of Time Of Flight raw data from the Time Of Flight sensor data, computing a phase differential signal array for fixed point utilizing the four phases of the Time Of Flight raw data, computing the depth map, confidence map and the average light signal strength utilizing the phase differential signal array, obtaining the dynamic confidence map threshold for wrap around error correction utilizing the average light signal strength, and correcting the depth map wrap-around error utilizing the depth map, the confidence map and the dynamic confidence map threshold. | 05-17-2012 |
| 20120121166 | METHOD AND APPARATUS FOR THREE DIMENSIONAL PARALLEL OBJECT SEGMENTATION - A method and apparatus for parallel object segmentation. The method includes retrieving at least a portion of a 3-dimensional point cloud data x, y, z of a frame, dividing the frame into sub-image frames if the sub-frame based object segmentation is enabled,
| 05-17-2012 |
| 20120121165 | Method and apparatus for time of flight sensor 2-dimensional and 3-dimensional map generation - A method and apparatus for Time Of Flight sensor 2-dimensional and 3-dimensional map generation. The method includes retrieving Time Of Flight sensor fixed point data to obtain four phases of Time Of Flight fixed point raw data, computing Gray scale image array and phase differential signal arrays utilizing four phases of TOF fixed point raw data, computing Gray image array and Amplitude image array for fixed point, converting the phase differential signal array from fixed point to floating point, performing the floating point division for computing Arctan, TOF depthmap, and 3-dimensional point cloud map for Q format fixed point, and generating depthmap, 3-dimensional cloud coefficients and 3-dimensional point cloud for Q format fixed point. | 05-17-2012 |
| 20120121051 | RECEIVE TIMING MANAGER - A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement. | 05-17-2012 |
| 20120120285 | METHOD AND APPARATUS FOR RECONFIGURING TIME OF FLIGHT SHOT MODE - A method and apparatus for configuring Time Of Flight sensor and data transfer for dynamically reconfigurable sensor mode change depending on scene characteristics. The method includes configuring the sensor configuration set on normal shot mode, performing scene analysis on at least one captured scenes, when dynamic motion is detected and the automatic shot mode sensor change is enabled, configuring the sensor to fast shot mode, and when in normal shot mode, capturing and transferring the full size TOF raw pixels for each phase, and when in fast shot mode, capturing and transferring less than all the size of the Time Of Flight raw pixels for each phase. | 05-17-2012 |
| 20120119824 | BIAS VOLTAGE SOURCE - An integrated circuit that includes a data storage cell. The data storage cell has a PMOS transistor in an n-well. In addition, the data storage cell has a PMOS diode connecting a voltage source to a bias node of the n-well. Alternatively, an integrated circuit that includes a data storage cell. The alternative data storage cell has an NMOS transistor in an isolated p-well. In addition, the alternative data storage cell has an NMOS diode connecting a voltage source to a bias node of the isolated p-well. | 05-17-2012 |
| 20120119802 | DELAY LOCKED LOOP WITH DELAY PROGRAMMABILITY - A delay locked loop (DLL) with delay programmability includes a pair of delay blocks, each containing multiple delay elements, but configurable to connect a desired subset of the delay elements between input and output nodes of the respective delay blocks. The subsets of the delay elements in the two delay blocks are connected in series. The ratio of the number of delay elements programmed to form each of the two subsets determines a delay provided as an output by the DLL. In operation, a phase discriminator and a loop filter in combination with the programmed subsets in the delay blocks, operate to generate an analog error signal to compensate for process, temperature and voltage (PTV) variations in the delay provided as an output by the DLL. | 05-17-2012 |
| 20120119696 | Devices And Methods For Detecting USB Devices Attached To A USB Charging Port - Methods and devices for detecting USB devices attached to a USB charging port are disclosed. The USB charging port includes a USB port having a first data line D+, a second data line D−, and a power line. A method includes attaching the USB device to the USB port; applying power to the USB device by way of the power line; applying a first voltage to the line D+ at the USB port by way of a first impedance; applying a second voltage to the line D− at the USB port by way of a second impedance. The voltages on the line D+ and the line D− are then monitored at the USB port. If the voltage on the line D+ is approximately equal to a first predetermined value for a predetermined period and the voltage on the line D− is below a second predetermined value, then the USB device is determined to be of an alpha type device. | 05-17-2012 |
| 20120119364 | ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING - An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening. | 05-17-2012 |
| 20120119343 | STACKED LEADFRAME IMPLEMENTATION FOR DC/DC CONVERTOR POWER MODULE INCORPORATING A STACKED CONTROLLER AND STACKED LEADFRAME CONSTRUCTION METHODOLOGY - Methods and systems are described for enabling the efficient fabrication of small form factor power converter packages and other devices using stacked leadframes. | 05-17-2012 |
| 20120117519 | METHOD OF TRANSISTOR MATCHING - A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to forming a photomask. A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to printing a gate pattern and optionally printing an active pattern on a wafer. | 05-10-2012 |
| 20120117435 | PARALLEL AND SERIAL ACCESS TO TEST COMPRESSION ARCHITECTURES - The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure. | 05-10-2012 |
| 20120117434 | PROBELESS TESTING OF PAD BUFFERS ON WAFER - The peripheral circuitry ( | 05-10-2012 |
| 20120117360 | DEDICATED INSTRUCTIONS FOR VARIABLE LENGTH CODE INSERTION BY A DIGITAL SIGNAL PROCESSOR (DSP) - In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The DSP selectively uses a dedicated insert instruction to insert a variable number of bits into a register. | 05-10-2012 |
| 20120114054 | Systems and Methods for Low-Complexity Max-Log MIMO Detection - Embodiments provide novel systems and methods for multiple-input multiple-output (MIMO) Max-Log detection. These systems and methods enable near-optimal performance with low complexity for a two-input two-output channel. Some embodiments comprise using a Max-Log detector to compute a set of log-likelihood ratio (LLR) values for a channel input by minimizing cost function while computing only one instance of the cost function for each value of each bit in a symbol. Other embodiments comprise using a Max-Log detector to compute a set of log-likelihood ratio (LLR) values for a channel input by computing all instances of a cost function for each value of each bit in a symbol and selecting the minimum cost from all computed instances of the cost function for each value of each bit. | 05-10-2012 |
| 20120113921 | Adaptive Selection of Transmission Parameters for Reference Signals - A method and apparatus for defining transmission parameters of user equipment reference signals. The method includes estimating channel delay spreads of a plurality of user equipments scheduled for transmission at a particular transmission time period or sub-frame in an uplink for communication with a NodeB, and allocating transmission parameters to each scheduled user equipment of the plurality of user equipments in accordance to the delay spreads of the plurality of user equipments scheduled for transmission in the particular time period or sub-frame, wherein the parameters comprises a cyclic shift allocated to each m-th user equipment equal to the sum of a delay spread and a timing uncertainty of each of the previous m-1 user equipments. | 05-10-2012 |
| 20120113701 | INVERTER CURRENT MEASUREMENT USING A SHUNT RESISTOR - A method for determining each current output of a three-phase inverter ( | 05-10-2012 |
| 20120112941 | Systems and Methods for Analog to Digital Converter Charge Storage Device Measurement - Systems and methods for analog to digital conversion charge storage device measurement are presented. In multi-cell charge storage device monitoring systems, accurate measurement of cell voltages is used for protection of the multi-cell device. The disclosed cell referenced solution converts the cell voltage to a digital representation referenced at the cell voltage. The digital representation referenced to the cell voltage is then level shifted to a ground referenced signal suitable for digital post processing. This processing may be used for fault detection of over-voltage, under-voltage, open cell, and similar fault conditions and cell capacity measurements. An example embodiment implements a sigma delta modulator to perform the signal transformation from analog to digital. The disclosed systems and methods may be differential and stackable for multiple cells. | 05-10-2012 |
| 20120112826 | ACTIVE LOW PASS FILTER - Sallen-Key active low pass filters (LPFs) have been knows for many years; however, these LPFs generally include passive components (i.e., resistors and capacitors) and active components (i.e., amplifiers) that are within the direct signal path that can contribute to the noise at the output of the filter within the pass band. Here, an LPF (which has the same general behavior as a Sallen-Key LPF) has been provided that AC couples passive components and active components to the direct signal path so as to suppress the noise contribution in the pass band. | 05-10-2012 |
| 20120112823 | METHOD TO MATCH SOI TRANSISTORS USING A LOCAL HEATER ELEMENT - An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. | 05-10-2012 |
| 20120112822 | DIFFERENTIAL INPUT FOR AMBIPOLAR DEVICES - Differential input pairs have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional designs for differential input pairs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a differential input pair has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors. | 05-10-2012 |
| 20120112733 | Hall Effect Device - A Hall effect device includes a Hall element and a voltage regulator. The Hall element has first and second bias terminals, or nodes. The Hall effect device maintains, or regulates, a voltage at a point within the Hall element between the first and second bias terminals at about a constant voltage level, while generating a Hall effect voltage. In particular embodiments, the Hall effect voltage is, thus, prevented from substantially varying with the temperature of the Hall element. | 05-10-2012 |
| 20120112686 | LOW-VOLTAGE DUAL-POWER-PATH MANAGEMENT ARCHITECTURE FOR RECHARGEABLE BATTERY MONITORING SOLUTIONS - A control circuit of a battery power-path management circuit establishes a first power path between a battery input node and an output node when the input node voltage is larger than a charger input node voltage and a second power path between the charger input node and the output node when the voltage on the charger input node is larger than the battery input node voltage. It controls the second power path to provide power to the output node, enabling battery charging and protection over a battery voltage range from about zero volts. It has low power consumption and can support wide-swing power supply voltage from as low as one volt to as high as maximum allowed Vds of drain-extended devices. It can use smaller device sizes because the PMOS switch gate voltage is 0V when the power supply is not too high. | 05-10-2012 |
| 20120112343 | ELECTROPLATED POSTS WITH REDUCED TOPOGRAPHY AND STRESS - Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height. | 05-10-2012 |
| 20120112286 | ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE STRING - An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. | 05-10-2012 |
| 20120112277 | INTEGRATED LATERAL HIGH VOLTAGE MOSFET - An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate. | 05-10-2012 |
| 20120112275 | Drain Extended CMOS with Counter-Doped Drain Extension - An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region. | 05-10-2012 |
| 20120110659 | LESS-SECURE PROCESSORS, INTEGRATED CIRCUITS, WIRELESS COMMUNICATIONS APPARATUS, METHODS AND PROCESSES OF MAKING - An integrated circuit ( | 05-03-2012 |
| 20120110351 | POWER MANAGEMENT FOR DIGITAL DEVICES - In a digital device, activity of (or load on) one or more processors, peripherals and memory buses are measured. A power management framework operated in the digital device bases power settings in the digital device on the measured loads, and accordingly issues power management commands to change power consumption states of one or more of the processors, peripherals and memory buses. Some user applications (termed power aware applications) in the digital device provide a number identifying their application type to the power management framework, which thereby determines the resources required by the application. The power management commands issued by the power management framework ensure provision of the corresponding resources to the application, while also targeting minimization of power consumption in the digital device. In an embodiment, the digital device corresponds to a mobile phone. | 05-03-2012 |
| 20120108076 | SHOWERHEAD FOR CVD DEPOSITIONS - A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer. | 05-03-2012 |
| 20120108068 | Method for Patterning Sublithographic Features - A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern. | 05-03-2012 |
| 20120108066 | PECVD SHOWERHEAD CONFIGURATION FOR CMP UNIFORMITY AND IMPROVED STRESS - A dielectric deposition tool for forming a silicon dioxide layer on a wafer with a TEOS showerhead which delivers a flow rate per unit area from an edge band of the showerhead that is at least twice a flow rate per unit area from a central region of the showerhead. The edge band extends at least one half inch from an outer edge of the showerhead up to one fourth of the diameter of the wafer. A process of forming an integrated circuit by forming a silicon dioxide layer on a wafer containing the integrated circuit using the dielectric deposition tool. The silicon dioxide layer is thicker under the edge band than under the central region. A subsequent CMP operation reduces the thickness difference between the wafer outer annulus and the wafer core by at least half. The silicon dioxide layer has a compressive stress between 125 and 225 MPa. | 05-03-2012 |
| 20120108027 | IMPROVED SILICIDE METHOD - A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide. | 05-03-2012 |
| 20120108021 | PMOS SiGe-LAST INTEGRATION PROCESS - A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses. | 05-03-2012 |
| 20120108020 | LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW - A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow. | 05-03-2012 |
| 20120107729 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES - A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W | 05-03-2012 |
| 20120107552 | Chip Attachment Layer Having Traverse-Aligned Conductive Filler Particles - A method for conductively attaching a workpiece ( | 05-03-2012 |
| 20120106614 | SYSTEM AND METHOD FOR CHANNEL INTERPOLATION - A system and method for channel interpolation in a wireless device. In one embodiment a wireless device includes a channel estimator. The channel estimator is configured to generate estimated channel coefficients for a wireless channel over which the wireless device receives a packet. The channel estimator includes an interpolation filter. The interpolation filter is configured to provide interpolated channel coefficients for a plurality of non-pilot sub-carriers. The interpolated channel coefficients are based on pilot sub-carriers of non-preamble symbols. | 05-03-2012 |
| 20120106611 | PHASE LOCKING LOOP - A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL is configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received by the wireless receiver. The PLL includes a loop bandwidth controller. The loop bandwidth controller is configured to set a bandwidth of the PLL to a first value for reception of an initial symbol of the packet. The loop bandwidth controller is configured to reduce the bandwidth of the PLL over a number of symbols preceding an initial header of the packet. | 05-03-2012 |
| 20120106609 | SYSTEM AND METHOD FOR CHANNEL CLASSIFICATION - A system and method for classifying a channel with regard to delay spread in a wireless network applying orthogonal frequency division multiplexing. In one embodiment, a wireless receiver includes a channel classifier. The channel classifier is configured to compute a channel estimate corresponding to a channel traversed by a packet received by the wireless receiver. The channel classifier is also configured to partition the channel estimate into a plurality of windows. Each window corresponds to a range of time of the channel estimate. The channel classifier is further configured to assign a delay spread classification to the channel based on a distribution of energy across the windows. | 05-03-2012 |
| 20120106602 | Signaling in a Medical Implant Based System - Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes transmitting bits modulated with a first predefined sequence of a plurality of predefined sequences by a first medical transceiver. The first predefined sequence is detected by a second medical transceiver when the second medical transceiver enters into an active state. A predetermined action is preformed if the first predefined sequence is detected. | 05-03-2012 |
| 20120106528 | UNIFIED PROTOCOL STACK FOR COLOCATED WIRELESS TRANSCEIVERS - A system and method for accessing a wireless network via unified protocol stack. In one embodiment a wireless networking system includes a wireless device. The wireless device includes a first wireless transceiver, a second wireless transceiver, a processor, and a unified protocol stack. The first wireless transceiver is configured for communication via a first wireless network. The second wireless transceiver is configured for communication via a second wireless network. The unified protocol stack includes first protocols defined for accessing the first wireless network and second protocols defined for accessing the second wireless network. The unified protocol stack includes instructions that cause the processor to access the first wireless network via the first wireless transceiver using one of the second protocols. | 05-03-2012 |
| 20120106418 | CLIENT' DEVICE POWER REDUCTION IN WIRELESS NETWORKS HAVING NETWORK-COMPUTED CLIENT' LOCATION - A method of reducing client power consumption in a wireless network including a network server which provides computed client' locations, at least one access point (AP), and a plurality of wireless stations (STAs) including a first wireless station (STA1). The AP periodically sends beacon frames that span a beacon period, wherein at least a first beacon frame is sent during the beacon period. The STA1 sends a location request frame to the AP requesting a STA1 location. During the beacon period the STA1 wakes up from a powersave (PS) mode or a sleep mode and sends a PSPoll frame to the AP. Responsive to the PSPoll frame, the AP replies with a priority response being a data frame including a location response packet including the STA1 location or a Null frame if the STA1 location is not available. | 05-03-2012 |
| 20120106381 | SYSTEM AND METHOD FOR SOFT ACCESS POINT POWER REDUCTION - A system and method for reducing power consumption of a wireless device operating as a soft access point. In one embodiment, a wireless device includes a soft access point controller that configures the wireless device to operate as a group owner in a peer-to-peer wireless local area network. The soft access point controller includes a beacon controller. The beacon controller is configured to transmit beacon frames at a first periodic interval. The beacon controller is also configured to extend a discovery interval of a wireless station by transmitting acknowledgement packets at a second periodic interval. The second periodic interval is shorter than the first periodic interval and shorter than a minimum discovery scan timeout of the wireless station. | 05-03-2012 |
| 20120106225 | Array-Based Integrated Circuit with Reduced Proximity Effects - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 05-03-2012 |
| 20120106211 | POWER FACTOR AND LINE DISTORTION METHOD AND APPARATUS - Today, power distribution systems can be used to supply power to many loads, and since many loads, such as servers, are reactive (i.e., have capacitors and/or inductors), line distortion and power factor can be an issue. Conventional techniques to correct for line distortion and power factor use a specialized circuit that is generally in series with the load, but these specialized circuits can be prohibitively expensive when used in large numbers. Here, however, a corrective power supply has been provided, which can correct for other parallel power supplies that can reduce cost. | 05-03-2012 |
| 20120105992 | METHOD AND CIRCUITRY FOR PROGRAMMABLY CONTROLLING DEGAUSS WRITE CURRENT DECAY IN HARD DISK DRIVES - A control circuit to provide a control current to control an amplitude of a write current in a magnetic media drive. The control circuit has an output circuit for providing the control current with an amplitude dependent on a bias voltage. A bias current path provides the bias voltage to the output circuit, and a current diverting circuit is connected to divert current from the bias current path. A programmable ramp voltage generator operates in response to a degauss enable signal, and a voltage-to-current converter receives the programmable ramp voltage to control the current diverting circuit to divert current from the bias current path at a rate determined by the programmable ramp voltage. The bias voltage and the write current decay according to the programmable ramp voltage. The write current decay can be made linear and independent of a beginning write current amplitude. | 05-03-2012 |
| 20120105261 | ADC CHANNEL SELECTION AND CONVERSION - A microcontroller includes a microcontroller core and an analog-to-digital converter (“ADC”) coupled to said microcontroller core. The ADC has multiple input channel multiplexers that are configured to receive multiple analog input channels. The microcontroller further includes a selection register and a data structure. The data structure comprises a plurality of associated field sets. Each bit position in the selection register indexes to one of the associated field sets in the data structure, and the value contained in each such bit position indicates whether or not to select the corresponding associated field set for selection of an analog input channel. Each associated field set comprises one or more values collectively specifying an analog input channel to select for conversion to digital form. | 05-03-2012 |
| 20120105046 | CURRENT MIRROR USING AMBIPOLAR DEVICES - Current mirrors have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional current minor designs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a current minor has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors. | 05-03-2012 |
| 20120105009 | SYSTEMS AND METHODS FOR DETERMINING BATTERY STATE OF CHARGE | 05-03-2012 |
| 20120104604 | CRACK ARREST VIAS FOR IC DEVICES - An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads. | 05-03-2012 |
| 20120104540 | TRENCH WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion. | 05-03-2012 |
| 20120104539 | TRENCHES WITH REDUCED SILICON LOSS - An isolation trench in a substrate of a semiconductor device includes a first shallow portion with a dielectric sidewall and a second deeper portion without a dielectric sidewall. The isolation trench is formed by forming a first shallow portion of the trench, forming dielectric sidewalls on the first shallow portion, and then etching the substrate below the first shallow portion to form the second deeper portion. Shallow isolation trenches may be formed simultaneously with the etching of the second deeper portion. | 05-03-2012 |
| 20120104510 | CMOS PROCESS TO IMPROVE SRAM YIELD - An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. | 05-03-2012 |
| 20120104503 | TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND PROCESS FOR FABRICATION - A transistor is formed in a semiconductor substrate with a gate over a channel region, source/drain extension regions in the substrate adjacent the channel region, and source/drain regions in the substrate adjacent the source/drain extension regions. Silicide is formed on the source/drain extension regions and the source/drain regions so that the silicide has a first thickness over the source/drain extension regions and a second thickness over source/drain regions, with the second thickness being greater than the first thickness. Silicide on the source/drain extension regions lowers transistor series resistance which boosts transistor performance and also protects the source/drain extension regions from silicon loss and silicon damage during contact etch. | 05-03-2012 |
| 20120104497 | HIGH VOLTAGE DRAIN EXTENSION ON THIN BURIED OXIDE SOI - An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel). | 05-03-2012 |
| 20120104493 | LATERAL SUPERJUNCTION EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer. | 05-03-2012 |
| 20120102730 | MIRROR ASSEMBLY WITH RECESSED MIRROR - A mirror device and a method for manufacturing the mirror device are presented. The mirror device includes a mirror formed from a first substrate and a hinge/support structure formed from a second substrate. The hinge/support structure includes a recessed region and a torsional hinge region. The mirror is coupled to the hinge/support structure at the recessed region. Further, a driver system is employed to cause the mirror to pivot about the torsional hinge region. | 05-03-2012 |
| 20120102443 | N/P CONFIGURABLE LDMOS SUBCIRCUIT MACRO MODEL - A process of operating a computer system to create a subcircuit model of an N/P configurable extended drain MOS transistor in which the subcircuit model includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A process of operating a computer system to simulate the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor in which a subcircuit model of the N/P configurable extended drain MOS transistor includes an npn bipolar transistor and a pnp bipolar transistor which correspond to current paths through n-channel drift lanes and p-channel drift lanes during dual mode operation. A computer readable medium storing an electronic circuit simulation program that generates a simulation output of the behavior of an electronic circuit including a N/P configurable extended drain MOS transistor. | 04-26-2012 |
| 20120102441 | MARKER LAYER TO FACILITATE MASK BUILD WITH INTERACTIVE LAYERS - A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site. | 04-26-2012 |
| 20120102375 | AT-SPEED TEST ACCESS PORT OPERATIONS - This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements. | 04-26-2012 |
| 20120100717 | TRENCH LITHOGRAPHY PROCESS - A process of forming an integrated circuit using a dual damascene interconnect process by etching a via hole in an ILD and filling the via hole with a sacrificial via fill material. A trench etch hard mask layer is formed over the ILD. An inorganic hard mask layer is formed over the trench etch hard mask layer. The inorganic hard mask layer is etched to form an etch mask for the trench etch hard mask layer, which is subsequently etched to form an etch mask for the trench etch process. The sacrificial via fill material etches at a comparable rate to the ILD layer. The trench etch hard mask layer is removed and the sacrificial via fill material is removed from the via hole. | 04-26-2012 |
| 20120100680 | Low Temperature Implant Scheme to Improve BJT Current Gain - A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region. | 04-26-2012 |
| 20120100679 | THICK GATE OXIDE FOR LDMOS AND DEMOS - A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. | 04-26-2012 |
| 20120099628 | Symbol-Level Repetition Coding in Power Line Communications - Systems and methods for implementing symbol-level repetition coding in power line communications (PLC) are described. In some embodiments, these systems and methods may provide reliable communication in severe channel environments of PLC networks, at least in part, by changing the forward error correction (FEC) used by various devices operating within current PLC systems. For example, a method may include receiving a PLC signal and applying convolutional encoding to the received signal, the convolutional encoding producing an encoded signal. The method may also include performing a subcarrier modulation operation upon the encoded signal, the subcarrier modulation operation producing a modulated signal. The method may further include applying symbol-level repetition coding to the modulated signal, the symbol-level repetition coding producing a repetitious signal. In some cases, one or more distinct repetition patterns may be applied to different symbols or portions thereof. The repetitious signal may then be transmitted over a power line. | 04-26-2012 |
| 20120098590 | QUANTUM ELECTRO-OPTICAL DEVICE USING CMOS TRANSISTOR WITH REVERSE POLARITY DRAIN IMPLANT - A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode. | 04-26-2012 |
| 20120098572 | LATCHED COMPARATOR HAVING ISOLATION INDUCTORS - Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths). | 04-26-2012 |
| 20120098512 | ELECTRONIC DEVICE AND METHOD FOR DC-DC CONVERSION - An electronic device for DC-DC conversion including a feedback loop coupled at one side to the inductor for measuring a current through the inductor with a series of an auxiliary capacitor and an auxiliary resistor, a transconductance stage coupled to the auxiliary capacitor for generating a current proportional to a voltage drop across the auxiliary capacitor, wherein the electronic device further includes a ramp resistor coupled to the output of the transconductance stage for generating a ramp voltage across the ramp resistor and a comparator receiving at a first input the ramp voltage, wherein the output of the comparator is coupled to a gate driving stage for driving a power transistor coupled with a control gate to the gate driving stage and with a channel to a switching node of the electronic device. | 04-26-2012 |
| 20120098098 | STACKED ESD CLAMP WITH REDUCED VARIATION IN CLAMP VOLTAGE - An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed. | 04-26-2012 |
| 20120098071 | High Sheet Resistor in CMOS Flow - An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates. | 04-26-2012 |
| 20120098069 | NEUTRALIZATION CAPACITANCE IMPLEMENTATION - Neutralization capacitances are commonly employed to compensate for the Miller effect; however, at higher frequencies, the parasitic inductance introduced in the interconnect can affect the neutralization. Here, a layout has been provided where a MOS capacitor is merged with a complementary transistor. By having this merged device, the layout is compact and reduces interconnect area, which reduces the effects of parasitic inductance at higher frequencies (i.e., millimeter wave or terahertz). This layout can also be used to implement linearity enhancement schemes. | 04-26-2012 |
| 20120098065 | LOW RESISTANCE LDMOS WITH REDUCED GATE CHARGE - An integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate. A process of forming an integrated circuit containing an MOS transistor with a drain drift region adjacent to the channel region, a field oxide element in the drain region, a first gate section over the channel region and a second gate section over the field oxide element, with a gap between the gate sections so that at least half of the drift region is not covered by gate, so that the source/drain implant is blocked from the drift region below the gap. | 04-26-2012 |
| 20120098062 | HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions. | 04-26-2012 |
| 20120098045 | Zero Temperature Coefficient Capacitor - A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×10 | 04-26-2012 |
| 20120097095 | Thermal Method to Control Underfill Flow in Semiconductor Devices - Apparatus for assembling a semiconductor device has a plate with body and a surface heatable to a controlled a temperature profile from location to location across the plate. Mesas at same temperature of plate protrude from the surface are configured to support a portion of the substrate. Movable capillaries have openings for blowing cooled gas onto selected locations of the assembly. At least one movable syringe movable has an opening for dispensing a polymer precursor. | 04-26-2012 |
| 20120096325 | In or relating to 1149.1tap linking modules - Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 04-19-2012 |
| 20120096324 | TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT - The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure. | 04-19-2012 |
| 20120094441 | Semiconductor Chip Attach Configuration Having Improved Thermal Characteristics - An array of metal bodies are attached to a metal carrier by forming Metal bodies form metal inter-diffusions with carrier. The metal bodies are coined to form flattened body ends. A polymeric adhesive precursor is disposed onto the array and a semiconductor chip having a first surface including circuitry and an opposite second surface free of circuitry is attached to the adhesive precursor so that the second chip surface is in contact with the flattened ends of the arrayed metal bodies, which stop at the second surface. | 04-19-2012 |
| 20120093198 | Building, Transmitting, and Receiving Frame Structures in Power Line Communications - Systems and methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols based on a chirp signal that yields a low peak-to-average power ratio (PAPR). According to some techniques, the preamble may be constructed with one or more different types and/or number of symbols configured to identify a PLC domain operating in close physical proximity to another PLC domain. According to other techniques, one or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise. According to yet other techniques, a PLC detector may be capable of receiving and decoding two or more types of PLC frames (e.g., using different PLC standards). | 04-19-2012 |
| 20120092458 | Method and Apparatus for Depth-Fill Algorithm for Low-Complexity Stereo Vision - A method and apparatus for depth-fill algorithm for low-complexity stereo vision. The method includes utilizing right and left images of a stereo camera to estimate depth of the scene, wherein the estimated depth relates to each pixel of the image, and updating a depth model with the current depth utilizing the estimated depth of the scene. | 04-19-2012 |
| 20120092200 | SIGMA-DELTA MODULATOR - A Sigma-Delta Modulator (SDM) has a summing junction that receives an input signal and a feedback signal, a multi-level analog-to-digital converter (ADC) that receives the SDM input signal and generates an ADC output, a first analog switch that receives the ADC output and generates a plurality of reference voltages, a second analog switch generating the feedback signal, where the feedback signal is selected from one of the reference voltages. | 04-19-2012 |
| 20120092199 | PIPELINED ADC HAVING A THREE-LEVEL DAC ELEMENTS - In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used. | 04-19-2012 |
| 20120092051 | 1 TO 2N-1 FRACTIONAL DIVIDER CIRCUIT WITH FINE FRACTIONAL RESOLUTION - A fractional divider has been provided that allows for division ratios of 1:1 to 1:2 | 04-19-2012 |
| 20120091531 | Flexible Integration of Logic Blocks with Transistors of Different Threshold Voltages - An integrated circuit constructed according to an arrangement of logic blocks, with one or more logic blocks including transistors of a different threshold voltage than in other logic blocks. Spacing between neighboring active regions of different threshold voltages is minimized by constraining the angle of implant for the threshold adjust implant, and by constraining the thickness of the mask layer used with that implant. These constraints ensure adequate implant of dopant into the channel region while blocking the implant into channel regions not subject to the threshold adjust, while avoiding shadowing from the mask layer. Efficiency is attained by constraining the direction of implant to substantially perpendicular to the run of the gate electrodes in the implanted regions. | 04-19-2012 |
| 20120090438 | PLUNGER/CAVITY COOPERATION WITHOUT CREATION OF SUCTION FORCE DURING WITHDRAWAL - A cavity for receiving insertion of a plunger is designed so that the plunger may be withdrawn without permitting creation of a suction force sufficient to remove from the cavity a workpiece that the plunger carried into the cavity. | 04-19-2012 |
| 20120089878 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 04-12-2012 |
| 20120087565 | METHOD AND APPARATUS FOR ENHANCING REPRESENTATIONS OF MICRO-CALCIFICATIONS IN A DIGITAL MAMMOGRAM IMAGE - Method and apparatus for enhancing representations of micro-calcifications in a digital mammogram image. The method includes smoothing the digital mammogram image using a fuzzy smoothing technique to yield a fuzzy smoothed image. The method includes subtracting the fuzzy smoothed image from the digital mammogram image to yield a micro-calcifications enhanced image. The method includes scaling gray level values of pixels in the micro-calcifications enhanced image by a predetermined amount to provide a digital mammogram image with enhanced representations of the micro-calcifications. Apparatus for enhancing representations of micro-calcifications includes an image processing unit that uses an image acquisition unit to receive an image and a digital signal processor to process the image to provide a digital mammogram image with enhanced representations of micro-calcifications. | 04-12-2012 |
| 20120086590 | METHOD FOR CALBRATING A PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR - Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise. | 04-12-2012 |
| 20120086589 | PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR - Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise. | 04-12-2012 |
| 20120086509 | Amplifier Input Stage and Slew Boost Circuit - Various apparatuses, methods and systems for boosting an amplifier slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a pair of inputs connected to a pair of differential input devices in an amplifier, a current source, a first current path connected to the current source, a second current path connected to the current source and to the pair of differential input devices, a switch in the first current path, and a voltage difference signal connected between the pair of inputs and the switch. The voltage difference signal represents the voltage difference between the pair of inputs. The conductance of the switch is inversely proportional to the voltage difference signal. | 04-12-2012 |
| 20120086505 | SWITCHING CORE LAYOUT - Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection. | 04-12-2012 |
| 20120086489 | ADAPTIVE QUADRATURE CORRECTION FOR QUADRATURE CLOCK PATH DESKEW - Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry. | 04-12-2012 |
| 20120086479 | Controlling Power Chain with Same Controller in Either of Two Different Applications - A controller for controlling a power chain in an electronic device can be used in either of two different applications. The first application requires the controller to produce drive signals for driving discrete power MOSFETs within the power chain. The second application requires the controller to produce an output PWM signal to control an integrated circuit having power MOSFETs integrated with MOSFET drivers within the power chain. The controller generally includes a sensor that detects which of the two applications the controller is in. The controller also generally includes outputs that produce, when the controller is in the first application, the drive signals for driving the discrete power MOSFETs. But when the controller is in the second application, one of the outputs is used to produce the output PWM signal for controlling the integrated circuit. | 04-12-2012 |
| 20120086112 | Multi-Component Electronic System Having Leadframe with Support-Free Cantilever Leads | 04-12-2012 |
| 20120086098 | IONIC ISOLATION RING - There has been very little (if any) attention to address contamination diffusion within an integrated circuit (IC) because there are very few applications where a protective overcoat will be penetrated as part of the manufacturing process. Here, a sealing ring is provided that address this problem. Preferably, the sealing ring uses the combination of electrically conductive barrier rings and the tortuous migration path to allow an electronic device (i.e., thermopile), where a protective overcoat is penetrated during manufacture, to communicate with external devices while being isolated to prevent contamination. | 04-12-2012 |
| 20120084614 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 04-05-2012 |
| 20120084613 | SCAN RESPONSE REUSE METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure. | 04-05-2012 |
| 20120082392 | METHOD AND APPARATUS FOR FRAME CODING IN VERTICAL RASTER SCAN ORDER FOR HEVC - A method and apparatus for frame coding in adaptive raster scan order. The method includes encoding at least one of image or video utilizing input frames and at least one of a data related to the input frame to produce bitstream with raster scan order information and displacement information for producing compressed video bitstream, at decoding time, decoding at least one of the encoded bitstream with raster scan order information and displacement information for producing compressed video bitstream. | 04-05-2012 |
| 20120082279 | PLURAL CIRCUIT SELECTION USING ROLE REVERSING CONTROL INPUTS - Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits. | 04-05-2012 |
| 20120082253 | Pilot Structure for Coherent Modulation - A system and method for communicating in a power line communications (PLC) network using Orthogonal Frequency-Division Multiplexing (OFDM) symbols. Pilot tones are carried by the OFDM symbols according to a predetermined pattern. A receiving device identifies pilot tones on each frequency. A group of previously received pilot tones on a selected frequency are filtered to generate a channel estimate for a tone on the selected frequency in a new symbol. The channel estimates on two different frequencies within an OFDM symbol may be interpolated to determine a channel estimate for a third frequency with the OFDM symbol. | 04-05-2012 |
| 20120082233 | METHOD AND APPARATUS FOR DIAGONAL SCAN AND SIMPLIFIED CONTEXT SELECTION FOR PARALLEL ENTROPY CODING OF SIGNIFICANCE MAP OF TRANSFORM COEFFICIENTS - A method and apparatus for encoding bit code utilizing context dependency simplification to reduce dependent scans. The method includes retrieving at least one 2 dimensional array of transform coefficient, transforming the at least one 2 dimensional array of the significance map of the transform coefficient to a 1 dimensional coefficient scanning and determining at least one of scan direction, coding unit type and slice type assigned to transform coefficient, selecting neighbors based on at least one of scan direction and coding unit type and slice type, computing context index based on the values of the selected neighbors for context selection, and performing arithmetic coding to generate coded bit utilizing the computed context index and binarization. | 04-05-2012 |
| 20120081832 | Chip Capacitor Precursors - A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps. | 04-05-2012 |
| 20120080595 | NON-CONTACT DETERMINATION OF JOINT INTEGRITY BETWEEN A TSV DIE AND A PACKAGE SUBSTRATE - A non-contact voltage contrast (VC) method of determining TSV joint integrity after partial assembly. A TSV die is provided including TSVs that extend from a frontside of the TSV die to TSV tips on a bottomside of the TSV die. At least some TSVs (contacting TSVs) are attached to pads on a top surface of a multilayer (ML) package substrate. The ML package substrate is on a substrate carrier that blocks electrical access to the frontside of the TSV die. Two or more nets including groups of contacting TSVs are tied common within the ML substrate. A charged particle reference beam is directed to a selected TSV within a first net and a charged particle primary beam is then rastered across the TSVs in the first net. VC signals emitted are detected, and joint integrity for the contacting TSVs to pads of the ML package substrate is determined from the VC signals. | 04-05-2012 |
| 20120079717 | Assembly Method for Converting the Precursors to Capacitors - A method of assembling a packaged semiconductor device includes dropping a pre-formed capacitor precursor on a surface of a substrate. A pair of vias are formed in the pre-formed capacitor precursor if they don't already exist. The vias are filled with an electrically conductive material to form a chip capacitor. The filling of the vias provides an electrical contact between capacitor plates of the chip capacitor and electrically conductive contact regions on the substrate. | 04-05-2012 |
| 20120079333 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 03-29-2012 |
| 20120077537 | SYSTEMS AND METHODS OF WIRELESS POWER TRANSFER WITH INTERFERENCE DETECTION - Performance of wireless charging systems may be significantly degraded when parasitic metal objects come in close proximity to the transmitting coil. Some of the transmitted energy may be coupled by these metal objects and wasted as heat. This may create a danger as the metal objects may get hot enough to create a fire hazard, to cause plastic parts deformation, or operator skin burns when touched. | 03-29-2012 |
| 20120077287 | DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES - A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. | 03-29-2012 |
| 20120076241 | MULTIPLE-INPUT MULTIPLE-OUTPUT WIRELESS TRANSCEIVER ARCHITECTURE - A wireless transceiver includes a receiver and a transmitter, the receiver and transmitter implemented to have multiple receive and transmit channels respectively, to provide multiple-input multiple-output (MIMO) capability. In an embodiment, the transceiver is implemented to include two transmit channels and two receive channels. Some blocks/circuitry of each of the receive and transmit channels are implemented with reduced area and current consumption, with a corresponding increase in noise. In a single-input single-output (SISO) mode of operation, the receiver combines the output of both the receive channels to compensate for the increase in noise due to the implementation with smaller area and lower current consumption. Similarly, the transmitter combines the output of both the transmit channels to compensate for the increase in noise. The transceiver operates with no signal degradation in SISO mode, and with a small degradation in signal quality in the MIMO mode. | 03-29-2012 |
| 20120076211 | Systems and Methods for Facilitating Power Line Communications - Systems and methods for facilitating power line communications are described. In some embodiments, a PLC device may detect the availability of a first frequency band as well the availability of a combination of a second frequency band with a third frequency band. The PLC device may then communicate with another PLC device using a frequency band selected as (a) at least a portion of a combination of the first, second, and third frequency bands, (b) at least a portion of the first frequency band, or (c) at least a portion of the combination of the second with third frequency bands. The PLC device may further transmit a message to a higher-level PLC apparatus (e.g., a domain master) over the power line using a device-based access mode, receive an instruction to switch to a domain-based access mode, and thereafter communicate with another PLC device using the domain-based access mode. | 03-29-2012 |
| 20120076176 | ELECTRONIC DEVICE AND METHOD FOR SPREAD SPECTRUM CLOCK (SSC) MODULATION - The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme. | 03-29-2012 |
| 20120074987 | ELECTRONIC DEVICE AND METHOD FOR BUFFERING - A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode. | 03-29-2012 |
| 20120074980 | SCRIBE LINE TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS FOR ICs INCLUDING MOS DEVICES - An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters. | 03-29-2012 |
| 20120074973 | ON-DIE PARAMETRIC TEST MODULES FOR IN-LINE MONITORING OF CONTEXT DEPENDENT EFFECTS - An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters. | 03-29-2012 |
| 20120074479 | AREA-EFFICIENT ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY CELL - Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed. | 03-29-2012 |
| 20120074458 | QUASI-VERTICAL GATED NPN-PNP ESD PROTECTION DEVICE - Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process. | 03-29-2012 |
| 20120070993 | PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS - A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region. | 03-22-2012 |
| 20120070939 | STACKED DIE ASSEMBLIES INCLUDING TSV DIE - A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies. | 03-22-2012 |
| 20120069931 | MULTI-BAND POWER AMPLIFIER DIGITAL PREDISTORTION SYSTEM AND METHOD - Traditionally, for multi-band communication systems, independent signal chains for each of the different bands are employed. By using such an architecture, there are a large number of components, and there is substantial power consumption. Here, transmit processor is provided that enables transmission across multiple bands using few components (namely, fewer signal chains), while also provided for digital predistortion. | 03-22-2012 |
| 20120068891 | CHIP TO DIELECTRIC WAVEGUIDE INTERFACE FOR SUB-MILLIMETER WAVE COMMUNICATIONS LINK - In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. | 03-22-2012 |
| 20120068890 | HIGH SPEED DIGITAL INTERCONNECT AND METHOD - In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. | 03-22-2012 |
| 20120068883 | Method for GNSS Coexistence - A method for operating a wireless transmitter and a global navigation satellite (“GNSS”) receiver coexistent in a mobile wireless device. A mobile wireless device includes a GNSS receiver and a wireless networking system. The wireless networking system includes a wireless transmitter. The wireless transmitter provides a first interference level signal to the GNSS receiver. The first interference level signal indicates a level of interference that the GNSS receiver can expect due to operation of the transmitter. A priority signal is asserted if the processing of navigation signals in the GNSS receiver takes precedence over wireless transmitter transmissions. | 03-22-2012 |
| 20120068784 | Coupling Circuits for Power Line Communication Devices - Coupling circuits for power line communication (PLC) devices are described. In an embodiment, a PLC device may comprise a processor and a coupling circuit coupled to the processor. The coupling circuit may in turn comprise a transmitter path and a receiver path. In some implementations, the transmitter path may include a first amplifier, a first capacitor coupled to the first amplifier, a first transformer coupled to the first capacitor, and a plurality of line interface coupling circuits coupled to the first transformer, where each of the line interface coupling circuits is configured to be connected to a different phase of an electrical power circuit. Meanwhile, the receiver path may include a plurality of capacitors, where each of the plurality of capacitors coupled to a corresponding one of the line interface circuits, a filter network coupled to the plurality of capacitors, and a second amplifier coupled to the filter network. | 03-22-2012 |
| 20120068238 | LOW IMPEDANCE TRANSMISSON LINE - Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown. | 03-22-2012 |
| 20120066415 | METHODS AND SYSTEMS FOR DIRECT MEMORY ACCESS (DMA) IN-FLIGHT STATUS - In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information. | 03-15-2012 |
| 20120066162 | System and Method for Training an Adaptive Filter in an Alternate Domain with Constraints - The adaptive filtering techniques described herein allow a filter that is operating in a target domain to be trained in another domain, possibly with constraints, using the same adaptation framework used in a standard adaptive filter. As a result, the adaptation engine may be configured to run in a transform domain that is more desirable than the target domain. For example, the transform domain may be less susceptible to noise or may have more impact on the trained filter's desired results. The filter is trained in the transform domain and then the filter hardware is updated in the target domain. | 03-15-2012 |
| 20120064826 | TRANSMIT AND RECEIVE PERFORMANCE OF A NEAR FIELD COMMUNICATION DEVICE THAT USES A SINGLE ANTENNA - A near field communication (NFC) transceiver contains a transmitter portion to generate a transmit wireless signal, and a receiver portion to receive and process a receive wireless signal. The circuit further contains a shunt capacitor, a switch, and an antenna interface to couple the transmitter portion and the receiver portion to an antenna designed to communicate with external antennas by inductive coupling. The switch couples the shunt capacitor in parallel with the antenna in one operational mode, and decouples the shunt capacitor from the antenna in another operational mode. Transmit and receive performance of the NFC transceiver are enhanced as a result. | 03-15-2012 |
| 20120064686 | Lateral Uniformity in Silicon Recess Etch - A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation. | 03-15-2012 |
| 20120063497 | Systems And Methods for Implementing Application Profiles and Device Classes in Power Line Communication (PLC) Environments - Systems and methods for application profiles and device classes in power line communications (PLCs) are described. In some embodiments, a PLC device may include a processor and a memory coupled to the processor. The memory may be configured to store program instructions, which may be executable by the processor to cause the PLC device to communicate with a higher-level PLC apparatus over a power line using a frequency band. The frequency band may be selected based upon an application profile and/or a device class associated with the PLC device. In some implementations, the higher-level PLC apparatus may include a PLC gateway or a data concentrator, and the PLC device may include a PLC modem or the like. Examples of application profiles include access communications, in-premises connectivity, AC charging, and/or DC charging. Device classes may represent a minimum communication data rate and/or an operating frequency band restriction of the PLC device. | 03-15-2012 |
| 20120063395 | Network Coexistence through Active Superframe Interleaving - Embodiments of the invention provide coexistence among independent networks through active superframe interleaving. Network hubs and devices exchange signals over a selected channel only during active superframes of their network. Network hubs broadcast coexistence information during their active superframes. A hub of network B desiring to use the selected channel first attempts to fit its active superframes within network A's inactive superframes, if available. If network A is not providing inactive superframes, then the network B hub determines whether network A is willing to coexist using active superframe interleaving on the channel. If so, the network B hub sends an interleave request message to the network A hub, which may accept the message and send back an interleave response message. The network A hub then offers new inactive superframes, and the network B hub adapts the transmissions and receptions of network B to fit within these inactive superframes. | 03-15-2012 |
| 20120063340 | SYSTEM AND METHOD FOR ACCESS POINT BASED POSITIONING - Apparatus and methods for scanning for access points (APs) for wireless local area network (WLAN) positioning. In one embodiment a wireless device includes a WLAN positioning system. The WLAN positioning system includes an AP scanner. The AP scanner is configured to determine which WLAN channels are being used by APs proximate to the wireless device. The AP scanner is also configured to scan for AP transmissions only the WLAN channels determined to be used by APs proximate to the wireless device. The AP scanner is further configured to extract signal strength and AP identification information for WLAN positioning from the AP transmissions on the scanned channels. | 03-15-2012 |
| 20120063321 | CFI Signaling for Heterogeneous Networks with Multiple Component Carriers in LTE-Advanced - This invention mitigates interference in wireless telephony in heterogeneous networks having a macro base station and a low power base station. This invention attempts to avoid cross carrier scheduling on an anchor carrier and a non-anchor carrier. If cross carrier scheduling is unavoidable, then this invention attempts: (1) semi-statically signalling a CFI value on a cross-scheduled component carrier; (2) semi-statically signalling a channel quality information (CSI) value on a cross-scheduled component carrier setting a Physical Hybrid ARQ Indicator CHannel (PHICH) value to be maximum; or (3) semi-statically signalling a channel quality information (CSI) value on a cross-scheduled component carrier using Physical Control Format Indicator CHannel (PCFICH) power boosting on cross-scheduled component carriers (CC). | 03-15-2012 |
| 20120063202 | 3T DRAM CELL WITH ADDED CAPACITANCE ON STORAGE NODE - A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a third transistor connected between the storage node and a write bit line having a third control element connected to a write word line. Additionally, the DRAM cell includes a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell. A method of operating an integrated circuit having a 3T DRAM cell includes providing a memory state on a storage node of the 3T DRAM cell and extending a refresh interval of the memory state with a supplemental capacitance added to the storage node. | 03-15-2012 |
| 20120063093 | REDUCING THERMAL GRADIENTS TO IMPROVE THERMOPILE PERFORMANCE - With infrared (IR) sensors, repeatability and accuracy can become an issue when there are thermal gradients between the sensor and an underlying printed circuit board (PCB). Conventionally, a large thermal mass is included in the sensor packaging to reduce the effect from such thermal gradients, but this increase costs and size of the sensor. Here, however, a PCB is provided that includes an isothermal cage included therein that generally ensures that the temperature of the underlying PCB and sensor are about the same by including structural features (namely, the isothermal cage) that generally ensure that the thermal time constant for a path from a heat source to the thermopile (which is within the sensor) is approximately the same as thermal time constants for paths through the PCB. | 03-15-2012 |
| 20120063041 | THIN-OXIDE CURRENT CLAMP - A thin-oxide current clamp includes a clamp transistor in current-conducting relation between a voltage-sensitive circuit and a common return of a power supply, the clamp transistor responsive to a sense output signal to provide a low-resistance current flow path from the voltage-sensitive circuit to the common return and thereby clamp a voltage in the voltage-sensitive circuit. The thin-oxide current clamp also includes a current source and a reference current minor, the reference current minor providing a reference current. Further, the thin-oxide current clamp includes a sense current mirror providing a sense current. Further, the thin-oxide current clamp also includes an output transistor that receives the sense current and provides a current flow to a gate of the clamp transistors if the sense current exceeds the reference current. | 03-15-2012 |
| 20120062587 | METHOD FOR COLOR SIGNAL GAMUT MAPPING AND SATURATION BOOSTING - Methods for gamut mapping and boosting a color saturation of a color signal having multiple colors and a color value for each color. An example method includes mapping each color from a first to a second color space, adjusting each color in the mapped color signal including boosting a color saturation; determining a maximum color value of the color signal; and, in response to a determining that the maximum color value exceeds a maximum displayable color value, setting the color value of the color having the maximum color value to be equal to the maximum displayable color value and scaling color values of colors not having the maximum color value. | 03-15-2012 |
| 20120062402 | MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING - In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths. | 03-15-2012 |
| 20120062298 | FLIP-FLOP ARCHITECTURE FOR MITIGATING HOLD CLOSURE - A circuit for mitigating hold closure. The circuit includes a flip-flop having a clock input and an output. The circuit also includes a multiplexer. The multiplexer includes a select input coupled to the clock input of the flip-flop. The multiplexer also includes a first data input coupled to the output of the flip-flop. Further, the multiplexer includes an output coupled to a second data input of the multiplexer. | 03-15-2012 |
| 20120062286 | TERAHERTZ PHASED ARRAY SYSTEM - Microelectronics have now developed to the point where radiation within the terahertz frequency range can be generated and used. Here, an integrated circuit or IC is provided that includes a phased array radar system, which uses terahertz radiation. In order to accomplish this, several features are employed; namely, a lower frequency signal is propagated to transceivers, which multiplies the frequency up to the desired frequency range. To overcome the losses from the multiplication, an injection locked voltage controlled oscillator (ILVCO) is used, and a high frequency power amplifier (PA) can then be used to amplify the signal for transmission. | 03-15-2012 |
| 20120061570 | INFRARED LIGHT TRANSMISSIVITY FOR A MEMBRANE SENSOR - In conventional membrane infrared (IR) sensors, little to no attention has been paid toward transmissivity of IR near metal traces. Here, because the substrate of an integrated circuit carrying the sensor is used as a visible light filter, reflection of IR radiation back into the substrate can affect the operation and reliability of the IR sensor. As a result, an arrangement is provided that reduces the area occupied by metal lines by reducing the pitch and compacting the routing so as to reduce the effects from the reflection of IR radiation by metal traces. | 03-15-2012 |
| 20120060068 | SYNCHRONIZING A DEVICE THAT HAS BEEN POWER CYCLED TO AN ALREADY OPERATIONAL SYSTEM - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device. | 03-08-2012 |
| 20120058778 | SYSTEM AND METHOD FOR DETERMINING A POSITION OF A MOBILE WIRELESS DEVICE - A system and method for determining a position of a mobile wireless device using wireless local area network access points (APs). In one embodiment, a mobile wireless device includes an AP positioning system configured to estimate a position of the device based on locations of APs disposed about the device. The AP positioning system is configured to: 1) access an AP database; and 2) provide, to the database, one or more medium access controller (MAC) addresses and an area of interest value. The AP positioning system is also configured to retrieve, from the database: 1) location information for each AP having a provided MAC address, or located within the area of interest; and 2) at least one of: signal parameters for the APs nearby the device, a geographic area within which each MAC address can be received, and an indication of a scan type to used for identifying APs. | 03-08-2012 |
| 20120058614 | PRE-METAL DEPOSITION CLEAN PROCESS - A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC | 03-08-2012 |
| 20120056995 | Method and Apparatus for Stereo-Based Proximity Warning System for Vehicle Safety - A method and apparatus for stereo-based proximity warning system for vehicle safety. The method comprising capturing a right and a left image utilizing the right and left of stereo cameras, performing stereo analysis and depth computation for comparing and determining the depth deviation between the current depth image with the depth model, updating the depth model when there is minimal or no deviation, otherwise, performing morphological operations for clean-up and connected components analysis, and determining if the object is too close to be safe utilizing the component analysis, and generating a warning when the object is too close. | 03-08-2012 |
| 20120056297 | BALUNS FOR RF SIGNAL CONVERSION AND IMPEDANCE MATCHING - A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance. | 03-08-2012 |
| 20120045017 | TRANSFORM-BASED SYSTEMS AND METHODS FOR RECONSTRUCTING STEERING MATRICES IN A MIMO-OFDM SYSTEM - Embodiments provide a transform-based method for representing steering matrices in transmit beamforming for a multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) system. Beamforming embodiments generate a transform-based representation of steering matrices for at least a subset of sub-carriers for which channel information is known. In some embodiments, a beamformer is able to receive transform matrices information for at least a subset of channel sub-carriers, and generate corresponding channel sub-carrier steering matrices. Some embodiments of a beamformee are able to map at least a subset of channel sub-carrier steering matrices to corresponding transform matrices information prior to transmitting the transform matrix information to a beamformer. Other embodiments of a beamformer are able to receive channel information for at least a subset of sub-carriers of a channel, and compute a transform-based representation of a steering matrix for each sub-carrier for which channel information is known. | 02-23-2012 |
| 20120044718 | POWER CONVERTERS - A power converter for delivering power to a load at a regulated voltage | 02-23-2012 |
| 20120044323 | Method and Apparatus for 3D Image and Video Assessment - A method and apparatus for assessing 3 dimensional video. The method includes computing at least one of 3 dimensional quality and geometric quality, and combining two quality values for overall 3 dimensional quality assessment. | 02-23-2012 |
| 20120044020 | METHOD AND APPARATUS FOR SENSING A CURREN FOR VARYING IMPEDANCE LOADS - Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include one or more discrete components in series with the load, but this degrades performance. Here, however, circuit is provided (which includes sample-and-hold circuit) that accurately measures load currents without inhibiting performance and that is not inhibited by the phase differences between the load voltage and load current. | 02-23-2012 |
| 20120044004 | TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths. | 02-23-2012 |
| 20120043992 | IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER - An electronic integrated circuit includes a signal path connected between the functional logic ( | 02-23-2012 |
| 20120043619 | SYSTEM AND CIRCUIT FOR SIMULATING GATE-TO-DRAIN BREAKDOWN - A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET. | 02-23-2012 |
| 20120043612 | Device Layout in Integrated Circuits to Reduce Stress from Embedded Silicon-Germanium - An integrated circuit including one or more transistors in which source and drain regions are formed as embedded silicon-germanium (eSiGe). Guard ring structures in the integrated circuit are formed in single-crystal silicon, rather than in eSiGe. In one example, p-channel MOS transistors have source/drain regions formed in eSiGe, while the locations at which p-type guard rings are formed are masked from the recess etch and the eSiGe selective epitaxy. Defects caused by concentrated crystal strain at the corners of guard rings and similar structures are eliminated. | 02-23-2012 |
| 20120041993 | METHOD AND APPARATUS FOR CONFIGURING FUNCTIONALITY OF A CALCULATOR - A method and apparatus for configuring calculator functionalities available to an end user. The method includes selecting at least one of functionality to be enabled and disabled in the calculator to the end user, saving the selection in a content document, construction a new application based on the content document, and configuring the calculator according to the new application. | 02-16-2012 |
| 20120041699 | Antenna Matching Network Tuning Method - A matching network having a pi configuration between an antenna and another component in an RF circuit may be tuned by a process including computing the admittance of the antenna using measured reflection coefficients from three settings of the matching network, and identifying capacitance values for tuning the matching network. Capacitance values for an antenna side shunt and a circuit side shunt are found by computing target susceptance value for the shunts and comparing to a list of available susceptance values. The capacitance values corresponding to the available susceptances closest to the target susceptances are used to tune the antenna side shunt. | 02-16-2012 |
| 20120039474 | Display Authenticated Security Association - A system and method for establishing a mutual entity authentication and a shared secret between two devices using displayed values on each device. Unique first private keys and first public keys are assigned to both devices. The public keys are exchanged between the two devices. Both devices compute a shared secret from their own private keys and the received public keys. Both devices compute, exchange, and verify their key authentication codes of the shared secret. If verification is successful, both devices use the shared secret to generate a displayed value. One or more users compare the displayed values and provide an indication to the devices verifying whether the displays match. If the displays match, then the devices compute a shared master key, which is used either directly or via a later-generated session key for securing message communications between the two devices. | 02-16-2012 |
| 20120039329 | SYSTEM AND METHOD FOR USING PARTIALLY RECEIVED PACKETS IN COEXISTING NETWORKS - A system and method for using partially received packets in coexisting networks. In one embodiment, a wireless receiver includes an interference detector and a packet validator. The interference detector is configured to determine that time multiplexing of a coexisting wireless network interferes with reception of a packet by the wireless receiver. The packet validator is configured to identify a type of the packet and useable data values of the packet when a partial packet is received due to the time multiplexing. The packet validator is configured to identify the type and useable data values of the packet based on a packet signature stored in the wireless receiver. | 02-16-2012 |
| 20120039093 | SYSTEMS AND METHODS FOR OFF-TIME CONTROL IN A VOLTAGE CONVERTER - Various embodiments of the present invention provide voltage converters and methods for using such. As one example, a voltage converter is disclosed that includes a transformer with a first winding and a second winding. A voltage is applied to the first winding for a period that is followed by an OFF time. The voltage converter further includes an OFF time controller that is operable to adjust the OFF time based at least in part on a load current traversing the second winding. | 02-16-2012 |
| 20120036695 | LOW COST WINDOW PRODUCTION FOR HERMETICALLY SEALED OPTICAL PACKAGES - Disclosed embodiments demonstrate batch processing methods for producing optical windows for microdevices. The windows protect the active elements of the microdevice from contaminants, while allowing light to pass into and out of the hermetically sealed microdevice package. Windows may be batch produced, reducing the cost of production, by fusing multiple metal frames to a single sheet of glass. In order to allow windows to be welded atop packages, disclosed embodiments keep a lip of metal without any glass after the metal frames are fused to the sheet of glass. Several techniques may accomplish this goal, including grinding grooves in the glass to provide a gap that prevents fusion of the glass to the metal frames along the outside edges in order to form a lip. The disclosed batch processing techniques may allow for more efficient window production, taking advantage of the economy of scale. | 02-16-2012 |
| 20120036408 | Test Chain Testability In a System for Testing Tri-State Functionality - An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed. | 02-09-2012 |
| 20120036407 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 02-09-2012 |
| 20120036406 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 02-09-2012 |
| 20120035768 | CONTROLLING AN EPITAXIAL GROWTH PROCESS IN AN EPITAXIAL REACTOR - A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as a linear function of the actual output parameter value and a second set of thermocouple offset parameter values. The processor also determines a distance between a target output parameter value and the modeled output parameter value | 02-09-2012 |
| 20120033722 | Time-Domain Link Adaptation - Embodiments of the invention provide time-domain link adaptation in power line communications. In one embodiment, the cyclic prefix length and position is adjusted with an OFDM symbol to overlap a periodic impulse noise pulse, thereby allowing the data carried in the symbol to be detected at a receiver. The cyclic prefix may be adjusted to provide a pattern that yields an integer number of OFDM symbols in one zero crossing period. The data rate used for the symbols overlapping the zero-crossing period may be zero or very low. A high data rate may be used for symbols outside the zero-crossing period because those symbols will not be affected by the periodic impulse noise. | 02-09-2012 |
| 20120033676 | MGCP PACKAGE FOR BATTERY BACKUP CONTROL - In one embodiment, a gateway includes an interface, and a processor cooperatively operable with the interface to transmit and receive packet communications. The processor receives, over the interface, a request-notification for a backup battery status, which is formatted according to a media gateway control protocol (MGCP) package protocol. The processor transmits, over the interface, a notify of an observed event, the observed event indicating the backup battery status which is formatted according to the MGCP package protocol. In another embodiment, a call agent includes an interface and a processor. The call agent processor transmits a request-notification for a backup battery status, which is formatted according to a media gateway control protocol (MGCP) package protocol. The call agent processor also receives a notify of an observed event over the interface, the observed event indicating the backup battery status, which is formatted according to the MGCP package protocol. | 02-09-2012 |
| 20120033652 | System and Method for Simultaneous Infrastructure and Ad Hoc Networked Communications - A method and a system are disclosed for maintaining a simultaneous communication between a first wireless station and both an access point and a second wireless station. The first and second wireless stations are associated with the access point, or only one of the wireless stations, but not both, is associated with the access point. The first wireless station gains an instance of medium access by using applicable medium access protocols. Once the first wireless station gains an instance of medium access, it transmits frames to the access point on an infrastructure network and to the second wireless station on the same infrastructure network or an ad hoc network. The overall air time must not exceed the maximum air time allowed for the instance of medium access. All transmitted frames must have a user priority mapped to the access category for which the instance of medium access was obtained. | 02-09-2012 |
| 20120033491 | PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY USING AN ACTIVE TRANSITION CONTROL - An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided. | 02-09-2012 |
| 20120032748 | Systems and Methods of Ripple Reduction in a DC/DC Converter - Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current. | 02-09-2012 |
| 20120032715 | HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER - A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. | 02-09-2012 |
| 20120032701 | QUAD STATE LOGIC DESIGN METHODS, CIRCUITS, AND SYSTEMS - Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs. | 02-09-2012 |
| 20120032280 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 02-09-2012 |
| 20120032270 | DEPLETION MODE FIELD EFFECT TRANSISTOR FOR ESD PROTECTION - A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode | 02-09-2012 |
| 20120030532 | STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING - A scannable integrated circuit ( | 02-02-2012 |
| 20120030447 | PROCESS, CIRCUITS, DEVICES, AND SYSTEMS FOR ENCRYPTION AND DECRYPTION AND OTHER PURPOSES, AND PROCESSES OF MAKING - A wireless communications device ( | 02-02-2012 |
| 20120028431 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING A NITROGEN CONTAINING OXIDE LAYER - The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure ( | 02-02-2012 |
| 20120026808 | Integrated Circuit With Low Power SRAM - An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage. | 02-02-2012 |
| 20120026762 | Pre-Bias Control for Switched Mode Power Supplies - An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the pre-biased output. After the high side switch is activated, a low side switch is activated to draw a second current from the pre-biased output such that the magnitude of the first current is greater than the magnitude of the second current for at least a portion of a time period T | 02-02-2012 |
| 20120026754 | DOUBLE PHASE-SHIFTING FULL-BRIDGE DC-TO-DC CONVERTER - A DC-to-DC converter has a leading full-bridge inverter and a lagging full-bridge inverter for receiving a DC input and producing respective AC output voltages. A full-wave rectifier circuit rectifies the AC output voltages to produce a rectified output voltage, which is filtered by a current doubling output filter circuit to produce a DC output voltage. A master phase-shift controller and a slave phase-shift controller respectively provide first and second control signals to the leading full-bridge inverter and third and fourth control signals to the lagging full-bridge inverter to regulate the DC output voltage by changing a phase of the second and fourth control signals with respect to the first and third control signals below a predetermined DC output voltage, and by changing a phase of the third and fourth control signals with respect to the first and second control signals above the predetermined threshold. | 02-02-2012 |
| 20120026367 | SYSTEM AND METHOD FOR MAINTAINING MAXIMUM INPUT RATE WHILE UP-SCALING AN IMAGE VERTICALLY - An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the receiving module that stores the pixel data in response to a write control signal from control logic. The triple line buffer is operated as a circular buffer. The resizer further includes a resizer core that reads pixel data from the triple line buffer in response to a read control signal from the control logic. The pixel data is replicated to up-scale the image vertically according to a vertical up-scale ratio such that the resizer achieves a maximum input data rate and also eliminates an overflow condition in the resizer. The vertical up-scale ratio is a fraction. | 02-02-2012 |
| 20120026213 | ILLUMINATION SOURCE AND METHOD THEREFOR - An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element optically coupled to the light circuit to provide multiple colors of light. The light circuit propagates light using light guides. The use of light guides eliminates the use of free space optical elements, enabling the creation of more compact light sources. Furthermore, the use of light guides may enable the creation of light sources with fewer mechanical restrictions, thereby making the light sources potentially more reliable and less expensive. | 02-02-2012 |
| 20120026039 | SINGLE RF RECEIVER CHAIN ARCHITECTURE FOR GPS, GALILEO AND GLONASS NAVIGATION SYSTEMS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES - A wireless receiver for multiple frequency bands reception includes a single receive radio frequency (RF) circuit ( | 02-02-2012 |
| 20120025901 | SENSOR NODE VOLTAGE CLAMPING CIRCUIT AND METHOD - A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present. | 02-02-2012 |
| 20120023381 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 01-26-2012 |
| 20120023313 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 01-26-2012 |
| 20120020266 | POWER STATE AND MEDIUM ACCESS COORDINATION IN COEXISTING WIRELESS NETWORKS - Apparatus and method for improving throughput in a wireless device accessing coexisting networks. In one embodiment, a wireless device includes first and second wireless transceivers, a power state controller, and an access controller. The first wireless transceiver is configured to access a first wireless network. The second wireless transceiver is configured to access a second wireless network. The power state controller is configured to switch the first wireless transceiver between an active state and a sleep state. The power consumed by the first wireless transceiver while in the sleep state is reduced relative to the active state. The access controller is configured to alternately allocate a wireless medium to the first wireless transceiver and the second wireless transceiver. The power state controller and the medium access controller are configured to coordinate power state switching of the first wireless transceiver and wireless medium access by the second wireless transceiver. | 01-26-2012 |
