| TEXAS INSTRUMENTS INCORPORATED Patent applications |
| Patent application number | Title | Published |
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| 20120036408 | Test Chain Testability In a System for Testing Tri-State Functionality - An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed. | 02-09-2012 |
| 20120036407 | METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL - Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits. | 02-09-2012 |
| 20120036406 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 02-09-2012 |
| 20120035768 | CONTROLLING AN EPITAXIAL GROWTH PROCESS IN AN EPITAXIAL REACTOR - A system for controlling an epitaxial growth process in an epitaxial reactor. The system includes a processor for setting up a modeled output parameter value as a linear function of the actual output parameter value and a second set of thermocouple offset parameter values. The processor also determines a distance between a target output parameter value and the modeled output parameter value | 02-09-2012 |
| 20120033722 | Time-Domain Link Adaptation - Embodiments of the invention provide time-domain link adaptation in power line communications. In one embodiment, the cyclic prefix length and position is adjusted with an OFDM symbol to overlap a periodic impulse noise pulse, thereby allowing the data carried in the symbol to be detected at a receiver. The cyclic prefix may be adjusted to provide a pattern that yields an integer number of OFDM symbols in one zero crossing period. The data rate used for the symbols overlapping the zero-crossing period may be zero or very low. A high data rate may be used for symbols outside the zero-crossing period because those symbols will not be affected by the periodic impulse noise. | 02-09-2012 |
| 20120033676 | MGCP PACKAGE FOR BATTERY BACKUP CONTROL - In one embodiment, a gateway includes an interface, and a processor cooperatively operable with the interface to transmit and receive packet communications. The processor receives, over the interface, a request-notification for a backup battery status, which is formatted according to a media gateway control protocol (MGCP) package protocol. The processor transmits, over the interface, a notify of an observed event, the observed event indicating the backup battery status which is formatted according to the MGCP package protocol. In another embodiment, a call agent includes an interface and a processor. The call agent processor transmits a request-notification for a backup battery status, which is formatted according to a media gateway control protocol (MGCP) package protocol. The call agent processor also receives a notify of an observed event over the interface, the observed event indicating the backup battery status, which is formatted according to the MGCP package protocol. | 02-09-2012 |
| 20120033652 | System and Method for Simultaneous Infrastructure and Ad Hoc Networked Communications - A method and a system are disclosed for maintaining a simultaneous communication between a first wireless station and both an access point and a second wireless station. The first and second wireless stations are associated with the access point, or only one of the wireless stations, but not both, is associated with the access point. The first wireless station gains an instance of medium access by using applicable medium access protocols. Once the first wireless station gains an instance of medium access, it transmits frames to the access point on an infrastructure network and to the second wireless station on the same infrastructure network or an ad hoc network. The overall air time must not exceed the maximum air time allowed for the instance of medium access. All transmitted frames must have a user priority mapped to the access category for which the instance of medium access was obtained. | 02-09-2012 |
| 20120033491 | PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY USING AN ACTIVE TRANSITION CONTROL - An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided. | 02-09-2012 |
| 20120032748 | Systems and Methods of Ripple Reduction in a DC/DC Converter - Systems and devices for ripple reduction in a DC/DC converter are presented. The disclosed systems and methods enable ripple reduction in discontinuous conduction mode (DCM) operation. In DCM, the inductor current peak to peak ripple may be reduced based on the load current. To achieve the reduction of the inductor peak to peak current ripple, a digital counter is used to count the time between consecutive PWM pulses. The digital output of the counter is used to control the pulse width modulation. As the digital output of the counter increases, the PWM on-time decreases. Since the PWM pulse is demanded by the load in DCM mode, the peak to peak inductor ripple is modulated by the counter, or, in turn, modulated by the load current. | 02-09-2012 |
| 20120032715 | HIGH-SPEED FREQUENCY DIVIDER AND A PHASE LOCKED LOOP THAT USES THE HIGH-SPEED FREQUENCY DIVIDER - A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise. | 02-09-2012 |
| 20120032701 | QUAD STATE LOGIC DESIGN METHODS, CIRCUITS, AND SYSTEMS - Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs. | 02-09-2012 |
| 20120032280 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 02-09-2012 |
| 20120032270 | DEPLETION MODE FIELD EFFECT TRANSISTOR FOR ESD PROTECTION - A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode | 02-09-2012 |
| 20120030532 | STRUCTURES AND CONTROL PROCESSES FOR EFFICIENT GENERATION OF DIFFERENT TEST CLOCKING SEQUENCES, CONTROLS AND OTHER TEST SIGNALS IN SCAN DESIGNS WITH MULTIPLE PARTITIONS, AND DEVICES, SYSTEMS AND PROCESSES OF MAKING - A scannable integrated circuit ( | 02-02-2012 |
| 20120030447 | PROCESS, CIRCUITS, DEVICES, AND SYSTEMS FOR ENCRYPTION AND DECRYPTION AND OTHER PURPOSES, AND PROCESSES OF MAKING - A wireless communications device ( | 02-02-2012 |
| 20120028431 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING A NITROGEN CONTAINING OXIDE LAYER - The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure ( | 02-02-2012 |
| 20120026808 | Integrated Circuit With Low Power SRAM - An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage. | 02-02-2012 |
| 20120026762 | Pre-Bias Control for Switched Mode Power Supplies - An embodiment of the invention provides a method of reducing a drop in voltage on a pre-biased output of a DC-DC step-down switching converter. A high side switch is activated to conduct a first current to the pre-biased output. After the high side switch is activated, a low side switch is activated to draw a second current from the pre-biased output such that the magnitude of the first current is greater than the magnitude of the second current for at least a portion of a time period T | 02-02-2012 |
| 20120026754 | DOUBLE PHASE-SHIFTING FULL-BRIDGE DC-TO-DC CONVERTER - A DC-to-DC converter has a leading full-bridge inverter and a lagging full-bridge inverter for receiving a DC input and producing respective AC output voltages. A full-wave rectifier circuit rectifies the AC output voltages to produce a rectified output voltage, which is filtered by a current doubling output filter circuit to produce a DC output voltage. A master phase-shift controller and a slave phase-shift controller respectively provide first and second control signals to the leading full-bridge inverter and third and fourth control signals to the lagging full-bridge inverter to regulate the DC output voltage by changing a phase of the second and fourth control signals with respect to the first and third control signals below a predetermined DC output voltage, and by changing a phase of the third and fourth control signals with respect to the first and second control signals above the predetermined threshold. | 02-02-2012 |
| 20120026367 | SYSTEM AND METHOD FOR MAINTAINING MAXIMUM INPUT RATE WHILE UP-SCALING AN IMAGE VERTICALLY - An example embodiment provides a resizer in an image processing system. The resizer includes a receiving module that receives pixel data representative of an image. A triple line buffer is coupled to the receiving module that stores the pixel data in response to a write control signal from control logic. The triple line buffer is operated as a circular buffer. The resizer further includes a resizer core that reads pixel data from the triple line buffer in response to a read control signal from the control logic. The pixel data is replicated to up-scale the image vertically according to a vertical up-scale ratio such that the resizer achieves a maximum input data rate and also eliminates an overflow condition in the resizer. The vertical up-scale ratio is a fraction. | 02-02-2012 |
| 20120026213 | ILLUMINATION SOURCE AND METHOD THEREFOR - An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element optically coupled to the light circuit to provide multiple colors of light. The light circuit propagates light using light guides. The use of light guides eliminates the use of free space optical elements, enabling the creation of more compact light sources. Furthermore, the use of light guides may enable the creation of light sources with fewer mechanical restrictions, thereby making the light sources potentially more reliable and less expensive. | 02-02-2012 |
| 20120026039 | SINGLE RF RECEIVER CHAIN ARCHITECTURE FOR GPS, GALILEO AND GLONASS NAVIGATION SYSTEMS, AND OTHER CIRCUITS, SYSTEMS AND PROCESSES - A wireless receiver for multiple frequency bands reception includes a single receive radio frequency (RF) circuit ( | 02-02-2012 |
| 20120025901 | SENSOR NODE VOLTAGE CLAMPING CIRCUIT AND METHOD - A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present. | 02-02-2012 |
| 20120023381 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 01-26-2012 |
| 20120023313 | PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE - An electronic circuit ( | 01-26-2012 |
| 20120020266 | POWER STATE AND MEDIUM ACCESS COORDINATION IN COEXISTING WIRELESS NETWORKS - Apparatus and method for improving throughput in a wireless device accessing coexisting networks. In one embodiment, a wireless device includes first and second wireless transceivers, a power state controller, and an access controller. The first wireless transceiver is configured to access a first wireless network. The second wireless transceiver is configured to access a second wireless network. The power state controller is configured to switch the first wireless transceiver between an active state and a sleep state. The power consumed by the first wireless transceiver while in the sleep state is reduced relative to the active state. The access controller is configured to alternately allocate a wireless medium to the first wireless transceiver and the second wireless transceiver. The power state controller and the medium access controller are configured to coordinate power state switching of the first wireless transceiver and wireless medium access by the second wireless transceiver. | 01-26-2012 |
| 20120019947 | TECHNIQUE FOR PROGRAMMABLE RISE TIME IN HARD DISK DRIVE WRITER - A write channel for a hard disk drive has a write current with a programmably adjustable rise time, and includes first and second analog write data signal paths having respective resistive nodes. First and second programmable capacitors are connected to the resistive nodes, whereby changes in capacitance of the first and second capacitors changes the rise time of the write current. A programmer selectively programs the first and second programmable capacitors. The rise time programmed is selected to provide a decreased bit error rate of an on-track write process and reduced adjacent-track interference. | 01-26-2012 |
| 20120019918 | SYSTEM AND METHOD FOR REDUCING VISIBLE SPECKLE IN A PROJECTION VISUAL DISPLAY SYSTEM - The disclosure provides an apparatus for reducing speckle in a projection visual display (PVD) system, a method of reducing visible speckle in a PVD system and a PVD system incorporating the method or apparatus. In one embodiment, the apparatus includes a diffuser interposable in an optical path of a PVD system and a diffuser actuator having a single drive axis configured to cause the diffuser to travel in a Lissajous curve at least partially transverse to the optical path. | 01-26-2012 |
| 20120019324 | Amplifier With Improved Input Resistance and Controlled Common Mode - An amplifier includes a first pair of transistors (the first pair) that defines a first output, each transistor of the first pair having a gate coupled to a first input terminal; a second pair of transistors (the second pair) that defines a second output, each transistor of the second pair having a gate coupled to a second input terminal; a first capacitor coupled to the second output terminal and to the gate of a first transistor of the first pair; a second capacitor coupled to the second output terminal and to the gate of a second transistor of the first pair; a third capacitor coupled to the first output terminal and to the gate of a third transistor of the second pair; and a fourth capacitor coupled to the first output terminal and to the gate of a fourth transistor of the second pair. | 01-26-2012 |
| 20120019280 | INTEGRATED CIRCUIT HAVING ELECTRICALLY ISOLATABLE TEST CIRCUITRY - Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power. | 01-26-2012 |
| 20120019263 | Precision Measurement of Capacitor Mismatch - Circuitry and methods for measuring capacitive mismatch with improved precision. The capacitors under measurement are connected in series in a voltage divider, with the node common to both capacitors connected to the gate of a source follower transistor. In one disclosed embodiment of the invention, a ramped voltage is applied to the drain of the source follower transistor simultaneously with the ramped voltage applied to the voltage divider; the slope of the ramped drain voltage is at the nominal slope of the voltage at the common node of the voltage divider. In another embodiment, a second transistor in saturation has its gate coupled to the source of the source follower device, and its source connected to the drain of the source follower device in series with a constant voltage drop. The drain-to-source voltage of the source follower device is thus held constant in each embodiment, improving precision of the measurement. | 01-26-2012 |
| 20120018810 | Structure And Method For Dual Work Function Metal Gate CMOS With Selective Capping - A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming. | 01-26-2012 |
| 20120017129 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 01-19-2012 |
| 20120017067 | ON-DEMAND PREDICATE REGISTERS - In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP. | 01-19-2012 |
| 20120015483 | Semiconductor Device Package and Method of Assembly Thereof - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 01-19-2012 |
| 20120015479 | Semiconductor Package with a Mold Material Encapsulating a Chip and a Portion of a Lead Frame - Various exemplary embodiments provide components, devices, and methods of semiconductor packaging. The disclosed packaging component can include a mold material disposed around a lead frame and at least an integrated circuit (IC), wherein the IC is electrically connected with one side of the lead frame. The opposite side of the lead frame including, for example, lead segments, can be exposed from the mold material. A variety of other components, devices, and packages can then be assembled, e.g., over the disclosed packaging component, through the exposed regions so as to improve packaging densities. | 01-19-2012 |
| 20120015478 | Integrated Circuit Stacked Package Precursors and Stacked Packaged Devices and Systems Therefrom - A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads. | 01-19-2012 |
| 20120014454 | Method and Apparatus for Parallel Context Processing - A method and apparatus for parallel context processing for example for high coding efficient entropy coding in HEVC. The method comprising retrieving syntax element relating to a block of an image, grouping at least two bins belonging to similar context based on the syntax element, and coding the grouped bins in parallel. | 01-19-2012 |
| 20120014243 | Allocation and Logical to Physical Mapping of Scheduling Request Indicator Channel in Wireless Networks - A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the cell. The NodeB transmits a specific SRI subframe offset and an index value to the particular UE within the cell. The specific SRI subframe offset and the index value enable the UE to determine a unique combination of cyclic shift, RS orthogonal cover, data orthogonal cover, and resource block number for the UE to use as a unique physical resource for an SRI in the physical uplink control channel (PUCCH). | 01-19-2012 |
| 20120014194 | Memory Cell with Equalization Write Assist in Solid-State Memory - A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors in series, or as a double-gate transistor. The equalization gate is controlled by a word line indicating selection of the row containing the cell in combination with a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to a selected cell, both gates are turned on, connecting the storage nodes of the cell to one another and assisting the write of the opposite date state from that previously stored. | 01-19-2012 |
| 20120014173 | Disturb-Free Static Random Access Memory Cell - A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column. | 01-19-2012 |
| 20120013390 | DISPLAYPORT SWITCH - In versions 1.1a and 1.2 of the DISPLAYPORT™ standard, capacitors are used between a sourcing circuit and a switch for the auxiliary channel. As a result, these capacitors are generally uncharged when the switch activates the auxiliary channel, which can result in errors. Here, a switch is employed that uses precharge circuits to precharge these capacitors. Thus, errors due to charging of these capacitors can be reduced. | 01-19-2012 |
| 20120013003 | BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP - A semiconductor flip-chip ball grid array package with one-metal-layered substrate. The sites of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area, when the sites can be routed for metal plating. The space to place a maximum number of signal routing traces is opened up by interrupting the periodicity of the site array from the edge of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array. | 01-19-2012 |
| 20120012982 | CAPACITORS AND METHODS OF FORMING - Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate. A top contact may be formed laterally spaced from the trenched area by patterning laterally extended portions of one or more of the dielectric, polysilicon and top metal contact layers. | 01-19-2012 |
| 20120012941 | FORMATION OF METAL GATE ELECTRODE USING RARE EARTH ALLOY INCORPORATED INTO MID GAP METAL - Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors. | 01-19-2012 |
| 20120011478 | MERGING SUB-RESOLUTION ASSIST FEATURES OF A PHOTOLITHOGRAPHIC MASK - Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique. | 01-12-2012 |
| 20120011412 | ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP. | 01-12-2012 |
| 20120011410 | SCAN TEST METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test. | 01-12-2012 |
| 20120011404 | METHOD AND SYSTEM OF A PROCESSOR-AGNOSTIC ENCODED DEBUG-ARCHITECTURE IN A PIPELINED ENVIRONMENT - A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system. | 01-12-2012 |
| 20120011351 | Security Processing Engines, Circuits and Systems and Adaptive Processes and Other Processes - An electronic circuit ( | 01-12-2012 |
| 20120011294 | SYSTEM AND METHOD FOR SECURE AUTHENTICATION OF A "SMART" BATTERY BY A HOST - Systems and methods for providing a battery module | 01-12-2012 |
| 20120009739 | Metallic Leadframes Having Laser-Treated Surfaces for Improved Adhesion to Polymeric Compounds - A leadframe for the assembly of a semiconductor chip has regions ( | 01-12-2012 |
| 20120008768 | MODE CONTROL ENGINE (MCE) FOR CONFIDENTIALITY AND OTHER MODES, CIRCUITS AND PROCESSES - An electronic data processing module ( | 01-12-2012 |
| 20120008718 | Wireless Precoding Methods - Various wireless precoding systems and methods are presented. In some embodiments, a wireless transmitter comprises an antenna precoding block, a transform block, and multiple transmit antennas. The antenna precoding block receives frequency coefficients from multiple data streams and distributes the frequency coefficients across multiple transmit signals in accordance with frequency-dependent matrices. The transform block transforms the precoded frequency coefficients into multiple time domain transmit signals to be transmitted by the multiple antennas. The frequency coefficients from multiple data streams may be partitioned into tone groups, and all the frequency coefficients from a given tone group may be redistributed in accordance with a single matrix for that tone group. In some implementations, the frequency coefficients within a tone group for a given data stream may also be precoded. In some alternative embodiments, tone group precoding may be employed in a single channel system. | 01-12-2012 |
| 20120008710 | Mapping Schemes for Secondary Synchronization Signal Scrambling - Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal. The transmitter further includes a transmit unit configured to transmit the primary synchronization signal and the scrambled secondary synchronization signal. | 01-12-2012 |
| 20120008691 | METHOD AND APPARATUS FOR REGION-BASED WEIGHTED PREDICTION WITH IMPROVED GLOBAL BRIGHTNESS DETECTION - A method and apparatus for determining a region-based weighted prediction with improved global brightness detection. The method includes applying a global brightness change detection methods by computing the weighted prediction parameters, determining if the brightness change is different amount of change for the different regions, if the change is not different, calculate motion estimation and setting Refidx to 1 and setting Refidx is set to 0 when there is change, determining the best motion vector, motion vector cost and the best reference input, and determining a region-based weighted prediction with improved global brightness detection based on the motion vector data. | 01-12-2012 |
| 20120008645 | SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR RATE AND/OR DIVERSITY ADAPTATION FOR PACKET COMMUNICATIONS - A media over packet networking appliance provides a network interface, a voice transducer, and at least one integrated circuit assembly coupling the voice transducer to the network interface. The at least one integrated circuit assembly provides media over packet transmissions and holds bits defining reconstruction of a packet stream having a primary stage and a secondary stage. The secondary stage has one or more of linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains. The packet stream has an instance of single packet loss, and the reconstruction includes receiving a packet sequence represented by P(n)P(n−1)′, [Lost Packet], P(n+2)P(n+1)′, and P(n+3)P(n+2)′, obtaining as information from the secondary stage one or more of the linear predictive coding parameters, long term prediction lags, parity check, and adaptive and fixed codebook gains, and performing an excitation reconstruction utilizing said packet sequence thus received. | 01-12-2012 |
| 20120008187 | System and Method for Operating Light Processing Electronic Devices - A system and method for operating an electronic device used in light processing. A method comprises altering a spatial relationship between a spatial light modulator (SLM) and a light incident on the SLM, shifting light modulator states of a first portion of light modulators to a second portion of light modulators, and placing a third portion of light modulators in the SLM into a performance degradation-reducing mode. The amount of shifting performed is proportional to the amount of change in the spatial relationship. The method allows for a change in light modulators used to modulate the light, thereby preventing the overuse of some of the light modulators, which may help to prevent degradation of the light modulators. The performance degradation reducing mode may help to further reduce or even reverse the performance degradation of the light modulators. | 01-12-2012 |
| 20120008102 | On-Axis Projection Lens with Offset - A method and system of projecting images with high degrees of image offset while limiting the physical offset of the projection lens elements. The methods and systems provided limit the displacement of the optical elements relative to the optical axis of the display panel and enable a very thin, efficient projector. | 01-12-2012 |
| 20120007992 | Method and Apparatus for Sub-Picture Based Raster Scanning Coding Order - A method and apparatus for sub-picture based raster scanning coding order. The method includes dividing an image into even sub-pictures, and encoding parallel sub-pictures on multi-cores in raster scanning order within sub-pictures, wherein from core to core, coding of the sub-picture is independent around sub-picture boundaries, and wherein within a core, coding of a sub-picture is at least one of dependent or independent around sub-picture boundaries. | 01-12-2012 |
| 20120007954 | METHOD AND APPARATUS FOR A DISPARITY-BASED IMPROVEMENT OF STEREO CAMERA CALIBRATION - A method and apparatus for camera calibration. The method is for disparity estimation of the camera calibration and includes collecting statistical information from at least one disparity image, inferring sub-pixel misalignment between a left view and a right view of the camera, and utilizing the collected statistical information and the inferred sub-pixel misalignment for calibration refinement. | 01-12-2012 |
| 20120007687 | Digital Amplitude Modulation - A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal. | 01-12-2012 |
| 20120007622 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 01-12-2012 |
| 20120005546 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 01-05-2012 |
| 20120005400 | Dual In Line Memory Module with Multiple Memory Interfaces - A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors. | 01-05-2012 |
| 20120002729 | METHOD AND APPARATUS FOR LOW COST COEFFICIENT-SUPPRESSION FOR VIDEO COMPRESSION - A method for video compression and a video encoder. The method for video compression includes finding a coefficient relating to inter-coded block with a biggest absolute value, determining the number of non-zero coefficients when the absolute value is less that 2, determining the number of non-zero coefficients is less than a threshold, and setting the coefficients to zero when the non-zero coefficients is less than the threshold. | 01-05-2012 |
| 20120002714 | Communication on a Pilot Wire - Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). The EVSE and EV exchange a Pulse Width Modulation (PWM) signal on the pilot wire to control charging operations of the EV. Data communications may also be transmitted on the pilot wire, such as between transmit and receive modems. The modems transmit communication signals either continuously, without regard to the state of the PWM signal, or only when the PWM is in an off-state. If transmitting while PWM is on, the modem needs a large coupling impedance and/or a large signal injection. To transmit only when the PWM is off, the modem may use a blocking diode in the coupling circuit or may synchronize to the pulses in the PWM signal. | 01-05-2012 |
| 20120002471 | Memory Bit Redundant Vias - An integrated circuit containing a memory array with memory bits and a differential sense amplifier for reading the logic state of the memory bits. The integrated circuit also contains redundant vias which are in the via path that couples a bitline to Vss. Moreover, an integrated circuit containing a FLASH memory bit with redundant vias in the via path from the bitline to Vss. | 01-05-2012 |
| 20120001336 | CORROSION-RESISTANT COPPER-TO-ALUMINUM BONDS - A connection formed by a copper wire ( | 01-05-2012 |
| 20110320897 | CORE CIRCUIT TEST ARCHITECTURE - A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate. | 12-29-2011 |
| 20110320850 | OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence. | 12-29-2011 |
| 20110318901 | SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION - A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure. | 12-29-2011 |
| 20110317779 | SCRAMBLING SEQUENCES FOR WIRELESS NETWORKS - An integrated circuit includes logic configured to generate scrambling sequences, each based on a different scrambling seed, for a smart-utility-network data packet communication. A Hamming distance between any two scrambling sequences is half the length of a PSDU of the data packet or greater. | 12-29-2011 |
| 20110317762 | VIDEO ENCODER AND PACKETIZER WITH IMPROVED BANDWIDTH UTILIZATION - Techniques for managing a video encoding pipeline are disclosed herein. In one embodiment, a video encoder includes a multi-stage encoding pipeline. The pipeline includes an entropy coding engine and a transform engine. The entropy encoding engine is configured to, in a first pipeline cycle, entropy encode a transformed first macroblock and determine that a predetermined slice size will be exceeded by adding the entropy encoded macroblock to a slice. The transform engine is configured to provide a transformed macroblock to the entropy coding engine. The transform engine is also configured to determine, in a third pipeline cycle, coding and prediction mode to apply to the first macroblock, based on the entropy coding engine determining, in the first pipeline cycle, that the predetermined slice size will be exceeded by adding the encoded macroblock to a slice. | 12-29-2011 |
| 20110317719 | DATA LINK LAYER HEADERS - A system for communicating protocol layer processing information is disclosed herein. A transmitter includes a protocol layer header generator that generators a header for a first protocol data unit. The header generator provides a first header comprising a first sequence number field that determines the order in which a receiving entity present the first data unit to higher protocol layer. The sequence number field varies in length. A receiver includes a protocol layer header parser that parses a header of a first protocol data unit. The header parser parses a first header comprising a first sequence number field that determines the order in which the first data unit is presented to a higher protocol layer. The sequence number field varies in length. | 12-29-2011 |
| 20110317702 | Two-Hop Star Network Topology Extension - Relayed nodes communicate with a target hub using a relaying node in a two-hop star network. The relayed nodes transmit a first encapsulating frame having a payload that comprises an encapsulated frame. The first encapsulating frame is formatted as a one-hop communication between the relayed node and the relaying node. The encapsulated frame is formatted as a one-hop communicate between the relayed node and the target hub. The relaying node generates a second encapsulating frame having a payload that comprises the encapsulated frame from the relayed node. The second encapsulating frame is formatted as a one-hop communication from between the relaying node and the target hub. The target hub sends frames to the relayed node in a similar manner through the relaying node. The target hub and relaying node communicate during scheduled uplink, downlink, or bilink allocations, and the relaying node and the relayed node communicate during scheduled bilink allocations. | 12-29-2011 |
| 20110317476 | Bit-by-Bit Write Assist for Solid-State Memory - A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, that is connected in series with a pair of power switch transistors between a power supply node and ground. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter that assists its change of state in a write operation. In other embodiments, a single power switch transistor gated by either a word line or a column select signal may be used. | 12-29-2011 |
| 20110316740 | Reacquiring Satellite Signals Quickly - Embodiments of the invention provide a method of reacquiring satellite signals quickly. A pseudorange of at least one satellite is estimated. A user's position is also estimated. Then a signal from at one or more satellites may be received. By detecting when the user is stationary, the Doppler frequency estimation can be corrected or the SNR can be boosted more both of which lead to improved performance. The embodiments allow a GNSS receiver to process signals in when the signal level would otherwise be too low—for example indoors. The embodiments can improve performance when one or more satellites are temporarily blocked but one or more satellites are still being tracked. | 12-29-2011 |
| 20110316738 | Adjusting a Bandwidth of GNSS Receivers - Embodiments of the invention provide a method of adjusting a bandwidth of receivers. A plurality of outputs from a correlator engine are combined. User dynamics are sensed. Bandwidth of one or more receivers are adjusted. By detecting when the user is stationary, the Doppler frequency estimation can be corrected or the SNR can be boosted more both of which lead to improved performance. The embodiments allow a receiver to process signals in when the signal level would otherwise be too low—for example indoors. The embodiments can improve performance when one or more satellites are temporarily blocked but one or more satellites are still being tracked. | 12-29-2011 |
| 20110316505 | Output Buffer With Improved Output Signal Quality - An output buffer receives an input signal and generates an output signal at an output node. The output buffer contains a driver circuit. The driver circuit includes two pairs of cascoded transistors connected at a junction node. Each of the cascoded pairs receives a corresponding level-shifted signal representing the input signal, and generates corresponding driver signals on driver nodes which are coupled to the output node. The driver circuit includes a capacitor connected between one of the driver nodes and the junction node. The capacitor enables the corresponding driver signal to be generated to reach a desired voltage quickly. The output impedance of the output buffer with which the output signal is launched is reduced and more closely matched the impedance of the path on which the output signal is provided. Signal quality of the output signal is thereby improved. | 12-29-2011 |
| 20110316089 | SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION - A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure. | 12-29-2011 |
| 20110314348 | SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS - Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation. | 12-22-2011 |
| 20110314321 | HIGH SPEED DIGITAL BIT STREAM AUTOMATIC RATE SENSE DETECTION - As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are support, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits present used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust. | 12-22-2011 |
| 20110314301 | SYSTEMS AND METHODS FOR HARDWARE KEY ENCRYPTION - Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide systems for encrypting/decrypting data. Such systems include a hardware key, a memory, a hardware decoder and a message encoder. The memory includes an encoded encoding key that represents an original encoding key. The hardware decoder receives a portion of the encoded encoding key and decodes the portion of the encoded encoding key using the hardware key to recover a portion of the original encoding key. The message encoder receives a data set and the portion of the original encoding key and encodes the data set using the portion of the original encoding key to create an encoded data set. | 12-22-2011 |
| 20110312168 | FORMATION OF SHALLOW JUNCTIONS BY DIFFUSION FROM A DIELECTRIC DOPED BY CLUSTER OR MOLECULAR ION BEAMS - A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10 | 12-22-2011 |
| 20110312144 | NOVEL METHOD TO ENHANCE CHANNEL STRESS IN CMOS PROCESSES - The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current. | 12-22-2011 |
| 20110311153 | REDUCED CALCULATIONS IN DETERMINING INTRA-PREDICTION TYPE METHOD AND SYSTEM - The method, system, and apparatus of source statistics based intra prediction type is disclosed. In one embodiment, a method includes classifying a four-pixel square block in an edge class (e.g., may include a DC edge class, a vertical edge class, a horizontal edge class, a diagonal edge class, and/or a planar edge class) based on an edge classifier, classifying an eight-pixel square block having the four-pixel square block and other four-pixel square blocks as a homogenous class if the four-pixel square block and the other four-pixel square blocks of the eight-pixel square block belong to the edge class, assigning a direction to the edge class of the eight-pixel square block, and determining an optimal intra-prediction type through the classification such that empirical testing of all possible ones of the edge class and the direction is avoided when the homogenous class is identified. | 12-22-2011 |
| 20110310999 | Dynamic Optimization of Overlap-and-Add Length - A method of performing overlap-and-add length for zero-padded suffixes. The method includes derotating received information symbol samples. The derotated received information symbol samples include a first set of derotated received information symbol samples and a second set of derotated received information symbol samples. The first set of derotated received information symbol samples are stored in a buffer. The second set of derotated received information symbol samples are provided to a received sample processing unit. The received zero-padded suffix samples are deroted. Based upon an overlap-and-add length, at least a fraction of the derotated received zero-padded suffix samples is added with at least a fraction of the first set of derotated received information symbol samples to produce multiple summed samples. The multiple summed samples is provided to the received sample processing unit. | 12-22-2011 |
| 20110310966 | SYNTAX ELEMENT DECODING - Techniques for efficient syntax element decoding in a system employing context-based adaptive binary arithmetic decoding are disclosed herein. In some embodiments, a video decoding system includes a context-based adaptive binary arithmetic code (“CABAC”) decoder. The decoder includes a processor and decode logic executed by the processor. The decode logic is configured to decompress a CABAC encoded syntax element. The decode logic includes a table embodying a set of rules that determine whether syntax element decoding is complete based on table addressing derived from a decoded syntax element binary value. | 12-22-2011 |
| 20110310869 | ENHANCING PACKET AGGREGATION PERFORMANCE IN COEXISTING WIRELESS NETWORKS - A method of communications for a coexisting wireless network including a wireless combination (combo) device communicating via a first wireless network and second wireless network, and a first wireless device on the first network. During an activity interval for the second network (i) a transmit (Tx) time interval is longer in duration than a Tx packet duration and/or (ii) a receive (Rx) time interval is longer in duration than a Rx packet duration to provide remaining time. A frame aggregated packet is used on the first network that includes a plurality of data packets and a dummy packet or spoofing so that the frame aggregated packet is extended in time or indicates an extension sufficient to overlap the Tx time interval or Rx time interval. The combo device transmits or receives an acknowledgement (ACK) on the first network during the activity interval for the second wireless network. | 12-22-2011 |
| 20110310859 | BASIC SERVICE SET SCHEDULING BASED ON MEDIA ACCESS CONTROLLER STATES - Apparatus and methods for controlling a wireless device concurrently operating in more than one basic service set (BSS). In one embodiment, a wireless device includes a first medium access controller (MAC), a second MAC, and a BSS scheduler. The first MAC is configured to communicate in a first BSS via a first wireless network. The second MAC is configured to communicate in a second BSS via a second wireless network. The BSS scheduler is configured to time multiplex medium access by the first and second MACs. Each of the first and second MACs is configured to provide a response to the BSS scheduler and to relinquish medium access when a request to relinquish medium access is received by the MAC, the timing of the response and relinquishment based on an activity state of the MAC when the request is received. | 12-22-2011 |
| 20110310826 | INTENTIONAL IDLE GAPS IN COEXISTING WIRELESS NETWORKS - A wireless combination device includes a first wireless transceiver configured for communication via a first wireless network over a first band, and a second wireless transceiver configured for communication via a second wireless network over a second band that overlaps the second band. The combination device includes a medium allocation scheduler coupled to the first wireless transceiver and second wireless transceiver for implementing spaced-mode operation that intentionally inserts idle gaps in transmissions via the second wireless network when triggered by the presence of at least one spaced-mode triggering condition. The idle gaps allow wireless transmissions via the first wireless network to be received by the combination device with higher probability, and without the need for clear to send (C2S) protection. | 12-22-2011 |
| 20110309523 | POP PRECURSOR WITH INTERPOSER FOR TOP PACKAGE BOND PAD PITCH COMPENSATION - An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer substrate has bottom metal land pads and top metal land pads, interposer vias, and an open receptacle region formed through the interposer substrate. The substrate top surface is positioned relative to the interposer so that the molded IC die is within the open receptacle region to align the bottom metal land pads and substrate contact pads. An underfill layer is between the substrate top surface and the bottom side of the interposer substrate. A step height from the mold cap height minus a height of the top metal land pads is generally from 0 to 0.2 mm. | 12-22-2011 |
| 20110309440 | HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN - An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations. | 12-22-2011 |
| 20110307750 | COMPRESSED SCAN CHAIN DIAGNOSIS BY INTERNAL CHAIN OBSERVATION, PROCESSES, CIRCUITS, DEVICES AND SYSTEMS - Electronic scan circuitry includes a decompressor ( | 12-15-2011 |
| 20110306207 | METHOD OF FABRICATING METAL-BEARING INTEGRATED CIRCUIT STRUCTURES HAVING LOW DEFECT DENSITY - A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater. | 12-15-2011 |
| 20110306176 | ALIGNMENT MARK FOR OPAQUE LAYER - An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process. | 12-15-2011 |
| 20110306172 | LATERAL TRENCH MOSFET HAVING A FIELD PLATE - One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed. | 12-15-2011 |
| 20110306170 | Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process - A method for forming an embedded SiGe (eSiGe) PMOS transistor ( | 12-15-2011 |
| 20110305044 | SWEEPING FREQUENCY LLC RESONANT POWER REGULATOR - An LLC resonant power regulator system ( | 12-15-2011 |
| 20110304994 | CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING - An integrated circuit structure includes a first conductive layer (MET | 12-15-2011 |
| 20110304596 | METHOD AND APPARATUS FOR INCREASING A PERCEIVED RESOLUTION OF A DISPLAY - According to one embodiment, a method of increasing a perceived resolution of a display includes directing light at a optical dithering element and repeatedly transitioning the optical dithering element from a first position to a second position and then back to the first position such that the mirror alternately reflects light to a first position on the display and then to a second position on the display. Each transition of the mirror includes controlling any overshoot or ringing in the position of the optical dithering element by providing a predetermined drive signal to the optical dithering element to smoothly accelerate and decelerate the element during the traverse between the first and second positions. | 12-15-2011 |
| 20110304493 | TERNARY SEARCH SAR ADC - Traditionally, successive approximation register (SAR) analog-to-digital converters (ADCs) using binary search algorithms have consumed power by performing unnecessary switching of a capacitive digital-to-analog converter (CDAC) when a CDAC voltage is relatively close to a sampling analog input signal. Here, a SAR ADC is provided that reduces the number of switching events. To accomplish this, a multi-stage comparator is provided that generates multiple output signals for SAR logic. Based on these outputs, the SAR logic can more efficiently switch its CDAC using a ternary search algorithm to reduce power consumption and improve efficiency. | 12-15-2011 |
| 20110304492 | MULTI-CHANNEL SAR ADC - For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors. | 12-15-2011 |
| 20110304490 | LOW POWER COMPARATOR FOR USE IN SAR ADCS - Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved. | 12-15-2011 |
| 20110304373 | LOW VOLTAGE HIGH-SPEED WAVE SHAPING CIRCUITRY - Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others. | 12-15-2011 |
| 20110304349 | LATERAL COUPLING ENABLED TOPSIDE ONLY DUAL-SIDE TESTING OF TSV DIE ATTACHED TO PACKAGE SUBSTRATE - A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections. | 12-15-2011 |
| 20110303976 | HIGH VOLTAGE CHANNEL DIODE - A channel diode structure having a drift region and method of forming. A charge balanced channel diode structure having an electrode shield and method of forming. | 12-15-2011 |
| 20110303959 | Ultraviolet Energy Shield for Non-Volatile Charge Storage Memory - An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another. | 12-15-2011 |
| 20110301947 | SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR RATE AND/OR DIVERSITY ADAPTATION FOR PACKET COMMUNICATIONS - Packets of real-time information are sent with a source rate greater than zero kilobits per second, and a time or path or combined time/path diversity rate initially being zero kilobits per second. This results in a quality of service QoS, optionally measured at the sender or the receiver. When the QoS is on an unacceptable side of a threshold of acceptability, the sender sends diversity packets at an increased rate. Increasing the diversity rate while either reducing or maintaining the overall transmission rate is new. CELP-based multiple-description data partitioning sends the base or important information plus a subset of fixed excitation in one packet and sends the base or important information plus the complementary subset of fixed excitation in another packet. Reconstruction produces acceptable quality when only one of the two packets is received and better quality when both packets are received. Reconstruction provides for single and multiple lost packets. | 12-08-2011 |
| 20110300677 | Novel Method to Enhance Channel Stress in CMOS Processes - The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current. | 12-08-2011 |
| 20110300673 | POST-DISPENSE VACUUM OVEN FOR REDUCING UNDERFILL VOIDS DURING IC ASSEMBLY - An IC assembly method for reducing voids in underfill material. An IC die is bonded to a substrate which creates a gap between the IC die and the substrate. An underfill material that has a curing temperature (Tuc) is dispensed around at least one side along a perimeter of the gap, where capillary forces draw the underfill material into the gap to at least partially fill the gap to form an underfilled IC assembly. After the dispensing, a vacuum oven process is applied to the underfilled IC assembly which applies a vacuum of 15 to 140 torr and a temperature that is between Tuc −85° C. and Tuc −5° C., for reducing voids in the underfill material. The underfill material is then cured by heating the underfilled IC assembly to a temperature ≧ Tuc. | 12-08-2011 |
| 20110300666 | PHOTODIODE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - The invention provides a semiconductor device manufactured with a plurality of photodiodes so that it does not short circuit, and includes an opening without leakage. A second semiconductor layer ( | 12-08-2011 |
| 20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 12-08-2011 |
| 20110299301 | FIXED-FREQUENCY LLC RESONANT POWER REGULATOR - An LLC resonant AC/DC power regulator system ( | 12-08-2011 |
| 20110298842 | Sparse Source Array for Display Pixel Array Illumination with Rotated Far Field Plane - A pixel array display system including an illumination source of discrete emitters with uniform emitting areas, a separate collimator in front of each emitter, and a condenser in front of said collimators which focuses collimated light from the emitters onto the pixel array. The pixel array display system does not include a light homogenizing optical element such as a light pipe. Each emitter is focused onto at least 75 percent of the pixels. A portion of the emitters which provide collimated light cones proximate to a modulated light optical cone from the pixel array may be provided reduced power in a high contrast operating mode. | 12-08-2011 |
| 20110298488 | THROUGH CARRIER DUAL SIDE LOOP-BACK TESTING OF TSV DIE AFTER DIE ATTACH TO SUBSTRATE - A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter. | 12-08-2011 |
| 20110298092 | DIODES WITH A DOG BONE OR CAP-SHAPED JUNCTION PROFILE TO ENHANCE ESD PERFORMANCE, AND OTHER SUBSTRUCTURES, INTEGRATED CIRCUITS AND PROCESSES OF MANUFACTURE AND TESTING - An integrated circuit structure includes a semiconductor doped area (NWell) having a first conductivity type, and a layer (PSD) that overlies a portion of said doped area (NWell) and has a doping of an opposite second type of conductivity that is opposite from the first conductivity type of said doped area (NWell), and said layer (PSD) having a corner in cross-section, and the doping of said doped area (NWell) forming a junction beneath said layer (PSD) with the doping of said doped area (NWell) diluted in a vicinity below the corner of said layer (PSD). Other integrated circuits, substructures, devices, processes of manufacturing, and processes of testing are also disclosed. | 12-08-2011 |
| 20110297088 | THIN EDGE CARRIER RING - A PECVD deposition chamber with a circular pedestal with a recessed portion in the outer top surface of the pedestal. A PECVD deposition chamber with a circular wafer carrier ring with a recessed portion in the outer top surface of the wafer carrier ring. | 12-08-2011 |
| 20110296263 | SEMICONDUCTOR TEST SYSTEM AND METHOD - A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test. | 12-01-2011 |
| 20110294305 | Antireflective Coating - Device and method for an antireflective coating to improve image quality in an image display system. A preferred embodiment comprises a first high refractive index layer overlying a reflective surface of an integrated circuit, a first low refractive index layer overlying the first high refractive index layer, a second high refractive index layer overlying the first low refractive index layer, and a second low refractive index layer overlying the second high refractive index layer. The alternating layers of high refractive index material and low refractive index material form an optical trap, allowing light to readily pass through in one direction, but not so easily in a reverse direction. The dual alternating layer topology improves the antireflective properties of the antireflective layer and permits a wide range of adjustments for manipulating reflectivity and color point. | 12-01-2011 |
| 20110294246 | SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES - An apparatus includes a semiconductor layer ( | 12-01-2011 |
| 20110292699 | Systems and Methods for Distortion Reduction - Systems and devices for reduction of total harmonic distortion in power supply circuits are presented. Example embodiments of the disclosed systems of total harmonic distortion reduction reduce a low frequency output voltage ripple seen by the voltage control loop by adding a compensating ripple voltage to the output feedback signal. The compensating signal may be scaled by the user to optimize the degree of ripple reduction, and may be automatically adjusted by monitoring circuitry to scale with a power factor control circuit output power level. | 12-01-2011 |
| 20110292514 | COLOR LIGHT COMBINER - For combining light from different light sources that are spatially apart, an optical system comprises a prism assembly that comprises a totally-internally-surface and a dichroic filter. The totally-internally-surface and the dichroic filter are configured for reflecting light of different colors or polarizations, so as to combine light of different polarization or colors into a single beam. | 12-01-2011 |
| 20110291263 | IC HAVING DIELECTRIC POLYMERIC COATED PROTRUDING FEATURES HAVING WET ETCHED EXPOSED TIPS - A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature coupled to the active circuitry that protrudes from the bottomside surface or the topside semiconductor surface. The topside semiconductor surface and/or bottomside surface and the protruding feature are coated with a dielectric polymer. A portion of the dielectric polymer is removed from the protruding feature using a solvent to expose a tip portion of the protruding feature for electrical connection thereto. With a solvent that does not corrode or oxidize the exposed protruding feature tips, the need for a conventional subsequent chemical exposure to remove corrosion or oxidation is avoided. | 12-01-2011 |
| 20110291222 | SILICON DIOXIDE CANTILEVER SUPPORT AND METHOD FOR SILICON ETCHED STRUCTURES - An apparatus includes a semiconductor layer ( | 12-01-2011 |
| 20110289371 | LOW POWER SCAN AND DELAY TEST METHOD AND APPARATUS - Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures. | 11-24-2011 |
| 20110289370 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 11-24-2011 |
| 20110285745 | METHOD AND APPARATUS FOR TOUCH SCREEN ASSISTED WHITE BALANCE - A method and apparatus for performing automatic white balance utilizing a touch screen. The method includes determining an area on a touch screen for performing automatic white balance, extracting portion of a frame relating to the determined area, determining red, green and blue values of the extracted portion of the frame, and performing automatic white balance based on the determined red, green and blue values. | 11-24-2011 |
| 20110285451 | PRECISION VOLTAGE DIVIDER - A circuit for producing a quotient of two input voltages, Vy and Vx has a resistor across which said two input voltages are selectively successively applied. An operational amplifier has a reference potential (Vref) applied to one input, and a tap selectively connectable at one side to various points of the resistor is connected at its other side to the other input of the operational amplifier. The tap also provides a voltage output node of the circuit. After the tap has been configured with input voltage Vy applied across the resistor so that a voltage on the output node is substantially equal to the reference potential (Vref), when the input voltage Vx is applied across the resistor, a voltage on the output node represents a quotient of the input voltages Vy and Vx. | 11-24-2011 |
| 20110285439 | Digital to Frequency Synthesis Using Flying-Adder with Dithered Command Input - To make Flying-Adder architecture even more powerful, a new concept, time-average-frequency, is incorporated into the clock generation circuitry. This is a fundamental breakthrough since it attacks the clock generation problem from its root: how is the clock signal used in real systems? By investigating from this direction, a much more powerful architecture, fixed-VCO-Flying-Adder architecture, is created. Furthermore, based on fixed-VCO-Flying-Adder frequency synthesizer and time-average-frequency, a new type of component called Digital-to-Frequency Converter (DFC) is born. | 11-24-2011 |
| 20110285423 | SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS - First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half. | 11-24-2011 |
| 20110283154 | ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION - A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator | 11-17-2011 |
| 20110282639 | Modeling of Non-Quasi-Static Effects During Hot Carrier Injection Programming of Non-Volatile Memory Cells - A non-quasi-static model of the programming behavior of a floating-gate metal-oxide-semiconductor (MOS) transistor. This model is based on evaluation of a body current, for example determined as a function of voltages applied to the transistor from the circuit environment. The body current is used as an input to a non-quasi-static function on which the modeled gate injection current is based. In one example, the body current is applied to a representation of a series R-C circuit beginning from a time corresponding to the onset of avalanche breakdown, with the voltage across the capacitor serving as a control voltage of a voltage-controlled current source that drives the gate injection current. Integration of the gate injection current over the time interval of the programming pulse provides an estimate of the trapped charge at the floating gate. | 11-17-2011 |
| 20110281593 | HIGH RESOLUTION, LOW POWER DESIGN FOR CPRI/OBSAI LATENCY MEASUREMENT - As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the “round trip” latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains. | 11-17-2011 |
| 20110281433 | ETCHING METHOD USING AN AT LEAST SEMI-SOLID MEDIA - An etching method that uses an etch reactant retained within at least a semi-solid media ( | 11-17-2011 |
| 20110280314 | SLICE ENCODING AND DECODING PROCESSORS, CIRCUITS, DEVICES, SYSTEMS AND PROCESSES - A video decoder includes a memory ( | 11-17-2011 |
| 20110280312 | VIDEO PROCESSING DEVICE WITH MEMORY OPTIMIZATION IN IMAGE POST-PROCESSING - A video processing device is disclosed that includes a processor unit with a processor and a memory having a reorder buffer. The processor includes a reorder module, a frame rate conversion module, and post-processing function modules. The reorder, frame rate conversion, and post-processing modules access video frames stored in the reorder buffer, while the video frames are stored in the reorder buffer, and reorder, adjust the frame rate, and perform image processing, respectively, on the video frames, while the video frames are stored in the reorder buffer. A method implemented on such a video processing device is also disclosed. A computer-readable storage medium with instructions stored thereon for performing the method is also disclosed. | 11-17-2011 |
| 20110280261 | Interleaver Design and Header Structure For ITU G.hnem - Embodiments of the invention provide an interleaver design and header fields for ITU-T G.hnem. The header may comprise two parts that are separately encoded. A common header segment is encoded alone, and an embedded header segment is encoded with payload data. The interleaver operates on blocks having a size based upon a total number of input bits in an FEC codeword block, a total number of bits loaded on symbols that span a half mains cycle, or a maximum fragment size of 3072 bits. The blocks may be repeated before interleaving. Each block and its repetitions may be interleaved together, such as for header data, or each block and repetition may be interleaved separately, such as for payload data. Cyclic padding may be used on each block to create an integer number of symbols for transmission. | 11-17-2011 |
| 20110279651 | Method and Apparatus for Auto-Convergence Based on Auto-Focus Point for Stereoscopic Frame - A method and apparatus for performing auto-convergence on a frame of a stereoscopic image or video based on at least one auto-focus point. The method includes retrieving a location of focus points from the image, estimating the disparity of focus points in the image, determining the disparity of the frame for the stereoscopic image or video, and shifting the frame to automatically adjust the convergence of the fame for the stereoscopic image or video. | 11-17-2011 |
| 20110279297 | Analog-to-Digital Conversion - One embodiment of the present invention includes an analog-to-digital converter (ADC) system. The system includes an ADC configured to generate digital samples that are digital versions of at least one analog signal at a sampling frequency and a memory configured to store data corresponding to an average value of the digital samples in at least one register. The system further includes a processor configured to access the data corresponding to the average value for processing at an access frequency that is less than the sampling frequency. | 11-17-2011 |
| 20110279170 | EMBEDDED SAR BASED ACTIVE GAIN CAPACITANCE MEASUREMENT SYSTEM AND METHOD - A system for measuring a capacitor (C | 11-17-2011 |
| 20110278936 | LOW DROPOUT REGULATOR WITH MULTIPLEXED POWER SUPPLIES - Generally, with low drop out (LDO) regulators that use multiplexed power supplies, the transistors within the regulator can use a substantial amount of area. Here, a regulator is provided that uses a multiplexer to commonly control the back-gates of multiple power transistors within the LDO. By doing this, the area overhead that would normally be present with these switches (of the multiplexer) can be dramatically reduced without sacrificing performance. | 11-17-2011 |
| 20110278693 | HIGH-VOLTAGE VARIABLE BREAKDOWN VOLTAGE (BV) DIODE FOR ELECTROSTATIC DISCHARGE (ESD) APPLICATIONS - Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV | 11-17-2011 |
| 20110276847 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 11-10-2011 |
| 20110276731 | DUAL-PORT FUNCTIONALITY FOR A SINGLE-PORT CELL MEMORY DEVICE - A network node ( | 11-10-2011 |
| 20110276216 | AUTOMOTIVE CRUISE CONTROLS, CIRCUITS, SYSTEMS AND PROCESSES - A cruise control includes an input ( | 11-10-2011 |
| 20110275210 | METHOD OF MAKING VERTICAL TRANSISTOR WITH GRADED FIELD PLATE DIELECTRIC - An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region. | 11-10-2011 |
| 20110275168 | SINGLE STEP CMP FOR POLISHING THREE OR MORE LAYER FILM STACKS - A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer>a RR for the silicon oxide layer>a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer. | 11-10-2011 |
| 20110273946 | UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING - An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included. | 11-10-2011 |
| 20110273217 | VOLTAGE GENERATING CIRCUIT FOR AN ATTENUATOR - A circuit includes a digital-to-analog converter (DAC), coupled to a power supply, that provides a first current at a first output terminal of the DAC and a second current at a second output terminal of the DAC, the first current being differential to the second current; a first circuit, coupled to the first output terminal of the DAC and to the second output terminal of the DAC, that generates a first voltage and a second voltage, the first voltage being non-linear with respect to the first current and the second voltage being non-linear with respect to the second current; and an attenuator coupled to the first circuit, and responsive to the first voltage and the second voltage to attenuate an input signal of the attenuator and to generate linear attenuation characteristics in decibels with respect to the first current and the second current. | 11-10-2011 |
| 20110273204 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 11-10-2011 |
| 20110273186 | CIRCUIT FOR CONTROLLING TEMPERATURE AND ENABLING TESTING OF A SEMICONDUCTOR CHIP - A circuit for controlling temperature of a semiconductor chip includes a first heating element that is built into the semiconductor chip. The first heating element generates heat to increase the temperature of the semiconductor chip. The chip also includes a temperature controller that is coupled to the first heating element and built into the semiconductor chip. The temperature controller controls the temperature to enable testing of the semiconductor chip at a desired temperature. | 11-10-2011 |
| 20110272449 | Dual Capillary IC Wirebonding - The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies. | 11-10-2011 |
| 20110271160 | ACCELERATING SCAN TEST BY RE-USING RESPONSE DATA AS STIMULUS DATA ABSTRACT - Scan testing of plural target electrical circuits, such as circuits | 11-03-2011 |
| 20110268289 | GROUND LOOP NOISE REJECTION FOR A HEADSET SUBSYSTEM - For headphone subsystems that employ common ground switches for speaker outputs (for example), there can be a significant issue with cross-talk and ground noise. Here, configurations for an amplifier and switch network are provided, which generally cancel noise from the “ground switch,” so as to provide an improvement over conventional configurations with little overhead. Additionally, the cross-talk for these configurations are not generally dependent on the “ground switch” or speaker impedance. | 11-03-2011 |
| 20110267177 | Effective Low Voltage to Medium Voltage Transmission on PRIME Band - Coupling and interface circuits for powerline modems are disclosed. A powerline modem may be coupled to a low voltage (LV) line or a medium voltage (MV) line using a circuit that is designed to compensate for signal attenuation and loss that is created by the a LV/MV transformer and/or a MV coupler. In one embodiment, separate coupling transformers may be used by the modem for reception and transmission. In other embodiments, a capacitance is switched on the transmission line before the modem transmits to lower the line impedance. | 11-03-2011 |
| 20110267146 | OPEN LOOP COARSE TUNING FOR A PLL - In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency. | 11-03-2011 |
| 20110266693 | TCE COMPENSATION FOR PACKAGE SUBSTRATES FOR REDUCED DIE WARPAGE ASSEMBLY - A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages. | 11-03-2011 |
| 20110266624 | ELECTROSTATIC DISCHARGE PROTECTION HAVING MULTIPLY SEGMENTED DIODES IN PROXIMITY TO TRANSISTOR - An ESD protection device for an I/O pad ( | 11-03-2011 |
| 20110264970 | LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths ( | 10-27-2011 |
| 20110263051 | INTERLEAF FOR LEADFRAME IDENTIFICATION - A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified. | 10-27-2011 |
| 20110261719 | SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR IMPROVED PACKET SCHEDULING OF MEDIA OVER PACKET - A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals. | 10-27-2011 |
| 20110261632 | Combined Write Assist and Retain-Till-Accessed Memory Array Bias - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode. | 10-27-2011 |
| 20110261629 | Reduced Power Consumption in Retain-Till-Accessed Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias devices are included within each memory array block, the bias devices constructed as one or more array transistors. The bias devices for a memory array block may be connected in parallel with one another. In the RTA mode, the bias devices drop the power supply voltage differential across each of the SRAM cells. In a normal operating mode, a core transistor serves as a switch, shorting out the bias devices so that the full power supply differential appears across the SRAM cells. | 10-27-2011 |
| 20110261609 | Retain-Till-Accessed Power Saving Mode in High-Performance Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices are included within each memory array block, for example associated with individual columns, and connected between a reference voltage node for cross-coupled inverters in each memory cell in the associated column or columns, and a ground node. In a normal operating mode, a switch transistor connected in parallel with the bias devices is turned on, so that the ground voltage biases the cross-coupled inverters in each cell. In the RTA mode, the switch transistors are turned off, allowing the bias devices to raise the reference bias to the cross-coupled inverters, reducing power consumed by the cells in that mode. | 10-27-2011 |
| 20110261328 | Apparatus and Method for Reducing Speckle in Display of Images - An apparatus and method of reducing speckle in projection of images is provided that includes the elements or features of producing a first image and displacing the first image to produce a second image that will reduce speckle relating to the first image when the first image and the second image are displayed on a display medium. | 10-27-2011 |
| 20110260766 | DIGITAL SUPPRESSION OF SPIKES ON AN I2C BUS - An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I | 10-27-2011 |
| 20110258506 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 10-20-2011 |
| 20110258502 | WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE - Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. | 10-20-2011 |
| 20110258500 | ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 10-20-2011 |
| 20110257943 | NODE-BASED TRANSIENT ACCELERATION METHOD FOR SIMULATING CIRCUITS WITH LATENCY - When modeling a circuit, transient analysis is an important part of the analysis. However, for transient analyses, device model evaluating can consume a considerable amount of time, when using conventional simulators. Here, a simulator is provided that allows for detection of latency on a node-by-node basis, as opposed to a device-by-device basis with conventional simulators. Using this type of analysis can greatly reduce the time of an analysis, which affects both the cost of a product and its time to market. | 10-20-2011 |
| 20110256729 | Showerhead for CVD Depositions - A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer. | 10-20-2011 |
| 20110256687 | Method for Fabricating Through Substrate Microchannels - A method of forming large microchannels in an integrated circuit by etching an enclosed trench into the substrate and later thinning the backside to expose the bottom of the trenches and to remove the material enclosed by the trench to form the large microchannels. A method of simultaneously forming large and small microchannels. A method of forming structures on the backside of the substrate around a microchannel to mate with another device. | 10-20-2011 |
| 20110255557 | Coexistence of Prime, S-FSK and G3 Devices in Powerline Communications - Communication devices, such as base nodes and modems, that comply with two or more different standards operate on a shared communication channel. To avoid mutual interference, a base node operating under a first standard reserves time using a contention free period designation. The base node allows devices operating under a second standard to communicate during the reserved time by not assigning the contention free period to another device operating under the first standard. Alternatively, a device using the first standard may avoid interference from transmissions generated under the second standard by modifying data packets prior to transmission. A prefix corresponding to a preamble in the second standard is added to the beginning of the data packet created under the first standard. Devices operating under the second standard observe the prefix and recognize that the channel is active. The second-standard devices backoff from transmission thereby minimizing interference. | 10-20-2011 |
| 20110255453 | SYSTEM AND METHOD FOR SCRAMBLING AND TIME-HOPPING - A system and method for scrambling and time-hopping in an ultra-wideband wireless network. In one embodiment, a wireless device includes a symbol mapper and a dynamic chip scrambler. The dynamic chip scrambler is configured to scramble each of a plurality of consecutive bursts of a time-hopped packet according to a pseudo-random scrambling sequence that varies from burst to burst. | 10-20-2011 |
| 20110255433 | ROBUST PACKET DETECTION, SYMBOL TIMING, CHANNEL LENGTH ESTIMATION AND CHANNEL RESPONSE ESTIMATION FOR WIRELESS SYSTEMS - A method in accordance with an embodiment of the invention includes producing a first signal match indication based on at least one match indication indicative of a match between at least one signal received in at least one band and a reference signal. The method also includes producing a first signal multipath combined signal based upon the first signal match indication, and detecting a first peak in the first multipath combined signal. | 10-20-2011 |
| 20110255136 | APPARATUS AND METHOD FOR TRANSMITTING DATA IN A MULTI-CHANNEL SYSTEM - Conventional analog front ends or AFEs for scanners are implemented using multiple integrated circuits or ICs. As a result, there is typically a problem of skew (due at least in part to manufacturing process variations) for these different ICs in the AFE. Here, an AFE is provided which serializes input data so as to compensate for skew. | 10-20-2011 |
| 20110254881 | System and Method for Dynamically Altering a Color Gamut - System and method for dynamically altering a color gamut used in projection display systems. An embodiment comprises determining a dim color from colors used in representing an image, adjusting the dim color to increase an available display time for a non-dim color used to represent the image, adjusting the non-dim color using the available display time, and generating a color sequence based on the adjusted dim color and the adjusted non-dim color. The pixel intensities of a dim color are increased, permitting a shortening of the display time of the dim color. The newly freed display time can be reallocated to all colors to increase the amount of light used to display the image, thereby increasing image brightness or altering color point. | 10-20-2011 |
| 20110254729 | CROSS COUPLED POSITIONING ENGINE (PE) ARCHITECTURE FOR SENSOR INTEGRATION IN GLOBAL NAVIGATION SATELLITE SYSTEM (GNSS) - Embodiments of the disclosure provide a cross coupled position engine architecture for sensor integration in a Global Navigation Satellite System. In one embodiment, a data processing engine for processing inertial sensor data within a positioning system receiver is disclosed. The data processing engine includes a first input for receiving the sensor data, and a second input for receiving a positioning data. The data processing system also includes a memory and a processor. The processor of the data processing system is coupled to the memory and to the first and second input. The processor of the data processing system is configured to calculate a net acceleration profile data from the inertial sensor data and from the positioning data. The net acceleration profile data calculated by the processor of the data processing system is used for the Global Positioning System (GPS) receiver to subsequently calculate a position and a velocity data. | 10-20-2011 |
| 20110254603 | PHASE INTERPOLATOR AND A DELAY CIRCUIT FOR THE PHASE INTERPOLATOR - Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs. | 10-20-2011 |
| 20110254150 | Method of Manufacturing a Semiconductor Device - The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements | 10-20-2011 |
| 20110253999 | SEMICONDUCTOR WAFER HAVING SCRIBE LINE TEST MODULES INCLUDING MATCHING PORTIONS FROM SUBCIRCUITS ON ACTIVE DIE - A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension. | 10-20-2011 |
| 20110252293 | Concatenated Coding Architecture for G.hnem PHY - Embodiments provide a method for determining the number of parity bytes that are added by a Reed-Solomon encoder. The number of parity bytes are equivalent to the error correcting capability of the Reed-Solomon code. The number of parity bytes is based on the payload length or the information block size used in the Reed-Solomon encoder. Other factors may also be used to make this choice. | 10-13-2011 |
| 20110250720 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 10-13-2011 |
| 20110248392 | Ball-Grid Array Device Having Chip Assembled on Half-Etched metal Leadframe - A ball grid array device ( | 10-13-2011 |
| 20110248347 | LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS - An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed. | 10-13-2011 |
| 20110243206 | POWER BACK-OFF MODE AND CIRCUIT FOR 100BASET - Generally, 100BaseT allows for the establishment of links on cables (such as Category 5 or CATS cables) up to 120 m or more in length. In a given industrial Ethernet system, many of the cables deployed will be less than 120 m in length, and, in fact, many of the cables are much shorter than 120 m. Yet, the transmission amplitude output from each unit is generally the same, regardless of cable length. Here, Power Back Off (PBO) circuitry is provided in a unit that operates in a PBO mode to passively estimate a cable length and adjust its corresponding transmission amplitudes to generally match the estimated cable length so as to reduce power consumption. | 10-06-2011 |
| 20110243079 | Transmission Modes and Signaling for Uplink MIMO Support or Single TB Dual-Layer Transmission in LTE Uplink - This invention is a method of wireless telephony. A bases station configures a user equipment for single-antenna port or multi-antenna port operation via Radio Resource Control (RRC) signaling including a 5-bit MCS-RV and 1-bit NDI for the second codeword (CW1) are needed for the DCI format 4. | 10-06-2011 |
| 20110243009 | Physical Downlink Shared Channel Muting on Cell-Specific Reference Symbols Locations for of Non-Serving Cells - The primary serving base station transmits PDSCH with zero energy on the inter-cell CRS resource element location. This is called mute PDSCH. Within the first Physical Resource Block (PRB | 10-06-2011 |
| 20110242879 | TWO WORD LINE SRAM CELL WITH STRONG-SIDE WORD LINE BOOST FOR WRITE PROVIDED BY WEAK-SIDE WORD LINE - An integrated circuit having a static random access memory (SRAM) includes an array of SRAM cells arranged in rows and columns having a write word line and a read/write word line connected to provide row access to the array of SRAM cells. The SRAM also includes a coupling capacitance connected between the write word line and a detachable allocation of the read/write word line as well as an overdrive module connected to charge the coupling capacitance and provide an overdrive voltage on the detachable allocation of the read/write word line during activation of the write word line. A method of operating an integrated circuit having an SRAM includes providing an overdrive voltage on the detachable allocation of the read/write word line corresponding to a charge redistribution across the coupling capacitance during part of a write cycle. | 10-06-2011 |
| 20110241771 | ACTIVE MUTE SCHEME FOR AN AMPLIFIER - Conventional muting circuitry for amplifiers (which usually uses clamps) generally has about 20-30 dB of attenuation. Here, an integrated circuit or IC is provided that includes an amplifier, switch networks, and a controller. The controller provides control signals to the switch network to provide mute functionality by actively muting the amplifier. In particular, feedback is provided through at least one of the switch networks to drive the output of the amplifier to null or ground so as to provide 70-80 dB (or more) of attenuation. | 10-06-2011 |
| 20110241155 | SEMICONDUCTOR THERMOCOUPLE AND SENSOR - Conventional “on-chip” or monolithically integrated thermocouples are very mechanically sensitive and are expensive to manufacture. Here, however, thermocouples are provided that employ different thicknesses of thermal insulators to help create thermal differentials within an integrated circuit. By using these thermal insulators, standard manufacturing processes can be used to lower cost, and the mechanical sensitivity of the thermocouple is greatly decreased. Additionally, other features (which can be included through the use of standard manufacturing processes) to help trap and dissipate heat appropriately. | 10-06-2011 |
| 20110239068 | TAM WITH SCAN FRAME COPY REGISTER COUPLED WITH SERIAL OUTPUT - Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation. | 09-29-2011 |
| 20110239066 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 09-29-2011 |
| 20110235706 | REGION OF INTEREST (ROI) VIDEO ENCODING - A method of encoding an image frame in a video encoding system. The image frame has a region of interest (ROI) and a non region of interest (non-ROI). In the method, quantization scale for the image frame based on rate control information is determined. ROI statistics based on residual energy of the ROI and non-ROI is then calculated. Quantization scale for the image frame based on ROI priorities and ROI statistics is calculated. Further, quantization scales for ROI and non-ROI based on ROI priorities are determined. | 09-29-2011 |
| 20110235600 | METHOD AND SYSTEM FOR USING RESOURCES ALLOCATED TO A WIRELESS NETWORK IN A COEXISTING WIRELESS NETWORK - A wireless device includes a first wireless transceiver and a second wireless transceiver. The first wireless transceiver is configured to communicate via a first wireless network, and includes a first scheduler configured to schedule communication via the first wireless network. The second wireless transceiver is configured to communicate via a second wireless network. The second wireless transceiver includes a second scheduler. The second scheduler is configured to identify a resource allocated to the second wireless transceiver for a transaction via the second wireless network, to identify a portion of the resource used by the second wireless transceiver for the transaction, and to transfer information defining the portion to the first transceiver. The first scheduler is also configured to schedule, based on the information transferred by the second scheduler, the first transceiver to communicate via the first wireless network using the resource allocated to the second wireless transceiver for the transaction. | 09-29-2011 |
| 20110234534 | CAPACITANCE MEASUREMENT SYSTEM AND METHOD - A capacitance measurement system precharges first terminals ( | 09-29-2011 |
| 20110234312 | AMPLIFIER WITH IMPROVED STABILITY - A circuit includes an amplifier that defines a positive input terminal, a negative input terminal, a positive output terminal and a negative output terminal. The circuit also includes a first positive feedback path between the positive input terminal and the positive output terminal of the amplifier. Further, the circuit includes a second positive feedback path between the negative input terminal and the negative output terminal of the amplifier. The first positive feedback path and the second positive feedback path compensate the amplifier. | 09-29-2011 |
| 20110231932 | SECURITY INTRUSION DETECTION AND RESPONSE - A system comprises an enclosure, host logic contained in the enclosure, and intrusion security logic also contained in the enclosure. The intrusion security logic is coupled to the host logic and configured to detect a security intrusion to the system and to respond to a security intrusion with a user-configurable trigger event. The intrusion security logic implements at least two tamper blocks, each tamper block configured to monitor one more input signals and initiate a trigger event when a security breach of the enclosure is detected. At least one of the tamper blocks comprises a state machine whose operation is controlled by way of user-programmable registers. | 09-22-2011 |
