| TESSERA RESEARCH LLC Patent applications |
| Patent application number | Title | Published |
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| 20120126389 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND VIAS CONNECTED TO THE CENTRAL CONTACTS - The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface. | 05-24-2012 |
| 20120119367 | CONDUCTIVE PADS DEFINED BY EMBEDDED TRACES - An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself. | 05-17-2012 |
| 20120104595 | NO FLOW UNDERFILL - A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element. | 05-03-2012 |
| 20120092832 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS - A microelectronic assembly includes a dielectric element having oppositely-facing first and second surfaces and one or more apertures extending between the surfaces, the dielectric element further having conductive elements thereon; a first microelectronic element having a rear surface and a front surface facing the first surface of the dielectric element, the first microelectronic element having a first edge and a plurality of contacts exposed at the front surface thereof; a second microelectronic element including having a rear surface and a front surface facing the rear surface of the first microelectronic element, a projecting portion of the front surface of the second microelectronic element extending beyond the first edge of the first microelectronic element, the projecting portion being spaced from the first surface of the dielectric element, the second microelectronic element having a plurality of contacts exposed at the projecting portion of the front surface; leads extending from contacts of the microelectronic elements through the at least one aperture to at least some of the conductive elements; and a heat spreader thermally coupled to at least one of the first microelectronic element or the second microelectronic element. | 04-19-2012 |
| 20120068365 | METAL CAN IMPEDANCE CONTROL STRUCTURE - A microelectronic assembly includes an interconnection element, element contacts, first and second metal layers, conductive elements, and first and second microelectronic devices. The first metal layer may extend beyond at least one of the edges of the first microelectronic device. The conductive elements may respectively extend beyond at least one of the edges of the first metal layer. The first metal layer may have a surface disposed at a substantially uniform spacing from at least substantial portions of the conductive elements, such that a desired impedance may be achieved for the conductive elements. The conductive elements may be spaced a smaller distance from the metal layer than the distance of the conductive elements from the front surface of the first microelectronic device. The second metal layer may be connectable to a source of reference potential. | 03-22-2012 |
| 20120068361 | STACKED MULTI-DIE PACKAGES WITH IMPEDANCE CONTROL - A microelectronic assembly may include microelectronic devices arranged in a stack and having device contacts exposed at respective front surfaces. Signal conductors having substantial portions extending above the front surface of the respective microelectronic devices connect the device contacts with signal contacts of an underlying interconnection element. A rear surface of a microelectronic device of the stack overlying an adjacent microelectronic device of the stack is spaced a predetermined distance above and extends at least generally parallel to the substantial portions of the signal conductors connected to the adjacent device, such that a desired impedance may be achieved for the signal conductors connected to the adjacent device. | 03-22-2012 |
| 20120068352 | STACKED CHIP ASSEMBLY HAVING VERTICAL VIAS - An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region. | 03-22-2012 |
| 20120068351 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 03-22-2012 |
| 20120068338 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 03-22-2012 |
| 20120068330 | STAGED VIA FORMATION FROM BOTH SIDES OF CHIP - A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad. | 03-22-2012 |
| 20120068327 | MULTI-FUNCTION AND SHIELDED 3D INTERCONNECTS - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 03-22-2012 |
| 20120068317 | TSOP WITH IMPEDANCE CONTROL - A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant. | 03-22-2012 |
| 20120025365 | MICROELECTRONIC PACKAGES WITH NANOPARTICLE JOINING - A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof. | 02-02-2012 |
| 20120020026 | MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION - A microelectronic unit includes a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can include a microelectronic element having a bottom surface adjacent the inner surface, a top surface remote from the bottom surface, and a plurality of contacts at the top surface. The microelectronic element can include terminals electrically connected with the contacts of the microelectronic element. The microelectronic unit can include a dielectric region contacting at least the top surface of the microelectronic element. The dielectric region can have a planar surface located coplanar with or above the front surface of the carrier structure. The terminals can be exposed at the surface of the dielectric region for interconnection with an external element. | 01-26-2012 |
| 20120018895 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 01-26-2012 |
| 20120018894 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 01-26-2012 |
| 20120018893 | METHODS OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM - A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device. | 01-26-2012 |
| 20120018868 | MICROELECTRONIC ELEMENTS HAVING METALLIC PADS OVERLYING VIAS - A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element. | 01-26-2012 |
| 20120018863 | MICROELECTRONIC ELEMENTS WITH REAR CONTACTS CONNECTED WITH VIA FIRST OR VIA MIDDLE STRUCTURES - A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via. A rear contact can be electrically connected to the conductive via and exposed at the rear surface for electrical connection with an external circuit element, such as another like microelectronic unit, a microelectronic package, or a circuit panel. | 01-26-2012 |
| 20120013001 | STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS - A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant. | 01-19-2012 |
| 20120013000 | STACKABLE MOLDED MICROELECTRONIC PACKAGES - A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings in the encapsulant at least partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may only partially expose top surfaces of posts. | 01-19-2012 |
| 20120007232 | MICROELECTRONIC PACKAGES WITH DUAL OR MULTIPLE-ETCHED FLIP-CHIP CONNECTORS - A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region. | 01-12-2012 |
| 20110285020 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 11-24-2011 |
| 20110147953 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 06-23-2011 |
| 20110147928 | MICROELECTRONIC ASSEMBLY WITH BOND ELEMENTS HAVING LOWERED INDUCTANCE - Microelectronic assemblies can have multiple conductive bond elements, e.g., bond wires, or a lead bond and a bond wire, extending between a pair of a substrate contact and a chip contact. E.g., a first bond wire can have ends joined to the contacts of the chip and substrate. A second bond wire can be joined to the ends of the first bond wire so that the second bond wire does not touch either the chip contact or the substrate contact to which the first bond wire is joined. In one example, a bond wire has a looped connection with first and second ends joined at a first contact and a middle portion joined to a second contact. In one example, first and second bond elements, e.g., bond wires or lead bonds can connect first and second pairs of a substrate contact with a chip contact. A third bond element, e.g., a bond wire or bond ribbon, can be joined to ends of the first and second bond elements. | 06-23-2011 |
| 20110101535 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 05-05-2011 |
| 20110095408 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 04-28-2011 |
| 20100314591 | CURABLE RESINS AND ARTICLES MADE THEREFROM - Optical devices of excellent optical and physical properties produced from cured resins are disclosed. The resins and/or the cured hybrid polymer material made with the resins are characterized by a high level of cycloaliphatic-containing groups. Specific additives that can participate in crosslinking the curable polysiloxane provide additional physical property advantages. | 12-16-2010 |
| 20100232128 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND REFERENCE WIREBOND - A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip, connected together with an interconnection element, e.g., substrate, the latter having signal contacts and reference contacts. The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds can be connected to device contacts exposed at a surface of the microelectronic device. Reference conductors, e.g., reference wirebonds can be provided, at least one of which can be connected with two reference contacts of the interconnection element. The reference wirebond can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor. In such manner a desired impedance may be achieved for the signal conductor. | 09-16-2010 |
| 20100230828 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 09-16-2010 |
| 20090316378 | Wafer level edge stacking - A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween. | 12-24-2009 |
