# Ternarylogic LLC

Ternarylogic LLC Patent applications | ||

Patent application number | Title | Published |
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20130145237 | Methods and Systems for Rapid Error Location in Reed-Solomon Codes - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude or error value are determined. The error is corrected by the processor. | 06-06-2013 |

20120233527 | Methods and Systems for Rapid Error Location in Reed-Solomon Codes - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude or error value are determined. The error is corrected by the processor. | 09-13-2012 |

20110293062 | Method and Apparatus for Rapid Synchronization of Shift Register Related Symbol Sequences - A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism. | 12-01-2011 |

20110276854 | Methods and Systems for Rapid Error Correction by Forward and Reverse Determination of Coding States - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor. | 11-10-2011 |

20110214038 | Methods and Systems for Rapid Error Correction of Reed-Solomon Codes - An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor. | 09-01-2011 |

20110182421 | ENCIPHERMENT OF DIGITAL SEQUENCES BY REVERSIBLE TRANSPOSITION METHODS - Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences. | 07-28-2011 |

20110170697 | Ternary and Multi-Value Digital Signal Scramblers, Decramblers and Sequence Generators - Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described. | 07-14-2011 |

20110064214 | Methods and Apparatus in Alternate Finite Field Based Coders and Decoders - Methods and apparatus for coding and decoding n-state symbols with n≧2 and n>2 and n>3 and n>4 are provided wherein at least one implementation of an addition over an alternate finite field GF(n) and an inverter defined by a multiplication over the alternate finite field GF(n) are provided. Encoders and decoders implementing a single n-state truth table that is a truth table of an addition over an alternate finite field GF(n) modified in accordance with at least one inverter defined by a multiplication over the alternate finite field GF(n) are also provided. Encoders include scramblers, Linear Feedback Shift Register (LFSR) based encoders, sequence generator based encoders, block coders, streaming cipher encoders, transposition encoders, hopping rule encoders, Feistel network based encoders, check symbol based encoders, Hamming coder, error correcting encoders, encipherment encoders, Elliptic Curve Coding encoders and all corresponding decoders. Systems applying encoders and decoders also are provided. | 03-17-2011 |

20100322414 | TERNARY AND HIGHER MULTI-VALUE DIGITAL SCRAMBLERS/DESCRAMBLERS - Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler. | 12-23-2010 |

20100299579 | Methods and Systems for Error-Correction in Convolutional and Systematic Convolutional Decoders in Galois Configuration - Convolutional coders having an n-state with n≧2 Linear Feedback Shift Registers (LFSR) in Galois configuration with k shift register elements with k>1 are provided. Corresponding decoders are also provided. A convolutional coder generates a sequence of coded n-state symbols. A content of a starting position of an LFSR in a decoder is determined when sufficient error free coded symbols are available. Up to k symbols in error are corrected. A systematic convolutional coder and decoder are also provided. | 11-25-2010 |

20100271243 | N-State Ripple Adder Scheme Coding with Corresponding N-State Ripple Adder Scheme Decoding - Methods and apparatus for implementing an n-state ripple-adder scheme coder with n≧2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems. | 10-28-2010 |

20100211803 | Multi-Valued Scrambling and Descrambling of Digital Data on Optical Disks and Other Storage Media - Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed. | 08-19-2010 |

20100180097 | Generation and Self-Synchronizing Detection of Sequences Using Addressable Memories - Methods and apparatus to implement LFSRs and LFSR based sequence generators, detectors, scramblers and descramblers by addressable memory are disclosed. The methods and apparatus may be processing binary or n-valued symbols, with n>2. Methods to uniquely characterize n-valued Gold sequence are also disclosed. Self-synchronizing methods to detect sequences which can be decomposed into unique words are also disclosed. Methods and apparatus to implement Fibonacci and Galois LFSRs are disclosed. | 07-15-2010 |

20100164548 | Implementing Logic Functions With Non-Magnitude Based Physical Phenomena - An n-valued switch with n≧2 and n>2 and n>7, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed. | 07-01-2010 |

20090172501 | Multi-State Symbol Error Correction in Matrix Based Codes - Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated with a matrix for detection of one or more symbols in error and the location of such symbols in error. Symbols in error are reconstructed from symbols not in error, error syndromes and check symbols not in error. Deliberately created errors that can be corrected are used as nuisance errors. | 07-02-2009 |