| TERADYNE, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120136477 | Storage Device Transport, Clamping And Testing - A storage device transporter ( | 05-31-2012 |
| 20120102374 | STORAGE DEVICE TESTING - A storage device testing system ( | 04-26-2012 |
| 20120082463 | ELECTRO-OPTICAL COMMUNICATIONS LINK - A communications link for carrying data between a transmitter and a receiver operates according to a communications protocol (such as PCI Express (PCIe)) specifying a reduced-power link operating state in which the transmitter generates a reduced-amplitude electrical output signal and the receiver is to operate in a power-save mode. The communications link includes an electro-optical link and a circuit coupling an output of the transmitter to an electrical input of the electro-optical link. The circuit is configured to detect initiation of the reduced-power operating state and to send messages to the receiver to maintain a normal amplitude of an optical signal on the electro-optical link. | 04-05-2012 |
| 20110310724 | DAMPING VIBRATIONS WITHIN STORAGE DEVICE TESTING SYSTEMS - A storage device test slot includes a housing. The housing defines a test compartment for receiving a storage device for testing. One or more tuned mass dampers are connected to the housing. The one or more tuned mass dampers are configured to inhibit vibration of the housing at one or more predetermined frequencies. | 12-22-2011 |
| 20110275170 | SYSTEM FOR CONCURRENT TEST OF SEMICONDUCTOR DEVICES - A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time. | 11-10-2011 |
| 20110210759 | FAST OPEN CIRCUIT DETECTION FOR OPEN POWER AND GROUND PINS - A system and method for identifying opens among parallel connections on a circuit assembly such as a printed circuit board (PCB). In a learn phase performed on a known good circuit assembly, a group of parallel connected pins are excited with a first signal. A second signal, out-of-phase with the first signal, is applied to a second group of pins associated with the component. The amplitude and/or the phase of the second signal and the number and/or specific pins in the second group of pins are selected so that first and second signals coupled to a detector plate proximal to the component substantially offset. During a manufacturing test, signals of comparable amplitude and phase are applied to like pins on a like component of a circuit assembly under test. If the response signal coupled to a like detector plate is below a threshold, it is determined that each pin in the group of parallel connected pins is connected. If the amplitude of the response is over the threshold, one or more of the parallel pins is determined to be open. Additional tests may be performed to identify which of the parallel pins is likely open. | 09-01-2011 |
| 20110204910 | METHOD AND APPARATUS FOR TESTING ELECTRICAL CONNECTIONS ON A PRINTED CIRCUIT BOARD - A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known “good” PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure. | 08-25-2011 |
| 20110172807 | Enclosed Operating Area for Storage Device Testing Systems - A storage device testing system includes one or more test racks, and one or more test slots housed by the one or more test racks, each test slot being configured to receive a storage device for testing. The storage device testing system also includes a transfer station for supplying storage devices to be tested. The one or more test racks and the transfer station at least partially define an operating area. The storage device testing system can also include automated machinery that is disposed within the operating area and is configured to transfer storage devices between the transfer station and the one or more test slots, and a cover at least partially enclosing the operating area, thereby at least partially inhibiting air exchange between the operating area and an environment surrounding the test racks. | 07-14-2011 |
| 20110087942 | Programmable Protocol Generator - A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test. | 04-14-2011 |
| 20110083825 | Temperature Control within Storage Device Testing Systems - A storage device testing system cooling circuit includes a plurality of test racks. Each of the test racks include a test slot compartment and a test electronics compartment. Each of the test slot compartments includes multiple test slots, and one or more cooling conduits configured to convey a cooling liquid toward the test slots. Each of the test electronics compartments includes test electronics configured to communicate with the test slots for executing a test algorithm, and a heat exchanger in fluid communication with the one or more cooling conduits. The heat exchanger is configured to cool an air flow directed toward the test electronics. | 04-14-2011 |
| 20110070748 | METHODS AND APPARATUS FOR CONNECTING PRINTED CIRCUIT BOARDS USING ZERO-INSERTION WIPING FORCE CONNECTORS - A circuit board assembly includes a primary board, and a connector mounted to a mounting location of the primary board. The connector includes compliant conductors, each compliant conductor having a first end and a second end. The connector further includes a connector body supported by the primary board. The connector body constrains the first end of each compliant conductor at the mounting location and the second end of each compliant conductor at an interface location. The connector further includes a movable member which is capable of moving relative to the connector body along an axis extending between the mounting location and the interface location. The movable member is constructed and arranged to control tension of the compliant conductors while the connector body constrains the first end of each compliant conductor at the mounting location and the second end of each compliant conductor at the interface location. | 03-24-2011 |
| 20110013362 | Test Slot Cooling System for a Storage Device Testing System - A test slot cooling system for a storage device testing system includes a storage device transporter having first and second portions. The first portion of the storage device transporter includes an air director and the second portion of the storage device transporter is configured to receive a storage device. The test slot cooling system includes a test slot housing defining an air entrance and a transporter opening for receiving the storage device transporter. The air entrance is in pneumatic communication with the air director of the received storage device transporter. The test slot cooling system also includes an air mover in pneumatic communication with the air entrance of the test slot housing for delivering air to the air director. The air director directs air substantially simultaneously over at least top and bottom surfaces of the storage device received in the storage device transporter. | 01-20-2011 |
| 20100312516 | PROTOCOL AWARE DIGITAL CHANNEL APPARATUS - In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal. | 12-09-2010 |
| 20100259277 | AUTOMATED TEST EQUIPMENT EMPLOYING TEST SIGNAL TRANSMISSION CHANNEL WITH EMBEDDED SERIES ISOLATION RESISTORS - Automated test equipment for high-speed testing of devices under test (DUTs) includes a tester channel circuit generating a high-speed electrical test signal applied to the signal input terminal of each DUT, and a contacter board in physical and electrical contact with the DUTs. The contacter board has a high-speed signal transmission channel including (1) an electrical contact at which the high-speed electrical test signal is received, (2) conductive etch extending from the electrical contact to isolation areas each adjacent to the signal input terminal of a respective DUT, and (3) an embedded series isolation resistor formed on an inner layer of the contacter board at a respective isolation area forming a connection between the conductive etch and the adjacent signal input terminal of the respective DUT. | 10-14-2010 |
| 20100207651 | TEST ACCESS COMPONENT FOR AUTOMATIC TESTING OF CIRCUIT ASSEMBLIES - A reliable and durable method of testing of printed circuit boards is presented. Test access components are placed in contact regions for providing electrical connectivity between test probes and the printed circuit board. In some cases, a test access component may be a surface mount resistor. The test access component may provide two points of contact for test probes to make electrical and mechanical contact with the printed circuit board. Test access components may also provide for increased durability of testing, allowing for a greater number of test contacts to be made between test probes and printed circuit boards than were previously possible. | 08-19-2010 |
| 20100083732 | Disk Drive Emulator And Method Of Use Thereof - A disk drive emulator for testing a test slot of a disk drive testing system includes an emulator body, an interface connecter disposed on the emulator body, and at least one vibration sensor disposed on the emulator body. The emulator body comprises a material having a tensile modulus of at least 40×10̂6 Psi. | 04-08-2010 |
| 20090297328 | Processing Storage Devices - A storage device processing system that includes at least one automated transporter, at least one rack accessible by the at least one automated transporter, and multiple test slots housed by the at least one rack. Each test slot is configured to receive a storage device for testing. The storage device processing system includes a conveyor arranged in a loop around and being accessible by the at least one automated transporter. The conveyor receives and transports the storage device thereon. The at least one automated transporter is configured to transfer the storage device between the conveyor and one of the test slots of the at least one rack. | 12-03-2009 |
| 20090265136 | Disk Drive Emulator And Method Of Use Thereof - A disk drive emulator for testing a test slot of a disk drive testing system includes an emulator housing, a testing circuit housed in the emulator housing, and an interface connector disposed on the emulator housing and in electrical communication with the testing circuit. The disk drive emulator includes at least one sensor in electrical communication with the testing circuit. The at least one sensor is selected from the group consisting of a temperature sensor, a vibration sensor, and a humidity sensor. The testing circuit is configured to test power delivery of the test slot to the disk drive emulator, monitor the at least one sensor, and monitor connector resistance between the test slot and the disk drive emulator. | 10-22-2009 |
| 20090265032 | Transferring Storage Devices Within Storage Device Testing Systems - A method of transferring storage devices within a storage device testing system includes actuating an automated transporter to substantially simultaneously retrieve multiple storage devices presented for testing, and actuating the automated transporter to substantially simultaneously deliver each retrieved storage device to a respective test slot of the storage device testing system and substantially simultaneously insert each storage device in the respective test slot. | 10-22-2009 |
| 20090262445 | Bulk Feeding Disk Drives to Disk Drive Testing Systems - A method of supplying disk drives to a disk drive testing system includes placing a disk drive tote, carrying multiple disk drives, in a presentation position accessible to an automated transporter of the disk drive testing system. The method includes actuating the automated transporter to retrieve one of the disk drives from the disk drive tote, and actuating the automated transporter to deliver the retrieved disk drive to a test slot of the disk drive testing system and insert the disk drive in the test slot. | 10-22-2009 |
| 20090262444 | Transferring Disk Drives Within Disk Drive Testing Systems - A method of transferring disk drives within a disk drive testing system includes actuating an automated transporter to retrieve multiple disk drives presented for testing, and actuating the automated transporter to deliver each retrieved disk drive to a respective test slot of the disk drive testing system and insert each disk drive in the respective test slot. | 10-22-2009 |
| 20090261872 | FAST, LOW POWER FORMATTER FOR AUTOMATIC TEST SYSTEM - Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE includes a signal formatter with an SR latch having set and reset inputs each connected through or coupled to a number of signal channels. Each signal channel may receive a long pulse from a timing generator and generate a short pulse. Each signal channel has a current steering circuit that couples the short pulses to the set or reset ports of the latch. Because the outputs of each current steering circuit have a high impedance when not sending a pulse, multiplexing circuitry and/or circuitry to logically OR the outputs of separate signal channels are unnecessary. The hardware eliminated by this design simplifies and improves the ATE. Additionally, the latch can be set and reset in quick succession with good timing resolution. | 10-22-2009 |
| 20090212802 | Test system with high frequency interposer - An interposer with a conductive housing is disclosed. Conductive members pass through insulators positioned in openings in the conductive housing. The conductive housing may be grounded, providing a closely spaced ground structure for signal conductors passing through the conductive housing and therefore providing a desirable impedance to signals carried by the conductive members. Such an interposer may be used in a test system to couple high speed signals between instruments that generate or measure test signals and devices under test. | 08-27-2009 |
| 20090167401 | Timing Signal Generator Providing Synchronized Timing Signals At Non-Integer Clock Multiples Adjustable By More Than One Period - A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations. | 07-02-2009 |
| 20090153993 | Disk Drive Testing - A disk drive testing system includes at least one robotic arm defining a first axis substantially normal to a floor surface. The robotic arm is operable to rotate through a predetermined arc about and extend radially from the first axis. Multiple racks are arranged around the robotic arm for servicing by the robotic arm. Each rack houses multiple test slots that are each configured to receive a disk drive transporter configured to carry a disk drive for testing. A transfer station is arranged for servicing by the robotic arm. The transfer station includes multiple tote receptacles that are each configured to receive a disk drive tote. | 06-18-2009 |
| 20090153992 | Disk Drive Testing - A disk drive testing system includes at least one robotic arm defining a first axis substantially normal to a floor surface. The robotic arm is operable to rotate through a predetermined arc about and extend radially from the first axis. Multiple racks are arranged around the robotic arm for servicing by the robotic arm. Each rack houses multiple test slots that are each configured to receive a disk drive transporter configured to carry a disk drive for testing. | 06-18-2009 |
| 20090100303 | Adjustable test pattern results latency - A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles. | 04-16-2009 |
| 20080285636 | CALIBRATING JITTER - Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter. | 11-20-2008 |
| 20080238516 | Timing interpolator with improved linearity - A programmable timing interpolator circuit includes low output impedance buffer circuitry driving a node having a capacitance that varies in response to a programmed delay to be introduced by the interpolator. The low output impedance buffer circuitry receives a subset of course delay signals and, after buffering, provides the buffered course delay signals to fine delay circuitry. The buffer may include two source follower stages coupled to each other. The first source follower stage shifts the level of the received signal down. The second source follower stage shifts the level of the signal from the first source follower stage up. The first and second source follower stages are implemented using NMOS and PMOS technology. | 10-02-2008 |
| 20080208495 | ELECTRICALLY STIMULATED FINGERPRINT SENSOR TEST METHOD - Systems and techniques for testing a fingerprint sensor are described. A conductive material is placed on a surface of the fingerprint sensor, and an electrical signal is applied to the conductive material. The electrical signal affects a first electrical property associated with first and second electrodes of the fingerprint sensor. First and second measurements of a second electrical property associated with the first and second electrodes are acquired, the second electrical property being correlated to the first electrical property. The first and second measurements are analyzed to determine whether the fingerprint sensor has one or more defects. | 08-28-2008 |
| 20080205172 | DESIGN-FOR-TEST MICRO PROBE - Systems and techniques for testing a device having first and second interconnected chips that are internal to the device include selecting a site on a communication pathway along which an internal signal travels inside the device between the first and second chips, and connecting a test probe to the site. | 08-28-2008 |
