Teledyne Licensing, LLC Patent applications |
Patent application number | Title | Published |
20110220967 | PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound. | 09-15-2011 |
20100151625 | BURIED VIA TECHNOLOGY FOR THREE DIMENSIONAL INTEGRATED CIRCUITS - A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer. | 06-17-2010 |
20090147195 | Method and apparatus to reduce dielectric discharge in liquid crystal devices driven with high voltages - The present invention relates to a method and apparatus to reduce dielectric discharge in liquid crystal cells driven with high voltage. In one embodiment, the present invention is a liquid crystal cell including a substrate with a surface and a tapered conductive film on top of the surface of the substrate including a first end and a second end. In another embodiment, the present invention is a method for forming a liquid crystal cell including covering a portion of a surface of a substrate with a shadow mask and then depositing conductive film onto the surface of the substrate such that the conductive film is tapered. | 06-11-2009 |
20080238446 | High temperature microelectromechanical (MEM) devices - A microelectromechanical (MEM) device per the present invention comprises a semiconductor wafer—typically an SOI wafer, a substrate, and a high temperature bond which bonds the wafer to the substrate to form a composite structure. Portions of the composite structure are patterned and etched to define stationary and movable MEM elements, with the movable elements being mechanically coupled to the stationary elements. The high temperature bond is preferably a mechanical bond, with the wafer and substrate having respective bonding pads which are aligned and mechanically connected to form a thermocompression bond to effect the bonding. A metallization layer is typically deposited on the composite structure and patterned to provide electrical interconnections for the device. The metallization layer preferably comprises a conductive refractory material such as platinum to withstand high temperature environments. | 10-02-2008 |
20080217723 | BACKSIDE ILLUMINATED CMOS IMAGE SENSOR WITH PINNED PHOTODIODE - A backside illuminated CMOS image sensor having an silicon layer with a front side and a backside, the silicon layer liberates charge when illuminated from the backside with light, an active pixel circuitry located on the front side of the semiconductor layer, a pinned photodiode adjacent to the active pixel circuitry on the front side of the semiconductor layer and configured to collect charge liberated in the semiconductor layer, and an implant located in the semiconductor layer, underneath the active pixel circuitry, for allowing charge liberated in the semiconductor layer to drift from the backside of the semiconductor layer to the pinned photodiode on the front side of the semiconductor layer. | 09-11-2008 |
20080217661 | TWO-DIMENSIONAL TIME DELAY INTEGRATION VISIBLE CMOS IMAGE SENSOR - A two dimensional time delay integration CMOS image sensor having a plurality of pinned photodiodes, each pinned photodiode collects a charge when light strikes the pinned photodiode, a plurality of electrodes separating the plurality of pinned photodiodes, the plurality of electrodes are configured for two dimensional charge transport between two adjacent pinned photodiodes, and a plurality of readout nodes connected to the plurality of pinned photodiodes via address lines. | 09-11-2008 |