Taiwan Semiconductor Manufacturing Company,Ltd.
|Taiwan Semiconductor Manufacturing Company,Ltd. Patent applications|
|Patent application number||Title||Published|
|20140246751||Integrated Circuit Using Deep Trench Through Silicon (DTS) - An embodiment radio frequency area of an integrated circuit includes a substrate having a first resistance, the substrate including an implant region, a buried oxide layer disposed over the substrate, an interface layer between the substrate and the buried oxide layer, the interface layer having a second resistance lower than the first resistance, a silicon layer disposed over the buried oxide layer, and an interlevel dielectric disposed in a deep trench, the deep trench extending through the silicon layer, the buried oxide layer, and the interface layer over the implant region. In an embodiment, the deep trench extends through a polysilicon layer disposed over the silicon layer.||09-04-2014|
|20140038088||Method of Fabricating a Lithography Mask - A method of fabricating an extreme ultraviolet (EUV) mask is disclosed. The method includes providing a substrate, forming a reflective multilayer (ML) over the substrate, forming a buffer layer over the reflective ML, forming an absorption layer over the buffer layer and forming a capping layer over the absorption layer. The capping layer and the absorption layer are etched to form the EUV mask.||02-06-2014|
|20130228871||PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE - A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.||09-05-2013|
|20100151648||Strained Channel Transistor - A semiconductor device, such as a PMOS or an NMOS transistor, having a stressed channel region is provided. The semiconductor device is formed by recessing the source/drain regions after forming a gate stack. The substrate is removed under the gate stack. Thereafter, an epitaxial layer is formed under the gate stack and in the source/drain regions. The epitaxial layer may be doped in the source/drain regions. In an embodiment, a lower portion of the epitaxial layer and the epitaxial layer under the gate stack may be doped with a conductivity type opposite of the conductivity type of the source/drain regions. In another embodiment of the present invention, a lower portion of the epitaxial layer is left undoped.||06-17-2010|
Patent applications by Taiwan Semiconductor Manufacturing Company,Ltd.