| TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120032743 | LOW-NOISE AMPLIFIER WITH GAIN ENHANCEMENT - A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element. | 02-09-2012 |
| 20120032742 | CMOS MILLIMETER-WAVE VARIABLE-GAIN LOW-NOISE AMPLIFIER - A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal. | 02-09-2012 |
| 20120032293 | EDGE DEVICES LAYOUT FOR IMPROVED PERFORMANCE - A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area. | 02-09-2012 |
| 20120026805 | SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION - An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level. | 02-02-2012 |
| 20120025273 | ELECTROMIGRATION RESISTANT STANDARD CELL DEVICE - A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells. | 02-02-2012 |
| 20120021602 | LOW RESISTANCE AND RELIABLE COPPER INTERCONNECTS BY VARIABLE DOPING - A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity. | 01-26-2012 |
| 20120019968 | TRANSMISSION-LINE-BASED ESD PROTECTION - An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad. | 01-26-2012 |
| 20120018786 | HIGHLY STRAINED SOURCE/DRAIN TRENCHES IN SEMICONDUCTOR DEVICES - A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable I | 01-26-2012 |
| 20120017428 | METHOD FOR FABRICATING A SEMICONDUCTOR TEST PROBE CARD SPACE TRANSFORMER - A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. | 01-26-2012 |
| 20120017197 | METHOD AND APPARATUS FOR ELECTRONIC SYSTEM MODEL GENERATION - A method of transmitting data is disclosed. At least one system block of a system-on-chip (SoC) is modeled at an untimed functional level in first and second untimed functional models. First and second transaction level (TL) models of the at least one system block system block are modeled at a transaction level (TL) using the first and second untimed functional models, respectively. First and second cycle accurate (CA) models are modeled at a cycle accurate (CA) level using the first and second TL models, respectively. Data is transmitted from the first untimed functional model to the first CA model, from the first CA model to the second CA model via a CA bus, and from the second CA model to the second untimed functional model. | 01-19-2012 |
| 20120015493 | INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 01-19-2012 |
| 20120014158 | MEMORY DEVICES - A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time. | 01-19-2012 |
| 20120012047 | METHOD OF TEMPERATURE DETERMINATION FOR DEPOSITION REACTORS - A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer. | 01-19-2012 |
| 20120005640 | METHOD AND APPARATUS FOR ELECTRONIC SYSTEM FUNCTION VERIFICATION AT TWO LEVELS - A method for verifying functionality of a system-on-chip (SoC) comprises modeling a system block in first and second models at a first level and a second level lower than the first level, respectively. A stimulus transaction is generated at a first testbench at the first level. The stimulus transaction is transmitted from the first testbench to a second testbench at the second level. The stimulus transaction is transformed into a first response transaction, using the first model, at the first level. The stimulus transaction received at the second testbench is transformed into a second response transaction, using the second model, at the second level. The first and second response transactions are stored in first and second response queues, respectively. Functionality of the SoC at the first and second levels is verified based on a comparison at the first testbench between head entries of the first and second response queues. | 01-05-2012 |
| 20110316617 | METHOD AND APPARATUS FOR FULL CLOCK CYCLE CHARGE PUMP OPERATION - A charge pump comprises at least one charge pump cell and control logic. The at least one charge pump cell is configured to receive a power supply voltage and provide a pump output voltage higher than the power supply voltage. The control logic is configured to receive an oscillator signal and a level detector enable signal, provide at least one cell clock signal, based on the oscillator signal, to the at least one charge pump cell, control the at least one pump cell to charge while the level detector enable signal is asserted, and control the at least one pump cell to continue to charge after the level detector enable signal is deasserted and until a full pulse cycle of the oscillator signal is completed. | 12-29-2011 |
| 20110310525 | SYSTEM FOR SECURELY DECHUCKING WAFERS - A system for chucking and de-chucking a work piece comprises a wafer stage having a chuck support for supporting a chuck. The wafer stage further comprises a chuck mounted on the chuck support for receiving and attaching the work piece thereto; a support lift means for supporting the work piece; a driving means coupled to the support lift means for gradually raising the support lift means to contact the work piece in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected. | 12-22-2011 |
| 20110304372 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high. | 12-15-2011 |
| 20110298551 | INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME - A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV. | 12-08-2011 |
| 20110292754 | MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION - A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit. | 12-01-2011 |
| 20110287627 | SEMICONDUCTOR TEST PAD STRUCTURES - A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer. | 11-24-2011 |
| 20110286136 | ESD BLOCK WITH SHARED NOISE OPTIMIZATION AND CDM ESD PROTECTION FOR RF CIRCUITS - A RF device includes a RF integrated circuit having a RF input and a RF output. The RF integrated circuit has an NMOS transistor having a gate terminal coupled to the RF input, a drain terminal coupled to a first power supply node and a source terminal coupled to a second power supply node. The RF integrated circuit is vulnerable to damage from an ESD event. A primary ESD protection circuit is coupled to the RF input and between the first and second power supply nodes. A secondary ESD protection circuit is coupled between the RF input and the second power supply node. The secondary ESD protection circuit includes a secondary ESD protection diode coupled between the gate and source terminals of the NMOS transistor. | 11-24-2011 |
| 20110279175 | SYSTEM AND METHOD FOR RC CALIBRATION USING PHASE AND FREQUENCY - An RC filter is calibrated to a desired cutoff frequency by initializing the filter with a cutoff frequency. An input signal is filtered by the RC filter to provide a filter output signal having phase and frequency values. The cutoff frequency of the RC filter is adjusted based on the phase and frequency values of the filter output signal if the phase and frequency values do not satisfy a predetermined condition. The filtering and adjusting are repeated until the phase and frequency values of the filter output signal satisfy the predetermined condition. A calibration apparatus has a frequency generator, a resistor-capacitor (RC) filter, a phase comparator, a frequency detector, and a state machine. The phase comparator, frequency detector, and state machine are configured to calibrate the RC filter to a cutoff frequency specified by the reference signal based on a filter output signal of the RC filter. | 11-17-2011 |
| 20110279150 | BUFFER OPERATIONAL AMPLIFIER WITH SELF-OFFSET COMPENSATOR AND EMBEDDED SEGMENTED DAC FOR IMPROVED LINEARITY LCD DRIVER - A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range. | 11-17-2011 |
| 20110273949 | ELECTRICAL FUSE PROGRAMMING TIME CONTROL SCHEME - A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse. | 11-10-2011 |
| 20110267901 | SWITCHED CAPACITOR BASED NEGATIVE BITLINE VOLTAGE GENERATION SCHEME - A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node. | 11-03-2011 |
| 20110267213 | FINGER-SPLIT AND FINGER-SHIFTED TECHNIQUE FOR HIGH-PRECISION CURRENT MIRROR - A current cell array includes a number of current cell groups arranged such that they extend in a first direction. Each of the current cell groups is identified by a first identifier that increases in a direction of a gradient across the current cell array. A number of current cells are included in each of the current cell groups. Each of the current cells is identified by a respective second identifier that increases in the direction of the gradient across the current cell array. The current cells are positioned in the current cell groups based on the first and second identifiers. | 11-03-2011 |
| 20110261086 | TWO-STAGE DAC ARCHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT SERIAL CHARGE REDISTRIBUTION DAC - A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. | 10-27-2011 |
| 20110261085 | TWO-STAGE DAC ACHITECTURE FOR LCD SOURCE DRIVER UTILIZING ONE-BIT PIPE DAC - A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. | 10-27-2011 |
| 20110261084 | DAC ARCHITECTURE FOR LCD SOURCE DRIVER - A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code. | 10-27-2011 |
| 20110260819 | CONTINUOUSLY TUNABLE INDUCTOR WITH VARIABLE RESISTORS - An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil. | 10-27-2011 |
| 20110248759 | RETENTION FLIP-FLOP - A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal. | 10-13-2011 |
| 20110242904 | Read Only Memory and Operating Method Thereof - A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages. | 10-06-2011 |
| 20110241746 | LOW POWER SMALL AREA STATIC PHASE INTERPOLATOR WITH GOOD LINEARITY - A static phase interpolator includes first and second plurality of inverters coupled in parallel between an output node and first and second input nodes for receiving first and second clock signals, and first and second plurality of switch elements coupled to the first and second plurality of inverters for selectively turning on individual ones of the inverters in response to a phase control signal. An inverter is coupled the output node. The interpolator may include a slew rate controller coupled to the first and second input nodes. Also, each inverter of the interpolator may include a PMOS transistor in series with an NMOS transistor and have a respective one of the switch elements disposed between the PMOS and NMOS transistors. | 10-06-2011 |
| 20110233678 | JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS - An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions. | 09-29-2011 |
| 20110233654 | NANO-CRYSTAL GATE STRUCTURE FOR NON-VOLATILE MEMORY - A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost. | 09-29-2011 |
| 20110227689 | Method of Creating Spiral Inductor having High Q Value - A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided and a plurality of metal layers are formed on the substrate. A spirally patterned conductor layer is formed over and in the substrate and in the metal layers to produce a planar spiral inductor. A via hole is formed over and in the substrate and in the metal layers within the spirally patterned conductor layer, the via hole being formed by a through silicon via (TSV) process. Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface of the metal layers. | 09-22-2011 |
| 20110227162 | METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD - A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET. | 09-22-2011 |
| 20110223767 | CONTROL WAFER RECLAMATION PROCESS - A method of recycling a control wafer having a low-k dielectric layer deposited thereon involves etching a portion of the low-k dielectric layer using a plasma resulting in a residual film of the low-k dielectric layer and byproduct particulates of carbon on the substrate. The residual dielectric film is removed by wet etching with a low polarization organic solvent that includes HF and a surfactant. | 09-15-2011 |
| 20110221494 | PHASE-LOCKED LOOP START UP CIRCUIT - A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit. | 09-15-2011 |
| 20110219876 | MOTION DETECTION USING CAPACITOR HAVING DIFFERENT WORK FUNCTION MATERIALS - An apparatus for detecting mechanical displacement in a micro-electromechanical system includes a capacitor having first and second plates spaced from one another, the first and second plates having different work functions and being electrically connected with each other. The capacitor plates are movable with respect to one another such that a spacing between the plates changes in response to a force. A current through the capacitor represents a rate of change in the spacing between the plates at a given time. | 09-15-2011 |
| 20110210393 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 09-01-2011 |
| 20110209109 | HIGH-SPEED SRAM - A method includes a) receiving a design for a static random access memory (SRAM) array including an SRAM cell having a read port cell, the read port cell including first and second MOS transistors each having an initial threshold voltage (Vth); b) adjusting one of a gate channel width (Wg) or a gate channel length (Lg) of one of the first and second MOS transistors to modify the Vth of at least one of the first and second MOS transistors; c) simulating a response of the SRAM array, the simulation providing response data for the SRAM array including the Vth for the first and second MOS transistors; and d) iteratively repeating steps b) and c) until a desired Vth is achieved. | 08-25-2011 |
| 20110207409 | ELECTROSTATIC DISCHARGE CIRCUIT USING INDUCTOR-TRIGGERED SILICON-CONTROLLED RECTIFIER - A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material. | 08-25-2011 |
| 20110207332 | THIN FILM COATED PROCESS KITS FOR SEMICONDUCTOR MANUFACTURING TOOLS - A plasma processing apparatus used in semiconductor device manufacturing includes a process kit formed of insulating materials such as quartz and coated with a Y | 08-25-2011 |
| 20110207279 | INTEGRATED METHOD FOR FORMING HIGH-K METAL GATE FINFET DEVICES - Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN | 08-25-2011 |
| 20110194362 | WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT - A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array. | 08-11-2011 |
| 20110194086 | WAFER EDGE EXPOSURE MODULE - A wafer edge exposure module connected to a semiconductor wafer track system. The wafer edge exposure module includes a wafer spin device, an optical system, a scanner interface module, and a controller. The wafer spin device supports a wafer for processing. The optical system directs exposure light on a respective edge portion of the wafer simultaneously to create a dummy track on the edge of the wafer. The scanner interface module sends and/or receives dummy edge exposure information from a scanner via a computer network. The controller receives the dummy edge exposure information from the scanner interface module and uses the exposure information to control the optical system. | 08-11-2011 |
| 20110193658 | FILTER USING A WAVEGUIDE STRUCTURE - A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports. | 08-11-2011 |
| 20110193175 | LOWER PARASITIC CAPACITANCE FINFET - An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer. | 08-11-2011 |
| 20110186909 | ESD PROTECTION CIRCUIT FOR RFID TAG - An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively. | 08-04-2011 |
| 20110183508 | REPLACEMENT GATE FinFET DEVICES AND METHODS FOR FORMING THE SAME - A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition. | 07-28-2011 |
| 20110177668 | METHOD OF MAKING A THIN FILM RESISTOR - A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole. | 07-21-2011 |
| 20110175165 | SEMICONDUCTOR FIN DEVICE AND METHOD FOR FORMING THE SAME USING HIGH TILT ANGLE IMPLANT - An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used. | 07-21-2011 |
| 20110174991 | SCANNING METHOD AND SYSTEM USING 2-D ION IIMPLANTER - An ion implanter system has a movable wafer support for holding a semiconductor wafer and a beam source that generates a beam for implanting ions in the semiconductor wafer while the wafer is moving. A plurality of path segments are identified, through which the wafer support is to move to expose the semiconductor wafer to the ion beam. A first position and a second position are identified for each respective one of the plurality of path segments, such that, when the wafer is in each first position and each second position, a perimeter of the beam projected in a plane of the wafer is tangent to a perimeter of the wafer. The ion implanter is configured to automatically move the wafer along each of the plurality of path segments, starting at the respective first position on each respective path segment and stopping at the respective second position on the same segment, so as to expose the wafer to the beam for implanting ions in the wafer. | 07-21-2011 |
| 20110169581 | RING-SHAPED VOLTAGE CONTROL OSCILLATOR - In one embodiment, a circuit topology for use in an n-phase voltage controlled oscillator (VCO) or injection-locked frequency divider includes a transmission line ring having n transmission line delay segments connected at n junctions, where n is an integer greater than or equal to 3. Each transmission line segment provides a 1/n wavelength signal delay between adjacent junctions. The transmission line ring is coupled to a first power supply node. Each of the junctions has a respective transistor coupled thereto, each transistor having a first source/drain terminal coupled to its respective junction, a second source/drain terminal coupled to a second power supply node, and a gate terminal, wherein the gate terminal is coupled to a signal that is ½ wavelength out-of-phase with respect to a signal at the first source/drain terminal of the transistor. | 07-14-2011 |
| 20110169085 | METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE - A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film. | 07-14-2011 |
| 20110165722 | METHOD FOR FORMING STRUCTURE FOR REDUCING NOISE IN CMOS IMAGE SENSORS - A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes a black light filter layer and an opaque layer covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer where the light blocking portion is desired but not over the active section. | 07-07-2011 |
| 20110157963 | SRAM WORD-LINE COUPLING NOISE RESTRICTION - A DC mode word-line coupling noise restriction circuit for multiple-port Random Access Memory cells. This circuit may comprise a Static Random Access Memory array. The SRAM array contains a plurality of columns and a plurality of rows with an SRAM cell formed at a cross-point of the columns and rows. Each SRAM cell has a first word-line conductor and a second word-line conductor. The first word-line conductor is connected to a first coupling noise restriction circuit. The first coupling noise restriction circuit comprises an inverter and a NMOSFET. The inverter has another NMOSFET and a PMOSFET. | 06-30-2011 |
| 20110156148 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME USING SEMICONDUCTOR FIN DENSITY DESIGN RULES - A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion. | 06-30-2011 |
| 20110153055 | WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL - A method includes selecting one of a plurality of existing transistor models for which fabrication and performance data are available, receiving first model data for a next-generation transistor based on target response data and the selected transistor model data, and simulating a response of a circuit including the next-generation transistor. The selection of the existing transistor model is based on target response data for the next-generation transistor for which fabrication and performance data are not available. The simulation is performed using the first transistor model data for the next-generation transistor. A difference between the target response and the simulated response of the next-generation transistor is calculated, and the first model data representing the next-generation transistor is stored in a computer readable storage medium if the performance data difference between the target response and the simulated response is below a threshold. | 06-23-2011 |
| 20110126397 | PVD TARGET WITH END OF SERVICE LIFE DETECTION CAPABILITY - A PVD target structure for use in physical vapor deposition. The PVD target structure includes a consumable slab of source material and one or more detectors for indicating when the slab of source material is approaching or has been reduced to a given quantity representing a service lifetime endpoint of the target structure. Each detector includes an enclosure which may be made by forming a plurality of bores in a bulk material and separating the bulk material into a plurality of discrete enclosure units each including one of the bores. Alternatively, the enclosure of the detector may be made using a mold having one or more mold members and an extrusion, casting, electrical chemical plating, and/or sheet forming method. | 06-02-2011 |
| 20110119648 | ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY - A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology. | 05-19-2011 |
| 20110117724 | ISOLATION STRUCTURE FOR STRAINED CHANNEL TRANSISTORS - A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region. | 05-19-2011 |
| 20110115088 | INTERCONNECT WITH FLEXIBLE DIELECTRIC LAYER - An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion. | 05-19-2011 |
| 20110111571 | METHOD FOR OBTAINING QUALITY ULTRA-SHALLOW DOPED REGIONS AND DEVICE HAVING SAME - A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×10 | 05-12-2011 |
| 20110095394 | ANTIFUSE AND METHOD OF MAKING THE ANTIFUSE - A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse. | 04-28-2011 |
| 20110090198 | LCD DRIVER - A method includes outputting a first signal from a first DAC decoder circuit in response to receiving a first number of bits of a digital control signal, outputting a second signal from a second DAC decoder circuit in response to receiving a second number of bits of the digital control signal, and alternately outputting one of the first and second signals to an LCD column from a buffer coupled to the first and second DAC decoder circuits. The first signal has a voltage level equal to one of a first plurality of voltage levels received at one of a first plurality of inputs of the first DAC decoder circuit. The second signal has a voltage level equal to one of a second plurality of voltage levels received at one of a second plurality of inputs of the second DAC decoder circuit. | 04-21-2011 |
| 20110084682 | PROGRAMMABLE CURRENT MIRROR - A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node. | 04-14-2011 |
| 20110083496 | SEMICONDUCTOR PROCESSING APPARATUS WITH SIMULTANEOUSLY MOVABLE STAGES - A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other. | 04-14-2011 |
| 20110083115 | ROBUST METHOD FOR INTEGRATION OF BUMP CELLS IN SEMICONDUCTOR DEVICE DESIGN - A system and method for computer-aided design of semiconductor integrated circuit devices provides for having dummy vias beneath UBM of bump cells to prevent delamination at the bump cell sites during bonding. The dummy vias are inserted into the design and bump cell placement occurs during the floorplanning stage and prior to placement and routing of the active integrated circuit components. In this manner, a sufficiently high via density is achieved and design information on the bump cells including the dummy vias is provided to a computer-aided design, CAD, system along with program instructions for carrying out the indicated sequence of design operations. | 04-07-2011 |
| 20110080220 | TEMPERATURE COMPENSATED INTEGRATOR - A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures. | 04-07-2011 |
| 20110080201 | DIGITAL LOGIC CIRCUITS HAVING A PULSE WIDTH TIMING CIRCUIT - A pulse width timing includes a first complementary resistor-capacitor (RC) circuit having an input for receiving an input signal, and a second complementary RC circuit coupled to an output of the first complementary RC circuit, wherein the first and second complementary RC circuits cooperate to produce an output signal based on the input signal, the output signal being delayed and having an adjusted pulse width with respect to the input signal. | 04-07-2011 |
| 20110079922 | INTEGRATED CIRCUIT WITH PROTECTIVE STRUCTURE, AND METHOD OF FABRICATING THE INTEGRATED CIRCUIT - A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices. | 04-07-2011 |
| 20110079820 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 04-07-2011 |
| 20110076832 | DUAL ETCH METHOD OF DEFINING ACTIVE AREA IN SEMICONDUCTOR DEVICE - A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature. | 03-31-2011 |
| 20110075470 | EMBEDDED SRAM STRUCTURE AND CHIP - An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one. | 03-31-2011 |
| 20110074038 | METHODS FOR FORMING INTERCONNECT STRUCTURES THAT INCLUDE FORMING AIR GAPS BETWEEN CONDUCTIVE STRUCTURES - A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening. | 03-31-2011 |
| 20110069527 | ROM CELL AND ARRAY STRUCTURE - A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cells in the array. An isolation transistor is formed in the elongated continuous active region between the first and second pass transistors and biased in an off state. First and second word lines are coupled to the gates of the pass transistors for applying a reading voltage. The array includes a differential bit line pair including first and second bit lines, a first logic value being encoded into the memory cells by connecting the pass transistors to the first bit line and a second logic value being encoded into the memory cells by connecting the pass transistors to the second bit line. | 03-24-2011 |
| 20110062996 | POWER ON DETECTION CIRCUIT - A power-on-detection (POD) circuit includes first and second comparators, a voltage divider, a detection circuit coupled to a first voltage source node and the voltage divider, and logic circuitry coupled to outputs of the first and second comparators. The detection circuit outputs a control signal identifying if a first voltage source node has a voltage potential that is higher than ground. The control signal turns on and off the first and second comparators, which are respectively coupled to first and second nodes of the voltage divider and to a reference voltage node. The logic circuitry outputs a power identification signal based on the signals received from the outputs of the first and second comparators. | 03-17-2011 |
| 20110062597 | PACKAGE STRUCTURES - A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die. | 03-17-2011 |
| 20110062375 | SILICON WAFER RECLAMATION PROCESS - An etchant for removing a porous low-k dielectric layer on a semiconductor substrate includes a hydrofluoric acid-based solvent, a dilating additive for dilating the pores in the porous low-k dielectric, and a passivating additive that forms a passivation layer at the interface between the low-k dielectric layer and the semiconductor substrate. | 03-17-2011 |
| 20110059604 | METHODS FOR FABRICATING STEP GATE ELECTRODE STRUCTURES FOR FIELD-EFFECT TRANSISTORS - A method is disclosed for forming at least two semiconductor devices with different gate electrode thicknesses. After forming a gate dielectric region, and determining whether a first or second device formed on the gate dielectric region expects a relatively faster gate dopant diffusion rate, a gate electrode layer is formed on the gate dielectric region wherein the gate electrode layer has a step-structure in which a portion thereof for the first device has a relatively larger thickness than that for the second device if the first device has a relatively faster gate dopant diffusion rate. | 03-10-2011 |
| 20110055783 | CODE TILING SCHEME FOR DEEP-SUBMICRON ROM COMPILERS - A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device. | 03-03-2011 |
| 20110051298 | ESD IMPROVEMENT WITH DYNAMIC SUBSTRATE RESISTANCE - In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential. | 03-03-2011 |
| 20110049516 | MULTI-PROJECT WAFER AND METHOD OF MAKING SAME - A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type. | 03-03-2011 |
| 20110042827 | BONDING STRUCTURES AND METHODS OF FORMING BONDING STRUCTURES - A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening. | 02-24-2011 |
| 20110039408 | Semiconductor Device and Fabrication Method Thereof - Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer. | 02-17-2011 |
| 20110035715 | SYSTEM AND METHOD FOR ON-CHIP-VARIATION ANALYSIS - Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library. An adder is provided for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path. A second storage device portion stores a table containing on chip variation (OCV) derating factors. The table is indexed by values of the sum. A total path delay is calculated for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path. | 02-10-2011 |
| 20110033787 | FRAME CELL FOR SHOT LAYOUT FLEXIBILITY - A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count. | 02-10-2011 |
| 20110026308 | CELL STRUCTURE FOR DUAL PORT SRAM - A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region. | 02-03-2011 |
| 20110026289 | CELL STRUCTURE FOR DUAL PORT SRAM - A multi-port SRAM cell includes cross-coupled inverters each including a pull-up transistor and at least a pair of pull down transistors. The SRAM cell includes first and second access ports coupled to first and second word line conductors, each access port including a first pass gate transistor coupled to the data storage node and a second pass gate transistor coupled to the data bar storage node, each pass gate transistor being coupled to a respective bit line conductor, wherein the pull down transistors of the first inverter are formed in a first active region, the pull down transistors of the second inverter are formed in a second active region, the pass gate transistors coupled to the data storage node are formed in a third active region and the pass gate transistors coupled to the data bar storage node are formed in a fourth active region. | 02-03-2011 |
| 20110024908 | LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE - The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer. | 02-03-2011 |
| 20110023002 | DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM - A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC. | 01-27-2011 |
| 20110010117 | APPARATUS FOR NBTI PREDICTION - An apparatus comprises a circuit for measuring a gate leakage current of a plurality of transistors. A circuit is provided to apply heat to gates of the plurality of transistors. A circuit is provided to apply a single stress bias voltage to the plurality of transistors for a stress period t. The stress bias voltage is sufficient to cause a 10% degradation in a drive current of the transistor within the stress period t. A processor is provided for estimating a negative bias temperature instability (NBTI) lifetime τ of the transistor based on a relationship between the gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors. The relationship is determined from data observed while applying the single stress bias voltage. | 01-13-2011 |
| 20110008940 | SELF-ALIGNED V-CHANNEL MOSFET - Forming a high-κ/metal gate field effect transistor using a gate last process in which the channel region has a curved profile thus increasing the effective channel length improves the short channel effect. During the high-κ/metal gate process, after the sacrificial materials between the sidewall spacers are removed, the exposed semiconductor substrate surface at the bottom of the gate trench cavity is etched to form a curved recess. Subsequent deposition of high-κ gate dielectric layer and gate electrode metal into the gate trench cavity completes the high-κ/metal gate field effect transistor having a curved channel region that has a longer effective channel length. | 01-13-2011 |
| 20110006401 | METHOD AND SYSTEM FOR COMBINING PHOTOMASKS TO FORM SEMICONDUCTOR DEVICES - A photomask set includes at least two masks that combine to form a device pattern in a semiconductor device. Orthogonal corners may be produced in a semiconductor device pattern to include one edge defined by a first mask and an orthogonal edge defined by a second mask. The mask set may include a first mask with compensation features and a second mask with void areas overlaying the compensation features when the first and second masks are aligned with one another, such that the compensation features are removed when patterns are successfully formed from the first and second masks. The compensation features alleviate proximity effects during the formation of device features. | 01-13-2011 |
| 20100329061 | ELECTRICAL FUSE CIRCUIT FOR SECURITY APPLICATIONS - A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation. | 12-30-2010 |
| 20100327463 | STACKED STRUCTURES AND METHODS OF FABRICATING STACKED STRUCTURES - A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure. | 12-30-2010 |
| 20100323587 | CHEMICAL MECHANICAL PLANARIZATION METHODS AND APPARATUS - A semiconductor process includes polishing a substrate with a slurry in an enclosure. Polishing the substrate is stopped. First mist is injected into the enclosure, such that the first mist has at least about 80% of saturation of a liquid or gaseous solvent in a carrier within the enclosure. | 12-23-2010 |
| 20100320465 | SEMICONDUCTOR DEVICE WITH MULTI-FUNCTIONAL DIELECTRIC LAYER - A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer. | 12-23-2010 |
| 20100314047 | Etching System - An etching system. An etching chamber includes an exhaust port. A gas input pipe is connected to the etching chamber, inputting etching process gas thereinto. A top RF electrode is disposed above the etching chamber. A bottom RF electrode is disposed under the etching chamber and opposite the top RF electrode. The etching process gas is transformed into plasma by operation of the top and bottom RF electrodes. An exhaust pump is connected to the exhaust port, expelling the plasma from the etching chamber. A base is disposed in the etching chamber. A focus ring is disposed on the base, accommodating a wafer. The wafer is etched by the plasma. A barricade is disposed on the focus ring and corresponds to the exhaust port, regulating the plasma flowing through the wafer. | 12-16-2010 |
| 20100308439 | DUAL WAVELENGTH EXPOSURE METHOD AND SYSTEM FOR SEMICONDUCTOR DEVICE MANUFACTURING - A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength. | 12-09-2010 |
| 20100296722 | FORMATION OF PRESCRIBED PATTERN ON WAFER FOR USE IN SEM DEFECT OFFSET - A prescribed pattern is formed at a plurality of known locations on a semiconductor wafer. The plurality of known locations are incorporated into a defect map that includes a location of at least one defect detected by an in-line inspection of the wafer. The defect map including the plurality of known locations and the location of the at least one defect is transmitted to a scanning electron microscope (SEM). The SEM uses the known locations to calculate a defect offset for use in imaging the at least one defect in the SEM. | 11-25-2010 |
| 20100291840 | SYSTEM AND METHOD FOR CONDITIONING CHEMICAL MECHANICAL POLISHING APPARATUS USING MULTIPLE CONDITIONING DISKS - A chemical mechanical polishing (CMP) apparatus provides for polishing semiconductor wafers and for conditioning the polishing pad of the CMP apparatus using multiple conditioning disks at the same time. The conditioning disks may be moved together or independently along the surface of polishing pad to condition the entire surface of the rotating polishing pad. | 11-18-2010 |
| 20100288369 | Piping System And Control For Semiconductor Processing - A vacuum system for semiconductor fabrication. The system includes a vacuum chamber for performing a semiconductor fabrication process, a vacuum source, and a piping system fluidly connecting the vacuum chamber to the vacuum source. In one embodiment, the piping system is configured without a horizontal flow path section of piping. In some embodiments, the piping system includes a first piping branch and a second piping branch. The first and second piping branches preferably have a symmetrical configuration with respect to the vacuum source. In yet other embodiments, the first and second piping branches preferably each include a throttle valve. | 11-18-2010 |
| 20100285399 | WAFER EDGE EXPOSURE UNIT - A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously. | 11-11-2010 |
| 20100283109 | MOSFET HAVING A CHANNEL MECHANICALLY STRESSED BY AN EPITAXIALLY GROWN, HIGH K STRAIN LAYER - A transistor, such a MOSFET, having an epitaxially grown strain layer disposed over a channel region of a substrate for stressing the channel region to increase the carrier mobility in the channel, and method for making same. The strain layer is composed of a high dielectric constant material. | 11-11-2010 |
| 20100279515 | ATOMIC LAYER DEPOSITION - A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer. | 11-04-2010 |
| 20100278622 | Automated Materials Handling System Having Multiple Categories of Overhead Buffers - An automated materials handling system comprises a plurality of overhead hoist buffers (OHBs) for receiving a plurality of semiconductor wafer carriers. Each OHB is assigned to a respective one of a plurality of categories. Each wafer carrier is associated with one or more of the plurality of categories. Each respective category is associated with at least one of a plurality of event trigger types. An overhead transport (OHT) if provided for transporting each of the plurality of wafer carriers to a respective one of the OHBs in response to a respective trigger event. Each trigger event has one of the plurality of event trigger types. Each wafer carrier is stored in a respective one of the plurality of OHBs assigned to a respective one of the categories associated with the respective event trigger type of the trigger event causing that wafer carrier to be transported and stored. | 11-04-2010 |
| 20100277850 | Multi-Zone Electrostatic Chuck and Chucking Method - A method for processing a semiconductor wafer comprises measuring data indicating an amount of warpage of the wafer. At least two different voltages are determined, based on the amount of warpage. The voltages are to be applied to respective portions of the wafer by an electrostatic chuck that is to hold the wafer. The at least two different voltages are applied to hold the respective portions of the wafer while performing a fabrication process on the wafer. | 11-04-2010 |
| 20100270598 | METHOD FOR FORMING HIGHLY STRAINED SOURCE/DRAIN TRENCHES - A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable I | 10-28-2010 |
| 20100267172 | Formation of Shallow Trench Isolation Using Chemical Vapor Etch - A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first chemical vapor etch (CVE) of the oxide material is performed, to partially form a recess in the STI region. The first CVE removes an amount of the oxide material less than the thickness of the nitride layer. The nitride layer is removed by dry etching. A remaining height of the STI region is measured after removing the nitride. A second CVE of the oxide material in the STI region is performed, based on the measured depth and the remaining height, to form at least one fin having a desired fin height above the oxide in the STI region without an oxide fence. | 10-21-2010 |
| 20100254210 | Multiple-Port SRAM Device - A static random access memory (SRAM) cell having a dedicated read port separated from a write port comprises a first and a second bit-line placed in parallel forming a complimentary bit-line pair for the dedicated read port, a first and second metal line adjacently flanking in both side of and in parallel to the first bit-line, the first and second metal line being formed in the same metal layer as the first bit-line and having a first and second predetermined distance to the first bit-line, respectively, and a third and fourth metal line adjacently flanking in both side of and in parallel to the second bit-line, the third and fourth metal line being formed in the same metal layer as the second bit-line and having a third and fourth predetermined distance to the second bit-line, respectively, wherein the first predetermined distance is equal to the third distance and the second predetermined distance is equal to the fourth distance for keeping the first and second bit-lines having balanced capacitance loading. | 10-07-2010 |
| 20100252907 | Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same - A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed. | 10-07-2010 |
| 20100244879 | APPARATUS FOR MASS DIE TESTING - A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes. | 09-30-2010 |
| 20100234992 | SEMICONDUCTOR WAFER ROBOT ALIGNMENT SYSTEM AND METHOD - A method and system for aligning robotic wafer transfer systems provides a wafer cassette having one or more wafer slots having portions covered with an electrically conductive material and a sensor that is in electrical communication with the electrically conductive material. When a wafer is loaded into a wafer cassette such as may be contained within a wafer transfer module such as a FOUP, an indication of position is delivered to the sensor which detects the alignment and indicates if the loaded wafer undesirably contacts either or both of the opposed grooves that form the wafer slot of the wafer cassette. An indication of the wafer's position may be provided from the sensor to a controller that delivers a signal for aligning the wafer transfer blade of the wafer transfer robot responsive to the signal indicative of position. | 09-16-2010 |
| 20100230816 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions. | 09-16-2010 |
| 20100230815 | SEMICONDUCTOR DEVICE - Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer. | 09-16-2010 |
| 20100230726 | POWER LINE LAYOUT TECHNIQUES FOR INTEGRATED CIRCUITS HAVING MODULAR CELLS - An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block. | 09-16-2010 |
| 20100229383 | WAFER LEVEL TEST PROBE CARD - A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing. | 09-16-2010 |
| 20100224256 | SLURRY SYSTEM FOR SEMICONDUCTOR FABRICATION - A slurry feed system suitable for chemical mechanical planarization (CMP) processes in a semiconductor fabrication facility and related method. The slurry feed system includes a valve manifold box having a discharge piping header fluidly connected to at least one CMP station and a first slurry supply train. The first slurry supply train may include a slurry mixing tank, day tank, and at least two slurry feed pumps arranged in series pumping relationship. The first slurry supply train defines a first slurry piping loop. In one embodiment, a second slurry supply train defining a second slurry piping loop is provided. The valve manifold box is operable to supply slurry from either or both of the first and second slurry piping loops to the CMP station. | 09-09-2010 |
| 20100216287 | METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS - A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards. | 08-26-2010 |
| 20100214547 | METHODS OF DETERMINING QUALITY OF A LIGHT SOURCE - Methods for determining a quality of a light source applied to a photolithographic process are provided. An image sensor array is exposed to a light from a light source. Addresses and respective intensities corresponding to a plurality of locations on a pupil map representing intensity of the light from on the image sensor array. At least one of an inner curve and an outer curve of the pupil map is defined based upon the collected addresses and respective intensities. The light source is applied to a photolithographic process if the addresses have a predetermined pattern relative to the at least one of the inner curve and the outer curve. | 08-26-2010 |
| 20100210189 | SLURRY DISPENSER FOR CHEMICAL MECHANICAL POLISHING (CMP) APPARATUS AND METHOD - A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case. | 08-19-2010 |
| 20100200923 | MULTIPLE-GATE TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING - A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized. | 08-12-2010 |
| 20100194501 | STRUCTURE DESIGN FOR MINIMIZING ON-CHIP INTERCONNECT INDUCTANCE - A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line. | 08-05-2010 |
| 20100190274 | RTP SPIKE ANNEALING FOR SEMICONDUCTOR SUBSTRATE DOPANT ACTIVATION - A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength. | 07-29-2010 |
| 20100190095 | PELLICLE MOUNTING METHOD AND APPARATUS - Apparatus is provided for mounting a pellicle to a photomask. A chamber has at least one port for filling the chamber with extreme clean dry air (XCDA) or an inert gas. A pellicle mounter is provided within the chamber. A vacuum ultra violet (VUV) light source is provided for irradiating a mask held by the pellicle mounter while the chamber is filled with the XCDA or inert gas. The mask is irradiated with the VUV light in an atmosphere of the XCDA or inert gas, and the pellicle is mounted to the mask while the mask is in the atmosphere of the XCDA or inert gas and exposed to the VUV light. | 07-29-2010 |
| 20100187637 | BIPOLAR DEVICE COMPATIBLE WITH CMOS PROCESS TECHNOLOGY - The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate. | 07-29-2010 |
| 20100187444 | FIELD-BY-FIELD LASER ANNEALING AND FEED FORWARD PROCESS CONTROL - A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area. | 07-29-2010 |
| 20100181500 | METHOD AND SYSTEM FOR LOW TEMPERATURE ION IMPLANTATION - A method comprises pre-cooling a first semiconductor wafer outside of a process chamber, from a temperature at or above 15° C. to a temperature below 5° C. The pre-cooled first wafer is placed inside the process chamber after performing the pre-cooling step. A low-temperature ion implantation is performed on the first wafer after placing the first wafer. | 07-22-2010 |
| 20100176306 | IMPLANTATION QUALITY IMPROVEMENT BY XENON/HYDROGEN DILUTION GAS - A method comprises supplying a dopant gas in an arc chamber of an ion source. A dilutant is supplied to dilute the dopant gas. The dilutant comprises about 98.5 wt. % xenon and about 1.5 wt. % hydrogen. An ion beam is generated from the diluted dopant gas using the ion source. | 07-15-2010 |
| 20100174858 | EXTRA HIGH BANDWIDTH MEMORY DIE STACK - A system includes a central processing unit (CPU); a memory device in communication with the CPU, and a direct memory access (DMA) controller in communication with the CPU and the memory device. The memory device includes a plurality of vertically stacked chips and a plurality of input/output (I/O) ports. Each of the I/O ports connected to at least one of the plurality of chips through a through silicon via. The DMA controller is configured to manage to transfer of data to and from the memory device. | 07-08-2010 |
| 20100173499 | LOW K DIELECTRIC SURFACE DAMAGE CONTROL - A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma. | 07-08-2010 |
| 20100167506 | INDUCTIVE PLASMA DOPING - In some embodiments, a method of doping a semiconductor wafer disposed on a pedestal electrode in an inductive plasma chamber includes generating a plasma having a first voltage with respect to ground in the inductive plasma chamber, and applying a radio frequency (RF) voltage with respect to ground to the pedestal electrode in the inductive plasma chamber. The positive RF voltage is based on the first voltage of the plasma. | 07-01-2010 |
| 20100164667 | ON-CHIP TRANSFORMER BALUN STRUCTURES - An electronic device includes a first winding having a first port and a second port. The first winding formed in a first metal layer. A second winding has a third port and a fourth port. The second winding includes a plurality of segments formed in the first metal layer. The second plurality of winding segments are connected by a bridge formed in a second metal layer. The first and second ports of the first winding are connected to the inner-portion of the first winding. | 07-01-2010 |
| 20100164050 | ROBUST STRUCTURE FOR HVPW SCHOTTKY DIODE - A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring. | 07-01-2010 |
| 20100163078 | SPINNER AND METHOD OF CLEANING SUBSTRATE USING THE SPINNER - A method includes spinning a semiconductor wafer about an axis normal to a major surface of the wafer. The wafer is translated in a direction parallel to the major surface with an oscillatory motion, while spinning the wafer. A material is sprayed from first and second nozzles or orifices at respective first and second locations on the major surface of the wafer simultaneously while spinning the wafer and translating the wafer. | 07-01-2010 |
| 20100151615 | METHODS FOR FABRICATING IMAGE SENSOR DEVICES - Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer. | 06-17-2010 |
| 20100143082 | PORTABLE STOCKER AND METHOD OF USING SAME - A system comprising a conveyor. A semiconductor processing tool has a lifter port. The tool is positioned near the conveyor, such that the lifter port is configured to transport a Front Opening Unified Pod (FOUP) between the conveyor and the lifter port. An upstream stocker and a downstream stocker are both co-located with the conveyor and the tool. The upstream and downstream stockers each have a respective storage space for the FOUP and a respective robotic device configured to transport the FOUP between its respective storage space and the conveyor. The upstream stocker is configured to receive the FOUP from an overhead transport (OHT) and deliver the FOUP to the conveyor. The downstream stocker is configured to receive the FOUP from the conveyor and deliver the FOUP to the OHT. | 06-10-2010 |
| 20100136779 | Sidewall SONOS Gate Structure with Dual-Thickness Oxide and Method of Fabricating the Same - A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively. | 06-03-2010 |
| 20100123135 | PAD STRUCTURE AND METHOD OF TESTING - An interconnect structure includes: a plurality of dielectric layers having aligned process control monitor (PCM) pads, and a conductive structure above a topmost one of the PCM pads. The conductive structure electrically connects the topmost PCM pad to a device under test above a level of the topmost PCM pad. The conductive structure is sized and shaped so as to leave a majority portion of the topmost PCM pad exposed for access by a test probe. | 05-20-2010 |
| 20100119958 | MASK BLANK, MASK FORMED FROM THE BLANK, AND METHOD OF FORMING A MASK - A mask for manufacturing a semiconductor device comprises a transparent substrate. A metal-containing layer overlies the transparent substrate in a first region. A capping layer overlies and is coextensive with the metal-containing layer without wrapping around side edges of the metal-containing layer. The capping layer is substantially free of nitride. The transparent substrate has a second region separate from the first region. The transparent substrate is exposed in the second region. | 05-13-2010 |
| 20100117080 | SEMICONDUCTOR TEST PAD STRUCTURES - A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer. | 05-13-2010 |
| 20100116709 | VENTILATED FRONT-OPENING UNIFIED POD - An improved substrate transport pod for storing or transporting semiconductor wafer substrates during semiconductor wafer processing has a main body defined by a plurality of side panels. A substantial portion of at least one of the side panels being formed of a semi-permeable membrane allowing any corrosive gas molecules introduced to the interior of the pod to diffuse out of the transport pod through the semi-permeable membrane while preventing particulate contaminants from entering the transport pod. | 05-13-2010 |
| 20100108104 | JETSPRAY NOZZLE AND METHOD FOR CLEANING PHOTO MASKS AND SEMICONDUCTOR WAFERS - A jetspray nozzle for cleaning a photolithographic mask or semiconductor wafer and method for cleaning the same. The jetspray nozzle in one embodiment includes a water supply inlet, a gas supply inlet, a first row of gas injection nozzles communicating with the gas supply inlet, a mixing cavity defining a jetspray nozzle outlet, and a flow mixing baffle disposed in the cavity. The mixing baffle preferably is configured and arranged to combine gas and water in the jetspray nozzle for delivering a concentrated stream of gas with a cluster of micro water droplets entrained in the gas for removing contaminant particles from the mask. The jetspray nozzle is capable of cleaning photo masks or wafers without the use of chemicals. In one embodiment, the water may be deionized water and the gas may be nitrogen. In another embodiment, the jetspray nozzle further includes a second row of gas injection nozzles spaced above or below the first row of gas injection nozzles that communicate with the gas supply inlet. | 05-06-2010 |
| 20100093135 | STRATIFIED UNDERFILL METHOD FOR AN IC PACKAGE - A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board. | 04-15-2010 |
| 20100080045 | ROBUST 8T SRAM CELL - This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line. | 04-01-2010 |
| 20100072632 | BOND PAD STRUCTURE HAVING DUMMY PLUGS AND/OR PATTERNS FORMED THEREAROUND - A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength. | 03-25-2010 |
| 20100072553 | METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE - A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film. | 03-25-2010 |
| 20100068656 | HIGH ETCH RESISTANT MATERIAL FOR DOUBLE PATTERNING - The present invention includes a lithography method comprising forming a first patterned insist layer including at least one opening therein over a substrate. A water-soluble polymer layer is formed over the first patterned resist layer and the substrate, whereby a reaction occurs at the interface of the first patterned resist layer and the water-soluble polymer layer. The non-reacted water-soluble polymer layer is removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer or abuts at least one portion of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask. | 03-18-2010 |
| 20100065944 | SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR DESIGN - An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors. | 03-18-2010 |
| 20100065921 | SEMICONDUCTOR DEVICE WITH LOCAL INTERCONNECTS - A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the substrate on both sides of the first gate line structure and a second pair of source/drain regions is formed in the substrate on both sides of the second gate line structure. A pair of conductive lines is disposed on the substrate on both sides of the first gate line structure and the second gate line structure, such that each conductive line is connected to one of the first pair of source/drain regions and one of the second pair of source/drain regions. | 03-18-2010 |
| 20100062693 | TWO STEP METHOD AND APPARATUS FOR POLISHING METAL AND OTHER FILMS IN SEMICONDUCTOR MANUFACTURING - A method and apparatus for removing a metal or conductive film from over a surface of a semiconductor wafer provides a two step process carried out within a single wafer processing apparatus. A first step is a wet chemical or mechanical removal process that removes an upper portion of the film at a high removal rate and is followed by a second step of a lower removal rate, the second step being CMP, chemical mechanical polishing. | 03-11-2010 |
| 20100058267 | PLACE-AND-ROUTE LAYOUT METHOD WITH SAME FOOTPRINT CELLS - This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof. | 03-04-2010 |
| 20100055897 | WET CLEANING STRIPPING OF ETCH RESIDUE AFTER TRENCH AND VIA OPENING FORMATION IN DUAL DAMASCENE PROCESS - After trench line pattern openings and via pattern openings are formed in a inter-metal dielectric insulation layer of a semiconductor wafer using trench-first dual damascene process, the wafer is wet cleaned in a single step wet clean process using a novel wet clean solvent composition. The wet clean solvent effectively cleans the dry etch residue from the plasma etching of the dual damascene openings, etches back the TiN hard mask layer along the dual damascene openings and forms a recessed surface at the conductor metal from layer below exposed at the bottom of the via openings of the dual damascene openings. | 03-04-2010 |
| 20100055846 | SEMICONDUCTOR PACKAGE STRUCTURES - A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. | 03-04-2010 |
| 20100051581 | PLASMA CLEANING FOR PROCESS CHAMBER COMPONENT REFURBISHMENT - A method for cleaning and refurbishing a chamber component includes placing a chamber component having process deposits on an exterior surface in a plasma vapor deposition chamber. The chamber component is bombarded with a plasma comprising Argon for a period of time sufficient to remove the process deposits from the exterior surface of the chamber component. | 03-04-2010 |
| 20100041194 | SEMICONDUCTOR DEVICE WITH SPLIT GATE MEMORY CELL AND FABRICATION METHOD THEREOF - A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell. | 02-18-2010 |
| 20100013020 | Semiconductor device with semi-insulating substrate portions - A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles. | 01-21-2010 |
| 20100009506 | DOPANT IMPLANTATION METHOD AND INTEGRATED CIRCUITS FORMED THEREBY - A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration. | 01-14-2010 |
| 20100008014 | METHOD AND APPARATUS FOR SUCURELY DECHUCKING WAFERS - A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a controller for receiving the variable quantity; and a regulating means coupled to the driving means and to the controller, the regulating means for controlling the variable quantity going to the driving means when a predetermined variable quantity is detected. | 01-14-2010 |
| 20100008013 | METHOD AND APPARATUS FOR SAFELY DECHUCKING WAFERS - A wafer stage installed in a process chamber for safely dechucking a wafer is provided. In one embodiment, the wafer stage comprises: a chuck support for supporting a chuck; a chuck mounted on the chuck support for receiving and attaching a wafer thereto; a support lift means for supporting the wafer; a driving means coupled to the support lift means for gradually raising the support lift means to contact the wafer in response to a variable quantity; a sensor attached to the driving means for detecting a change in the variable quantity; and a controller for controlling the variable quantity to the driving means when a predetermined variable quantity is detected in comparison to the change in the variable quantity for a predetermined time. | 01-14-2010 |
| 20090298256 | SEMICONDUCTOR INTERCONNECT AIR GAP FORMATION PROCESS - A semiconductor package including an interconnect air gap and method for making the same. The semiconductor package includes a dielectric layer, a metallic interconnect, an air gap disposed between the dielectric layer and interconnect, and a spacer interspersed between the metallic interconnect and air gap. The metallic interconnect is laterally supported by and isolated from the air gap by the spacer. A method for making the same is also provided. | 12-03-2009 |
| 20090283841 | SCHOTTKY DEVICE - An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer. | 11-19-2009 |
| 20090275278 | ULTRA-PURE AIR SYSTEM FOR NANO WAFER ENVIRONMENT - In one embodiment, an air filtration system includes a first ventilation path connected between at least one external air supply and a clean room. The first ventilation path is configured to direct air from the at least one external air supply to the clean room. A second ventilation path is connected to the clean room. The second ventilation path is configured to recirculate air in the clean room. A third ventilation path, separate from the first path, is connected between the at least one external air supply and a tool environment disposed within the clean room. The third ventilation path includes an ultra-pure air filtration unit disposed between the outdoor air supply and the tool environment. The ultra-pure air filtration unit includes a compressor and a dryer. | 11-05-2009 |
| 20090271019 | SYSTEM AND METHOD OF DEMAND AND CAPACITY MANAGEMENT - Systems of demand and capacity management with machine-time accuracy are provided. The system includes an allocation planning module, an order management module, a capacity model, and a capacity management module. The allocation planning module receives a demand plan for a product. The capacity management module transforms the demand plan into a machine-time-based plan according to the capacity model, and reserves capacity according to the machine-time-based plan for the demand plan. The capacity management module further transforms a purchase order received by the order management module before a cutoff date for the product into a machine-time-based order, accepts the machine-time-based order and decreases the reservation capacity depending on the machine-time-based plan. | 10-29-2009 |
| 20090263214 | FIXTURE FOR P-THROUGH SILICON VIA ASSEMBLY - A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps. | 10-22-2009 |
| 20090233447 | CONTROL WAFER RECLAMATION PROCESS - A method of recycling a control wafer having a dielectric layer deposited thereon involves removing most of the dielectric layer by plasma etching leaving a residual film of the dielectric and then removing the residual dielectric film by a wet etching process. The combination of the dry and wet etching provides effective removal of the dielectric material without damaging the wafer substrate and any residual wet etching byproduct particulate remaining on the wafer substrate is then removed by APM cleaning and scrubbing. | 09-17-2009 |
| 20090233402 | WAFER LEVEL IC ASSEMBLY METHOD - A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced. | 09-17-2009 |
| 20090218693 | LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE - A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers. | 09-03-2009 |
| 20090203217 | NOVEL SELF-ALIGNED ETCH METHOD FOR PATTERNING SMALL CRITICAL DIMENSIONS - A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O | 08-13-2009 |
| 20090200549 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate and a first wiring layer overlying the substrate. The first wiring layer comprises a first wiring area surrounded by a first seal ring. The first seal ring comprises a first monitor circuit isolated by a first dielectric layer embedded in the first seal ring. The first monitor circuit is responsive to a predetermined amount of deformation occurs in the third dielectric layer. | 08-13-2009 |
| 20090189233 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING SAME - An optical image sensor is fabricated by forming a pixel array and a peripheral region surrounding the pixel array on a semiconductor substrate, the peripheral region containing peripheral circuitry. An inter-level-dielectric layer is formed over the substrate and a plurality of interconnect wiring layers are formed over the inter-level-dielectric layer. Each interconnect wiring layer includes interconnecting metal features and a layer of inter-level-dielectric material covering the interconnecting metal features. The plurality of interconnect wiring layers are provided in a manner that there are N levels of wiring layers in the peripheral region and 1 to (N−1) levels of wiring layers over the pixel array. An etch-stop layer is formed over the top-most level interconnecting metal features in the peripheral region. | 07-30-2009 |
| 20090188104 | Method of Manufacturing a Coil Inductor - A method of manufacturing a coil inductor and a coil inductor are provided are provided. A plurality of conductive bottom structures are formed to be lying on a first dielectric layer. A plurality pairs of conductive side structures are then formed, wherein each pair of the conductive side structure stand on top surface of a first end and a second end of each conductive bottom structure respectively; a second dielectric layer is formed on the first dielectric layer, coating the bottom and side structures; and a plurality of conductive top structures are formed to be lying on the second dielectric layer, wherein each conductive top structure electrically connects each pair of the conductive side structures, wherein the conductive bottom structures, the conductive side structures and the conductive top structures together form a conductive coil structure. | 07-30-2009 |
| 20090174487 | VOLTAGE-CONTROL OSCILLATOR CIRCUITS WITH COMBINED MOS AND BIPOLAR DEVICE - A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor. | 07-09-2009 |
| 20090166817 | EXTREME LOW-K DIELECTRIC FILM SCHEME FOR ADVANCED INTERCONNECTS - An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer. | 07-02-2009 |
| 20090160024 | VERTICAL RESISTORS AND BAND-GAP VOLTAGE REFERENCE CIRCUITS - A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias. | 06-25-2009 |
| 20090157455 | INSTRUCTION SYSTEM AND METHOD FOR EQUIPMENT PROBLEM SOLVING - A method and system of providing instructions in addressing an equipment problem are provided. An indication of an equipment problem is checked against a solution database to identify at least one suggested solution to the equipment problem. A suggested solution from the at least one suggested solution is provided. An actual fix solution implemented in association with the equipment problem is recorded. | 06-18-2009 |
| 20090142860 | SYSTEM AND METHOD FOR ENHANCED CONTROL OF COPPER TRENCH SHEET RESISTANCE UNIFORMITY - A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches. | 06-04-2009 |
| 20090140393 | WAFER SCRIBE LINE STRUCTURE FOR IMPROVING IC RELIABILITY - A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation. | 06-04-2009 |
| 20090140391 | Seal Ring in Semiconductor Device - A semiconductor device includes a first circuit, a first seal ring and at least one first notch. The first seal ring surrounds the first circuit. The first notch cuts the first seal ring. Specifically, the first notch includes an inner opening, an outer opening and a connecting groove. The inner opening is located on the inner side of the first seal ring. The outer opening is located on the outer side of the first seal ring. The outer opening and the inner opening are not aligned. The connecting groove connects the inner opening and the outer opening. | 06-04-2009 |
| 20090140383 | METHOD OF CREATING SPIRAL INDUCTOR HAVING HIGH Q VALUE - A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV). Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface thereof. | 06-04-2009 |
| 20090137119 | NOVEL SEAL ISOLATION LINER FOR USE IN CONTACT HOLE FORMATION - A method is disclosed for etching a contact hole in a stack of dielectric layers. The method minimizes bridging defects between the contact hole and adjacent conductive structures. A substrate has a conductive material layer and an active device disposed thereon. An etch stop layer covers the device and the conductive material, A layer of interlevel dielectric and antireflective coating layers are then provided. A hole is etched through the stack using patterned photoresist. Ashing is used to remove all but the etch stop layer and the interlevel dielectric layer. An isolation liner is deposited over the interlevel dielectric layer, the sidewall surfaces of the hole and the exposed upper surface of the etch stop layer. Another etch removes the isolation liner disposed over the exposed upper surface of the etch stop layer, and removes the underlying etch stop layer to expose an upper surface of the conductive material layer. | 05-28-2009 |
| 20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 05-21-2009 |
| 20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 05-14-2009 |
| 20090117731 | SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME - A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening. | 05-07-2009 |
| 20090111269 | SILICON WAFER RECLAMATION PROCESS - By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant. | 04-30-2009 |
| 20090111208 | COLORS ONLY PROCESS TO REDUCE PACKAGE YIELD LOSS - Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses. | 04-30-2009 |
| 20090108365 | HIGH-K DIELECTRIC METAL GATE DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A metal gate/high-k dielectric semiconductor device provides an NMOS gate structure and a PMOS gate structure formed on a semiconductor substrate. The NMOS gate structure includes a high-k gate dielectric treated with a dopant impurity such as La and the high-k gate dielectric material of the PMOS gate structure is deficient of this dopant impurity and further includes a work function tuning layer over the high-k gate dielectric. A process for simultaneously forming the NMOS and PMOS gate structures includes forming the high-k gate dielectric material, and the work function tuning layer thereover, then selectively removing the work function tuning layer from the NMOS region and carrying out a plasma treatment to selectively dope the high-k gate dielectric material in the NMOS region with a dopant impurity while the high-k gate dielectric in the PMOS region is substantially free of the dopant impurity. | 04-30-2009 |
| 20090104547 | IMAGE SENSOR - A method is provided for processing a substrate. The substrate has at least one filter region, a plurality of bond pads, and a plurality of scribe lines arranged around the filter region and bond pads. A first planarization layer is formed above the substrate. The planarization layer has a substantially flat top surface overlying the filter region, the bond pads and the scribe lines. At least one color resist layer is formed over the first planarization layer and within the filter region while the first planarization layer covers the bond pads and the scribe lines. | 04-23-2009 |
| 20090101937 | NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION - The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices. | 04-23-2009 |
| 20090087955 | METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS - A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards. | 04-02-2009 |
| 20090087929 | METHOD AND SYSTEM FOR IMPROVING WET CHEMICAL BATH PROCESS STABILITY AND PRODUCTIVITY IN SEMICONDUCTOR MANUFACTURING - A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing. | 04-02-2009 |
| 20090087287 | APPARATUS AND METHOD FOR SEMICONDUCTOR WAFER TRANSFER - An apparatus for semiconductor wafer transfer comprises a first region for placement of a pod, a second region for placement of a cassette, an unloading mechanism, and a transferring mechanism for transferring wafers in the unloaded pod to the cassette horizontally. In an embodiment, the pod is unloaded by lifting the housing of the pod, and preferably the apparatus for movement of semiconductor wafers further comprises a carrying mechanism for moving the cassette toward the pod, so that the cassette can be closer to the pod for smoothing wafer transfer. | 04-02-2009 |
| 20090085112 | LATERAL DIFFUSION METAL-OXIDE-SEMICONDUCTOR STRUCTURE - A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms. | 04-02-2009 |
| 20090081862 | AIR GAP STRUCTURE DESIGN FOR ADVANCED INTEGRATED CIRCUIT TECHNOLOGY - A method for forming air gaps between interconnect structures in semiconductor devices provides a sacrificial layer formed over a dielectric and within openings formed therein. The sacrificial layer is a blanket layer that is converted to a material that is consumable in an etchant composition that the dielectric material and a subsequently formed interconnect material are resistant to. After the interconnect material is deposited a planarized surface including portions of the dielectric material, vertical sections of the converted material and portions of the interconnect material is produced. The etchant composition then removes the converted material thereby forming voids. A capping layer is formed over the structure resulting in air gaps. A sidewall protection layer may be optionally formed between the interconnect structure and the sacrificial material. In some embodiments an ARC layer may be formed over the dielectric and form part of the planar surface. | 03-26-2009 |
| 20090067105 | ESD PROTECTION CIRCUIT AND METHOD - A system includes a driving device operating at first supply voltage V | 03-12-2009 |
| 20090062956 | METHOD AND STRUCTURE FOR AUTOMATED INERT GAS CHARGING IN A RETICLE STOCKER - At least a first reticle is stored in a housing of a stocker. A first gas is delivered to the housing. At least one reticle pod having an additional reticle is delivered into a enclosure within the housing of the stocker. A second gas different from the first gas is delivered to the enclosure. The reticle pod is automatically retrieved from the enclosure. The delivery and retrieval of the reticle pod and delivery of the first gas and the second gas are automatically controlled. | 03-05-2009 |
| 20090058434 | METHOD FOR MEASURING A PROPERTY OF INTERCONNECTIONS AND STRUCTURE FOR THE SAME - A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad. | 03-05-2009 |
