| SYNOPSYS, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120137261 | METHOD AND APPARATUS FOR DETERMINING MASK LAYOUTS FOR A SPACER-IS-DIELECTRIC SELF-ALIGNED DOUBLE-PATTERNING PROCESS - Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged. | 05-31-2012 |
| 20120136635 | METHOD AND APPARATUS FOR OPTIMIZING CONSTRAINT SOLVING THROUGH CONSTRAINT REWRITING AND DECISION REORDERING - Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints. | 05-31-2012 |
| 20120131531 | Reducing Leakage Power in Integrated Circuit Designs - A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values. | 05-24-2012 |
| 20120131527 | TARGETED PRODUCTION CONTROL USING MULTIVARIATE ANALYSIS OF DESIGN MARGINALITIES - Targeted production control using multivariate analysis of design marginalities. A list of a plurality of metrology operations is accessed during production of an integrated circuit device. The list is generated from operations performed in the design of the integrated circuit device. At least one of the plurality of metrology operations is performed on the integrated circuit device. A manufacturing process of the integrated circuit device may be adjusted responsive to results of the performing. | 05-24-2012 |
| 20120131525 | METHOD AND APPARATUS FOR FIXING DESIGN REQUIREMENT VIOLATIONS IN MULTIPLE MULTI-CORNER MULTI-MODE SCENARIOS - Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one or more design requirement violations, which can involve estimating parameter values for circuit objects in multiple scenarios using parameter values stored in the scenario image and the multi-scenario ECO database. | 05-24-2012 |
| 20120124588 | Generating Hardware Accelerators and Processor Offloads - System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention. | 05-17-2012 |
| 20120123763 | METHOD AND APPARATUS FOR EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION - One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance. | 05-17-2012 |
| 20120106688 | Data Recovery Architecture (CDR) For Low-Voltage Differential Signaling (LVDS) Video Transceiver Applications - The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links. | 05-03-2012 |
| 20120101798 | EFFICIENT CLOCK MODELS AND THEIR USE IN SIMULATION - Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used. | 04-26-2012 |
| 20120099380 | PFET Nonvolatile Memory - A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon. | 04-26-2012 |
| 20120086498 | HIGH-VOLTAGE SWITCH USING THREE FETS - Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal. | 04-12-2012 |
| 20120086068 | METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES - A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate. | 04-12-2012 |
| 20120084847 | Secure Provisioning of Resources in Cloud Infrastructure - Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. The provisioning of resources is handled by a cloud provisioning system that is generally operated and maintained by an EDA tool developer using a provisioning credential. After the resources are provisioned, the cloud provisioning system places user key on the provisioned resources. Once the user key is placed on the provisioned resources, the cloud provisioning system has only limited access or no access to the provisioned resources. Instead, a user client device takes over the control of the provisioned resources by using a user's access credential. The provisioning credential is retained by the EDA tool developer and is not released to the user. Similarly, the access credential is retained by the user and not released to the EDA tool developer. In this way, the EDA tool developer can retain control of the resources deployed for the EDA tasks while ensuring that the user's information associated with the EDA tasks is secure. | 04-05-2012 |
| 20120079441 | Nonlinear Approach to Scaling Circuit Behaviors for Electronic Design Automation - Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based on the data and operating conditions in the library set. These parameters and nonlinear transforms can then be used to scale circuit behaviors to operating points not contained in the library set. | 03-29-2012 |
| 20120072879 | Method and Apparatus for Synthesis of Multimode X-Tolerant Compressor - Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described. | 03-22-2012 |
| 20120072876 | METHOD AND APPARATUS FOR REDUCING X-PESSIMISM IN GATE-LEVEL SIMULATION AND VERIFICATION - Methods and apparatuses are described for reducing or eliminating X-pessimism in gate-level simulation and/or formal verification. A system can identify a set of reconvergent inputs of a combinational block in a gate-level design. Next, the system can determine whether or not the combinational block is expected to exhibit X-pessimism during gate-level simulation. If the combinational block is expected to exhibit X-pessimism during gate-level simulation, the system can modify the gate-level design to reduce X-pessimism during gate-level simulation. In some embodiments, the system can build a model for the gate-level design by using unique free input variables to represent sources of indeterminate values. The system can then use the model to perform formal verification. | 03-22-2012 |
| 20120066656 | Parallel Parasitic Processing In Static Timing Analysis - A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process. | 03-15-2012 |
| 20120060169 | SYSTEMS AND METHODS FOR RESOURCE CONTROLLING - A resource controller that includes a first buffer configured to store requests of a first predefined category having a first priority. In addition, the resource controller includes at least a second buffer configured to store requests of a second predefined category having a second priority where the first priority is set such that processing requests of the first category has priority over processing the requests of the second category. Also, the resource controller includes a mechanism configured to block the requests of the first category when a predefined condition is met. | 03-08-2012 |
| 20120060132 | Non-Linear Rasterized Contour Filters - A system includes a conversion module that preserves the shape of a contour when converting an image to a different resolution. The conversion module receives a first image and divides the first image into regions of pixel values. For each region, a contribution of the region to the pixel values in the second image is determined. The contribution is selected from a set of pre-determined contributions that are a nonlinear function of the values in the region, and the selection is made based at least in part on the values in the region. The contributions are accumulated together to generate a second image. The conversion module may be, for example, part of a design flow for an integrated circuit that connects a mask simulation stage with an optical simulation stage. | 03-08-2012 |
| 20120041984 | Group Management Using Unix NIS Groups - In one implementation, a system for managing Groups in a Unix environment includes a group management engine and an NIS converter. A group information database stores information about Groups and their Members. The group management engine receives commands from Administrators of a Group to change attributes of Members in the Group. It accesses the database and makes the requested changes. The information in the database is not in an NIS-compatible format. The NIS converter accesses the database and generates an NIS group file that describes a Group and its Members in a format that is NIS-compatible. For example, the NIS group file can be incorporated into the master NIS group map using the | 02-16-2012 |
| 20120036488 | Method and Apparatus for Automatic Relative Placement Rule Generation - Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level. | 02-09-2012 |
| 20120030642 | HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION - Some embodiments of the present invention provide techniques and systems for performing aggressive and dynamic scenario reduction during different phases of optimization, e.g., during delay, area, leakage and DRC (design rule check) optimization. Specifically, essential scenarios at gates and timing end-points can be identified and then used during the dynamic scenario reduction process. In some embodiments, margin values associated with various constraints can be used to determine the set of essential scenarios to account for constrained objects that are near critical in addition to the constrained objects that are the worst violators. In some embodiments, at any point during the optimization process, only the set of essential scenarios are kept active, thereby substantially reducing runtime and memory requirements without compromising on the quality of results. | 02-02-2012 |
| 20120030641 | PERFORMING SCENARIO REDUCTION USING A DOMINANCE RELATION ON A SET OF CORNERS - Some embodiments of the present invention provide techniques and systems for performing scenario reduction using a dominance relation on a set of corners. During operation, the system can receive a design library which specifies gate characteristics at each corner in a set of corners. Next, the system can use the design library to determine a dominance relation on the set of corners for each gate type. The dominance relations can be stored with the design library. The system can then receive a set of scenarios over which a circuit design is to be optimized. Next, the system can determine a subset of the set of scenarios using one or more dominance relations on the set of corners. The system can then optimize the circuit design over the subset of the set of scenarios. | 02-02-2012 |
| 20120019224 | DC-DC Converter - A dual-mode switching voltage regulator has a duty cycle that varies with the input and output voltages so as to dynamically compensate for changes in the operating conditions. The switching voltage regulator uses input and output voltages/currents to optimize the duty cycle of the signals applied to a pair of switches disposed in the regulator. In the PFM mode, a control block senses the time that a first switch used to discharge an inductor is turned off. If the control block senses that the first switch is opened too early, the control block increases the on-time of a second switch used to charge the inductor. If the control block senses that the first switch is opened too late, the control block decreases the on-time of the second switch. | 01-26-2012 |
| 20120011479 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 01-12-2012 |
| 20110311009 | PATTERN AGNOSTIC ON-DIE SCOPE - An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream. | 12-22-2011 |
| 20110310947 | METHOD AND APPARATUS FOR PERFORMING ADAPTIVE EQUALIZATION - Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value. | 12-22-2011 |
| 20110310942 | HIGHLY FLEXIBLE FRACTIONAL N FREQUENCY SYNTHESIZER - One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f | 12-22-2011 |
| 20110309857 | CIRCUITRY FOR MATCHING THE UP AND DOWN IMPEDANCES OF A VOLTAGE-MODE TRANSMITTER - Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance. | 12-22-2011 |
| 20110307850 | RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 12-15-2011 |
| 20110307722 | REDUCING POWER CONSUMPTION IN CLOCK AND DATA RECOVERY SYSTEMS - Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system. | 12-15-2011 |
| 20110307226 | Efficient Data Compression For Vector-Based Static Timing Analysis - In a STA method, after accessing data sets regarding the IC, vectors of the data sets for STA can be generated. Each vector can include a base value and a plurality of tokens, wherein each token is quantized. For each vector, the data of the vector can be adjusted. Adjusting can include shifting a predetermined token to zero and adjusting the base value and remaining token values based on the shifting. Incremental compression can be applied within the vector by storing each token value as a difference versus its previous token value. Differential compression can then be applied by storing each token value as a difference versus a corresponding token value in a predetermined reference vector. A resulting vector can be stored. At this point, an operation for STA can be performed using multiple resulting vectors without de-quantizing or decompressing. | 12-15-2011 |
| 20110302547 | METHOD AND APPARATUS FOR USING SCENARIO REDUCTION IN A CIRCUIT DESIGN FLOW - Some embodiments of the present invention provide techniques and systems for using scenario reduction in a design flow. The system can use scenario reduction to determine two subsets of scenarios that correspond to two sets of design constraints. Next, the system can optimize the circuit design using one of the sets of design constraints over the associated subset of scenarios. Next, the system can optimize the circuit design using both sets of design constraints over the union of the two subsets of scenarios. In some embodiments, the system can iteratively optimize a circuit design by: performing multiple optimization iterations on the circuit design over progressively larger subsets of scenarios which are determined by performing scenario reduction with relaxation; and performing at least one optimization iteration on the circuit design over a subset of scenarios which is determined by performing scenario reduction without relaxation. | 12-08-2011 |
| 20110302546 | METHOD AND APPARATUS FOR PERFORMING SCENARIO REDUCTION - Some embodiments of the present invention provide techniques and systems for reducing the number of scenarios over which a circuit design is optimized. Each scenario in the set of scenarios can be associated with a process corner, an operating condition, and/or an operating mode. During operation, the system can receive a set of scenarios over which the circuit design is to be optimized. Next, the system can compute values of constrained objects in the circuit design over the set of scenarios. The system can then determine a subset of scenarios based at least on the values of the constrained objects, so that if the circuit design meets design constraints in each scenario in the subset of scenarios, the circuit design is expected to meet the design constraints in each scenario in the set of scenarios. | 12-08-2011 |
| 20110302452 | CIRCUITRY TO FACILITATE TESTING OF SERIAL INTERFACES - Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data. | 12-08-2011 |
| 20110301907 | Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization - Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention evaluates the design prior to the implementation of the compression IP so that it can define the configuration of DFT and ATPG to maximize the results of compression as measured by test data volume and test application time. | 12-08-2011 |
| 20110298051 | Electrostatic Discharge Management Apparatus, Systems, and Methods - Apparatus, systems, and methods may include managing electrostatic discharge events by using a semiconductor device having a non-aligned gate to implement a snap-back voltage protection mechanism. Such devices may be formed by doping a semiconductor substrate to form a first conductive region as a well, forming one of a source region and a drain region in the well, depositing a layer of polysilicon on the substrate to establish a gating area that does not overlap the one of the source region and the drain region, and forming an integrated circuit supported by the substrate to couple to the one of the source region and the drain region to provide snap-back voltage operation at a node between the integrated circuit and the source or drain region. Additional apparatus, systems, and methods are disclosed. | 12-08-2011 |
| 20110296364 | METHOD AND APPARATUS FOR CUSTOM MODULE GENERATION - Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one processor to generate one or more custom implementations of the circuit module from the nominal implementation. The system can then use the one or more custom implementations of the circuit module in the layout. | 12-01-2011 |
| 20110292990 | MULTIPLE-INPUT, ON-CHIP OSCILLOSCOPE - An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data. | 12-01-2011 |
| 20110289464 | GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT - Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate. | 11-24-2011 |
| 20110283246 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data - An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model. | 11-17-2011 |
| 20110276947 | CONTEXT-BASED EVALUATION OF EQUATIONS - Some embodiments provide a system that facilitates the evaluation of an equation. During operation, the system obtains one or more data-access functions to be used in the equation. Next, the system obtains an analysis context for the equation separately from the data-access functions. The analysis context may include one or more analysis parameters that specify one or more data sources and/or types of analysis to be used in evaluating the equation. Finally, the system evaluates the equation using the data-access functions and the data sources. | 11-10-2011 |
| 20110276934 | FORMAL EQUIVALENCE CHECKING BETWEEN TWO MODELS OF A CIRCUIT DESIGN USING CHECKPOINTS - Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems. | 11-10-2011 |
| 20110258503 | Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques - Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods. | 10-20-2011 |
| 20110258498 | Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry - A test architecture is described that adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. | 10-20-2011 |
| 20110255348 | Non-Volatile Memory Cell with BTBT Programming - A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read transistor. | 10-20-2011 |
| 20110252393 | AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS - Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes. | 10-13-2011 |
| 20110252390 | AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRCUITS - Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes. | 10-13-2011 |
| 20110252388 | COMPARING TIMING CONSTRAINTS OF CIRCUITS - Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes. | 10-13-2011 |
| 20110246997 | ROUTING AND DELIVERY OF DATA FOR ELECTRONIC DESIGN AUTOMATION WORKLOADS IN GEOGRAPHICALLY DISTRIBUTED CLOUDS - Electronic design automation (EDA) libraries are delivered using a geographically distributed private cloud including EDA design centers and EDA library stores. EDA projects associated with an EDA library are determined by matching information describing the EDA library with information describing the projects. A set of design centers hosting the projects is determined. A data delivery model is determined for transmitting the EDA library to the design centers. The EDA library is scheduled for delivery to the design centers based on a deadline associated with a project stage that requires the EDA library. Network links with specialized hardware for transmitting data are determined in the private cloud by measuring their deterioration in performance on increase of data transmission load. These links are used for delivering EDA libraries expected to be used urgently for a stage of an EDA project. | 10-06-2011 |
| 20110246653 | EFFICIENT PROVISIONING OF RESOURCES IN PUBLIC INFRASTRUCTURE FOR ELECTRONIC DESIGN AUTOMATION (EDA) TASKS - Provisioning resources in public cloud infrastructure to perform at least part of electronic design automation (EDA) tasks on the public cloud infrastructure. Performance metrics of servers in the public cloud infrastructure and performance history of a user's past EDA tasks are maintained to estimate operation parameters such as runtime of a new EDA task. Based on the estimation, a user can provision appropriate types and amounts of resources in the public cloud infrastructure in a cost-efficient manner. Also, a plurality of EDA tasks are assigned to computing resources in a manner that minimizes the overall cost for performing the EDA tasks. | 10-06-2011 |
| 20110234600 | Client/Server Waveform Viewer Using Bitmaps - Improving on the waveform viewing technology can advantageously address the industry's need for speedup and capacity of existing solution. As described herein, making data manipulation local and bounded can facilitate tremendous speedup. The waveform viewer can process data on-demand where the user explicitly specifies signals and a desired window (i.e. range). Operations including, but not limited to, zoom, pan, scan, etc. on the waveform viewer can be sent to the waveform servers in the form of a query containing the visualization parameters (e.g. number of pixels), which in turn compute bitmaps (or other waveform images) that are sent back to be displayed. | 09-29-2011 |
| 20110231811 | MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION - An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V | 09-22-2011 |
| 20110231805 | Increasing PRPG-Based Compression by Delayed Justification - An improved compression technique can increase PRPG-based compression by modifying test generation so that justification of certain decision nodes, called xheadlines, is delayed and merged with PRPG seed computation. Xheadlines are defined by gate modification restrictions, dynamic value considerations, and fanout allowance. Before mapping, the xheadlines can be preprocessed. This preprocessing can include transforming XOR xheadlines having shared inputs, augmenting AND/OR xheadlines, and reducing AND/OR xheadlines with common inputs. Mapping can include determining which xheadlines are satisfied by a current seed, which xheadlines can be satisfied by a future seed, and which xheadlines can opportunistically be satisfied by the current seed. | 09-22-2011 |
| 20110224963 | Fast Photolithography Process Simulation to Predict Remaining Resist Thickness - A lithography model uses a transfer function to map exposure energy dose to the thickness of remaining photoresist after development; while allowing the flexibility to account for other physical processes. In one approach, the model is generated by fitting empirical data. The model may be used in conjunction with an aerial image to obtain a three-dimensional profile of the remaining photoresist thickness after the development process. The lithography model is generally compact, yet capable of taking into account various physical processes associated with the photoresist exposure and/or development process for more accurate simulation. | 09-15-2011 |
| 20110219351 | Method for Compensation of Process-Induced Performance Variation in a Mosfet Integrated Circuit - An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing. | 09-08-2011 |
| 20110219349 | PARAMETERIZED CELL CACHING IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that improves performance during parameterized cell instantiation in an electronic design automation (EDA) application. During operation, the system persists evaluation results associated with a parameterized cell in the design within a session of the EDA application so that the evaluation results are available even after they have been flushed from memory. Further, the system can persist the evaluation results across sessions of the EDA application. Next, the system uses the persisted evaluation results to instantiate the parameterized cell without re-evaluating the parameterized cell. Finally, the system discards the persisted evaluation results based at least on a dependency associated with the parameterized cell. | 09-08-2011 |
| 20110218792 | Mixed Concurrent And Serial Logic Simulation Of Hardware Designs - A method of simulating a design described in HDL is provided. In this method, modules of the design can be partitioned into first modules for simulation by a serial simulation engine and second modules for simulation by a concurrent simulation engine. The first and second modules can be prioritized for simulation based on classes of events consistent with an execution model of the HDL. Simulations of the serial and concurrent simulation engines can be synchronized for each class of events. Synchronizing can include transferring updated interface variable values, which are shared by the second modules and at least a subset of the first modules, between the serial simulation engine and the concurrent simulation engine. This transferring can include translating representations of the updated interface variable values. | 09-08-2011 |
| 20110212601 | Stress-Enhanced Performance Of A Finfet Using Surface/Channel Orientations And Strained Capping Layers - Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs. | 09-01-2011 |
| 20110202891 | EVALUATING THE QUALITY OF AN ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD - One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target patterns in response to changes in focus condition of the lithography system. Note that the contours of the target patterns substantially coincide with the edges of set of the polygons. Next, the system computes a cost-covariance field (CCF field) based on the focus-sensitive cost function, wherein the CCF field is a two-dimensional (2D) map representing changes to the focus-sensitive cost function due to an addition of a pattern at a given location within the post-OPC mask layout. Finally, the system generates assist features for the post-OPC mask layout based on the CCF field. | 08-18-2011 |
| 20110197170 | Active Net Based Approach for Circuit Characterization - In a circuit design method, a computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a limited part of the circuit design, where the limited part determined by the active nets. The computer system performs simulation of the circuit design including the netlist of a circuit design and the parasitic netlist of the limited part of the circuit design. In another method the computer system performs simulation of a circuit design including a netlist of the circuit design and a parasitic netlist of a limited part of the circuit design, where the limited part is determined by active nets of a netlist of the circuit design, and the parasitic netlist of the limited part of the circuit design is extracted from a layout of the circuit design. Other aspects are the computer system and a computer readable medium storing the computer instructions to execute the steps. | 08-11-2011 |
| 20110191740 | ZONE-BASED OPTIMIZATION FRAMEWORK - Some embodiments of the present invention provide techniques and systems for efficiently optimizing a circuit design for one or more multi-mode multi-corner (MCMM) scenarios. A system can select an optimizing transformation for a logic gate, which if applied to the logic gate, does not degrade a timing metric in a local context of the logic gate. Next, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in a zone around the logic gate. If so, the system can reject the optimizing transformation. Otherwise, the system can determine whether applying the optimizing transformation to the logic gate degrades the timing metric in the circuit design. If so, the system can reject the optimizing transformation. Otherwise, the system can accept the optimizing transformation. | 08-04-2011 |
| 20110191738 | DENSITY-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide techniques and systems for improving the efficiency of area recovery in an electronic design automation (EDA) flow. During operation, the system determines a utilization of a region from a set of regions in a design floorplan. Next, the system performs area recovery (e.g., by using a processor) on the region based at least on the utilization. Specifically, the system can overlay the design floorplan with a grid, wherein the grid comprises a set of grid cells and uses the grid cells as the set of regions. The grid can be associated with a predetermined number of rows and a predetermined number of columns. The system can determine the utilization of the region by calculating the utilization as a cell area of the region divided by a placement area of the region. The utilization can be incrementally calculated during the creation and optimization of the design. | 08-04-2011 |
| 20110191732 | METHOD AND APPARATUS FOR DETERMINING A ROBUSTNESS METRIC FOR A CIRCUIT DESIGN - Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators. | 08-04-2011 |
| 20110191731 | ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell. | 08-04-2011 |
| 20110185341 | OPTIMIZING BOUNDS CHECKING USING COMPUTER ALGEBRA - Some embodiments of the present invention provide techniques and systems for optimizing bounds-checking During operation, the system can receive one or more instructions which when executed evaluate a first expression whose value is required to be between a lower bound expression's value and an upper bound expression's value, such that at least one of the following three values is not determinable before execution: the first expression's value, the lower bound expression's value, and the upper bound expression's value. Next, the system can use computer algebra to determine whether the first expression's value is guaranteed to be between the lower bound expression's value and the upper bound expression's value. If the system determines that the first expression's value is not guaranteed to be between the lower bound expression's value and the upper bound expression's value, the system can add bounds-checking instructions to the one or more instructions. | 07-28-2011 |
| 20110185335 | DETERMINING AN ORDER FOR VISITING CIRCUIT BLOCKS IN A CIRCUIT DESIGN FOR FIXING DESIGN REQUIREMENT VIOLATIONS - Some embodiments of the present invention provide techniques and systems for determining an order for visiting circuit blocks of a circuit design for fixing design requirement violations. Fixing design requirement violations by visiting circuit blocks in this order can improve performance and quality of results. During operation, a system can determine a set of equal value segments in the circuit design. In some embodiments, the system determines equal value segments for multiple corners and combines the equal value segments to obtain the set of equal value segments. Next, the system can determine an order for visiting circuit blocks of the circuit design for fixing design requirement violations based at least on the set of equal value segments. Note that circuit block pins in an equal value segment are associated with the same parameter value, and parameter values indicate an amount or degree of a design requirement violation. | 07-28-2011 |
| 20110185334 | ZONE-BASED LEAKAGE POWER OPTIMIZATION - A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate. | 07-28-2011 |
| 20110185333 | GLOBAL LEAKAGE POWER OPTIMIZATION - Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order. | 07-28-2011 |
| 20110185329 | GENERATING AND USING ROUTE FIX GUIDANCE - Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation. Additionally, a route fix guidance can specify a set of rectangles to remove from a routing solution, and a set of rectangles to insert into or add to a routing solution. Further, the route fix guidance can include information for moving one or more vias to new locations in the routing solution. The route fix guidance can specify a sequence in which the local modifications are to be made. | 07-28-2011 |
| 20110185324 | METHOD AND APPARATUS FOR CALIBRATING A PHOTOLITHOGRAPHY PROCESS MODEL BY USING A PROCESS WINDOW PARAMETER - One embodiment of the present invention relates to a system that calibrates a photolithography process model. During operation, the system receives a process model which models a photolithography process. The system further receives measured critical dimension (CD) values for a first set of features that were printed by applying the photolithography process to a layout. The system then calibrates the process model using the measured CD values so that CD values predicted by the process model substantially match the measured CD values, and depth of focus (DOF) values predicted by the process model for a second set of features are substantially maximized. | 07-28-2011 |
| 20110185307 | GENERATING EQUATIONS BASED ON USER INTENT - Some embodiments provide a system that facilitates the creation of an equation. During operation, the system obtains a user selection of a function to be used in the equation. Next, the system determines a state of a graphical user interface (GUI) associated with a software program. More specifically, the system may determine a cursor position or a text selection in the equation. Finally, the system facilitates the creation of the equation by inserting the function into the equation based at least on the determined state. | 07-28-2011 |
| 20110184546 | METHOD AND APPARATUS FOR USING AERIAL IMAGE SENSITIVITY TO MODEL MASK ERRORS - One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent on the local pattern density. In some embodiments, the mask error modeling term can include an edge bias term and a corner rounding term. The edge bias term can be based on the sensitivity of the aerial image intensity to an edge bias, and the corner rounding term can be based on the sensitivity of the aerial image intensity to a corner rounding adjustment. | 07-28-2011 |
| 20110179393 | ETCH-AWARE OPC MODEL CALIBRATION BY USING AN ETCH BIAS FILTER - One embodiment of the present invention relates to a system that constructs and calibrates an etch-aware photolithography model. During operation, the system constructs an etch bias model which models a critical dimension (CD) difference between a measured CD value of a feature after the photolithography process and a measured CD value of the feature after the etch process. The system then fits the photolithography process model based at least on the post-lithography measured CD data and the etch bias model, thereby causing the photolithography process model to be aware of etch effects. The present techniques facilitate bridging the gap between the photolithography and the etch process in the OPC modeling flow. In particular, these techniques can be used to modify conventional staged OPC model or to construct a model based rule table for correcting a retarget model. | 07-21-2011 |
| 20110173580 | Nonlinear Driver Model For Multi-Driver Systems - A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system. | 07-14-2011 |
| 20110169140 | RECLAIMING USABLE INTEGRATED CIRCUIT CHIP AREA NEAR THROUGH-SILICON VIAS - Roughly described, an integrated circuit device includes a substrate including a via passing therethrough, a strained electrically conductive first material in the via, the first material tending to introduce first stresses into the substrate, and a strained second material in the via, the second material tending to introduce second stresses into the substrate which at least partially cancel the first stresses. In an embodiment, SiGe is grown epitaxially on the inside sidewall of the via in the silicon wafer. SiO2 is then formed on the inside surface of the SiGe, and metal is formed down the center. The stresses introduce by the SiGe tend to counteract the stresses introduced by the metal, thereby reducing or eliminating undesirable stress in the silicon and permitting the placement of transistors in close proximity to the TSV. | 07-14-2011 |
| 20110161897 | METHOD AND APPARATUS FOR SIMULATING BEHAVIORAL CONSTRUCTS USING INDETERMINATE VALUES - One embodiment of the present invention provides a system that simulates behavioral constructs of a register transfer level design using indeterminate values. The system may receive hardware description language code which includes a construct that behaves differently depending on the value of an expression, e.g., the construct may execute different portions of code based on the value of a control expression, or it may store data in different storage locations based on the value of an index expression, etc. In response to determining that the expression's value is indeterminate, the system can execute two or more alternatives that are controlled by the expression, and then merge the results in some prescribed way. An embodiment of the present invention can enable a user to reduce the discrepancy between the results generated by a register transfer level simulation and the results generated by the associated gate level simulation. | 06-30-2011 |
| 20110147469 | Non Volatile Memory Circuit With Tailored Reliability - A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity. | 06-23-2011 |
| 20110140278 | OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION - An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation of the circuit. The library of shape modifications includes the results of process-specific calibration of the shape modifications which indicate adjustment of a circuit parameter caused by applying the shape modifications to the cells. The layout file is analyzed to identify a cell for adjustment of the circuit parameter. A shape modification calibrated to achieve the desired adjustment is selected from the library. The shape modification is applied to the identified cell in the layout file to produce a modified layout file. The modified layout file can be used for tape out, and subsequently for manufacturing of an improved integrated circuit. | 06-16-2011 |
| 20110138265 | METHOD AND APPARATUS FOR PRESENTING DATE IN A TABULAR FORMAT - Some embodiments provide a system for displaying cells of a table. During operation, the system can receive a sort-and-merge request for sorting the rows of the table using a sort column. Next, the system can sort the rows of the table based at least on cell values in the sort column to obtain a sorted table. The system can then merge a set of consecutive cells in a merge column of the sorted table to obtain a merged cell, wherein the set of consecutive cells are associated with the same cell value. Note that the sort column and the merge column can be the same column, or they can be different columns. Next, the system can display the merged cell and other cells in the sorted-and-merged table. Displaying a cell can involve positioning the cell's value in a visible area of the cell. | 06-09-2011 |
| 20110138157 | CONVOLUTION COMPUTATION FOR MANY-CORE PROCESSOR ARCHITECTURES - A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed. | 06-09-2011 |
| 20110131540 | Path Preserving Design Partitioning With Redundancy - Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of STA can be optimized without compromising the accuracy and quality of results. | 06-02-2011 |
| 20110126167 | Multi-Mode Redundancy Removal - A multi-mode redundancy removal method is provided. In this method, after accessing the design, a full-scale redundancy removal using fault simulation can be started. When a predetermined period for performing the full-scale redundancy removal has reached a first cut-off, then the method can determine a location for temporary outputs of the design, create the temporary outputs, and perform a localized redundancy removal up to the temporary outputs. An optimized design based on the full-scale redundancy removal and the localized redundancy removal can be output. | 05-26-2011 |
| 20110119531 | Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (IC) Design - Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances. | 05-19-2011 |
| 20110107293 | SIMULATION-BASED DESIGN STATE SNAPSHOTTING IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that performs a simulation within an electronic design automation (EDA) application. During operation, the system obtains a design from a user of the EDA application. Next, the system performs the simulation using the design to create a set of current simulation results associated with the design. The system then automatically saves a current design state of the design which is associated with the current simulation results. Finally, the system enables subsequent access to the current design state and one or more previous design states of the design by the user through a graphical user interface (GUI) associated with the EDA application. | 05-05-2011 |
| 20110107286 | METHOD AND APPARATUS FOR LEGALIZING A PORTION OF A CIRCUIT LAYOUT - A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints. | 05-05-2011 |
| 20110107281 | TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application. | 05-05-2011 |
| 20110107252 | TECHNIQUE FOR GENERATING AN ANALYSIS EQUATION - During a method, a hybrid graphical user interface (GUI), which is associated with electronic-design-automation (EDA) software, is displayed. This hybrid GUI allows users to efficiently specify useful analysis equations using textual and/or graphical information. In particular, the hybrid GUI has a first window that includes graphical objects associated with a circuit design. A user can select one or more of the graphical objects and associated electrical parameters using a user-interface device, such as a mouse. The hybrid GUI has a second window that has icons and other graphical controls that allow the construction of an analysis equation using the user-interface device. In addition, the hybrid GUI has a third window that includes an equation editor that provides a symbolic representation of an analysis equation based at least on one or more text entries provided by a user using a second user-interface device (such as a keyboard) and/or user selections of a given graphical object in the graphical objects and an associated electrical parameter. | 05-05-2011 |
| 20110107196 | TECHNIQUE FOR DYNAMICALLY SIZING COLUMNS IN A TABLE - During a technique for dynamically determining sizes of columns in a table, available space in the table is allocated based at least on sequential groups of size targets, which include ranges of sizes of the columns, and which are associated with ordered visual usability targets for the columns. Note that a given size target in a given group of size targets includes a given range of sizes of a given column. For example, minimum sizes of the columns may correspond to the ranges of sizes of one or more of the groups in the sequential groups of size targets for which the columns satisfy the associated ordered visual usability targets. Furthermore, for the next group of size targets in the sequential groups of size targets after the one or more groups, increments to the minimum sizes of the columns may be calculated based at least on the range of sizes of the next group of size targets, the available space and the minimum sizes. | 05-05-2011 |
| 20110102456 | DRAWING AN IMAGE WITH TRANSPARENT REGIONS ON TOP OF ANOTHER IMAGE WITHOUT USING AN ALPHA CHANNEL - An image display system draws a first image on top of a second image. Pixels of the first image include one or more color channels which encode color information, but do not include an alpha channel which encodes transparency information. The system encodes transparency information for the pixels in the first image using at least one bit in at least one color channel of each pixel. The system draws the first image on top of the second image using the transparency information encoded in the color channels of the pixels to obtain a combined image. | 05-05-2011 |
| 20110096848 | "Supply-Less" HDMI Source Terminated Output Stage With Tuned Wide-Range Programmable Termination - A “supply-less” transmitter output stage is provided for a transmitter. This transmitter output stage can include a tunable source termination and a reference voltage generator. The tunable source termination can be coupled between a differential pair of the transmitter. The reference voltage generator can advantageously generate reference voltages from a far-end termination. These reference voltages provide a way of translating the internal supply voltage level to the pad voltage level to enable/disable the tunable source termination. Also, it provides a way to minimize leakage and minimize the junction stress of switching transistors in the tunable source termination as well as the transmitter. The dependency between the reference voltages and the far-end termination voltage makes this design more portable to other supply voltages and other technologies specifications other than HDMI. | 04-28-2011 |
| 20110095367 | ESD/ANTENNA DIODES FOR THROUGH-SILICON VIAS - Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone. | 04-28-2011 |
| 20110093830 | Integrated Circuit Optimization Modeling Technology - A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results. | 04-21-2011 |
| 20110093752 | Method and Apparatus for Synthesis of Augmented Multimode Compactors - Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. | 04-21-2011 |
| 20110078639 | FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM - A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell. | 03-31-2011 |
| 20110061038 | Pre-Route And Post-Route Net Correlation With Defined Patterns - A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output. | 03-10-2011 |
| 20110061037 | Generating Net Routing Constraints For Place And Route - A method of generating net routing constraints for nets of an IC design includes generating a file with hashes organized by nets. Each hash has attributes of a net, e.g. net name, length, fanout, total actual route (AR) resistance, a corresponding virtual route (VR) resistance, and a number of vias. A wire only AR resistance for each net can be calculated. Wire scaling factors can be calculated using the wire only AR resistances and their corresponding VR resistances. Wire scaling factors can be binned by one or more net characteristics. An average wire scaling factor can be calculated for each bin. Code used by a place and route tool can then be generated, wherein the code applies the average wire scaling factors to nets of the design to improve pre-route and post-route correlation. | 03-10-2011 |
| 20110058388 | RIPPLED MIXERS FOR UNIFORMITY AND COLOR MIXING - Various embodiments described herein comprise mixers comprising a light pipe having input and output ends and a central region therebetween. An optical path extends in a longitudinal direction from the input end through the central region to the output end. The central region of the light pipe comprises one or more rippled reflective sidewalls having a plurality of elongate ridges and valleys and sloping surfaces therebetween. Light from the input end propagating along the optical path reflects from the sloping surfaces and is redirected at a different azimuthal direction toward the output end thereby mixing the light at the output end. Illuminance and/or color mixing can therefore be provided. | 03-10-2011 |
| 20110055791 | METHOD AND APPARATUS FOR PERFORMING ROUTING OPTIMIZATION DURING CIRCUIT DESIGN - One embodiment of the present invention provides a system that concurrently optimizes multiple routing objectives during routing of an integrated circuit (IC) chip design. During operation, the system starts by receiving a routing solution for the IC chip design and a set of routing objectives. The system then partitions the IC chip design into a set of partitions. Next, for each partition in the set of partitions, the system optimizes the routing solution by, iteratively: (1) analyzing the routing solution to determine weights for the set of routing objectives; (2) constructing a cost function based on the weights for the set of routing objectives; and (3) modifying the routing solution within the partition to attempt to optimize the cost function. | 03-03-2011 |
| 20110055790 | MULTI-THREADED DETAILED ROUTING - Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a set of partitions for a circuit design, wherein each partition has zero or more overlapping partitions along four directions, e.g., up, down, left, and right. Next, the system can perform, in parallel, detailed routing on non-overlapping partitions in the set of partitions, wherein detailed routing is performed on a partition after detailed routing is completed on adjacent or overlapping partitions that located along two perpendicular directions. In some embodiments, each detailed routing thread that is executing in parallel performs detailed routing on a different net. | 03-03-2011 |
| 20110055789 | MULTI-THREADED TRACK ASSIGNMENT - Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. During operation, the system can receive a first set of partitions for a circuit design, wherein each partition in the first set of partitions extends across the circuit design along a first direction. Next, the system can perform, in parallel, track assignment in the first direction on non-overlapping partitions in the first set of partitions. The system can then receive a second set of partitions for the circuit design, wherein each partition in the second set of partitions extends across the circuit design along a second direction which is different from the first direction. Next, the system can perform, in parallel, track assignment in the second direction on non-overlapping partitions in the second set of partitions. In some embodiments, each track assignment process being performed in parallel performs track assignment on a different net. | 03-03-2011 |
| 20110055788 | METHOD AND APPARATUS FOR ROUTING USING A DYNAMIC GRID - One embodiment of the present invention provides a system that routes connections in an integrated circuit (IC) chip design. The system includes a representation mechanism which is configured to represent routing resources in the IC chip design as a 3-dimensional (3D) grid. This 3D grid further includes: static grid lines which do not change while the system routes the connections; and dynamic grid lines which are created for routing a connection that includes pins which are not located on a static grid line. Note that the dynamic grid lines can be removed after the connection is routed. The system also includes a search engine which is configured to search for a path in the 3D grid between a first set of vertices and a second set of vertices. | 03-03-2011 |
| 20110055786 | METHOD AND APPARATUS FOR SATISFYING ROUTING RULES DURING CIRCUIT DESIGN - One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution. The system then assigns weights to the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule. The system additionally assigns effort levels to the set of routing rules, wherein a higher effort level for a routing rule indicates that a higher amount of resources are available to satisfy the routing rule. The system then modifies the routing solution to satisfy the routing rules based at least on the weights and the effort levels associated with the routing rules. | 03-03-2011 |
| 20110055785 | METHOD AND APPARATUS FOR PERFORMING REDUNDANT VIA INSERTION DURING CIRCUIT DESIGN - One embodiment of the present invention provides a system that concurrently performs redundant via insertion and timing optimization during routing of an integrated circuit (IC) chip design. During operation, the system performs an initial routing on the IC chip design to obtain a routing solution, which includes a set of vias. The system then performs a redundant-via-insertion operation on the routing solution, wherein the redundant-via-insertion operation attempts to modify a via within the set of vias into a redundant via. Next, the system performs a timing optimization on the routing solution by iteratively: (1) performing a timing analysis on the routing solution; (2) performing a logic optimization on the routing solution; and (3) performing an incremental routing adjustment on the routing solution, wherein the incremental routing adjustment adjusts the redundant vias. | 03-03-2011 |
| 20110055784 | MULTI-THREADED GLOBAL ROUTING - Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During operation, the system determines bounding boxes for nets, and associates nets with partitions, wherein a partition associated with a net encloses the net's bounding box. Then, the system routes nets in non-overlapping partitions in parallel. Next, the system adjusts bounding boxes of nets which need to be routed again, and routes these nets in the next iteration. In some embodiments, the system may use a cost function to guide the routing process. The system may adjust the weights of one or more terms of the cost function as the routing process progresses. Specifically, the system may increase the importance of a congestion term as the routing process progresses. | 03-03-2011 |
| 20110041112 | METHOD AND APPARATUS FOR GENERATING A CENTERLINE CONNECTIVITY REPRESENTATION - Some embodiments provide a system for generating a centerline connectivity representation for a set of routing shapes. During operation, the system can represent the set of routing shapes using a set of centerlines with endcap extensions. Note that an intersection between two centerlines represents an electrical connection between the two routing shapes associated with the two centerlines. Next, the system can detect two routing shapes which overlap, but whose centerlines do not intersect. The system can then create a virtual shape whose centerline intersects with the centerlines of the two routing shapes. In some embodiments, the system can modify a dimension of at least one of the two routing shapes. Next, the system can create a new routing shape which overlaps with the two routing shapes, and create virtual shapes which connect the centerline of the new shape with the centerlines of the two routing shapes. | 02-17-2011 |
| 20110041111 | METHOD AND APPARATUS FOR GENERATING A MEMORY-EFFICIENT REPRESENTATION OF ROUTING DATA - Some embodiments provide a system for generating a memory-efficient representation of a sequence of electrically connected routing shapes. The memory-efficient representation represents the sequence of electrically connected routing shapes using a sequence of points, such that two consecutive points represent a routing shape. At least some of the points can be represented using a compact representation, thereby reducing the memory required for storing the sequence of points. A full representation specifies a point's location using the point's two-dimensional coordinates, and a compact representation specifies a point's location using one of the point's two-dimensional coordinates and an orientation indicator which indicates the routing shape's orientation. The missing coordinate in a compact representation can be determined from the preceding points. The system can represent a via that joins two routing shapes by assigning different metal layers to the points associated with the two routing shapes. | 02-17-2011 |
| 20110040528 | Systemic Diagnostics For Increasing Wafer Yield - A method of performing systemic diagnostics for a wafer includes selecting a design for manufacturability (DFM) rule for analysis. For each IC chip on the wafer, two sets of IC features adjacent the rule can be extracted based on the chip's layout design. Upconverted diagnostics can be run to generate computed numbers associated with combination categories for each set. Zonal analysis can be run on the two sets using the computed numbers to derive metrics for the two sets. A report can be generated based on the zonal analysis. | 02-17-2011 |
| 20110035201 | METHOD FOR DYNAMICALLY ADJUSTING SPEED VERSUS ACCURACY OF COMPUTER PLATFORM SIMULATION - Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also comprises modifying the value of the dynamic quantum based on a simulation event. | 02-10-2011 |
| 20110029944 | ROUTING VARIANTS IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a schematic in an electronic design automation (EDA) application. During operation, the system obtains a source point and a destination point in the schematic from a user of the EDA application. Next, the system uses a line-probe-search technique to generate a set of route variants between the source point and the destination point. The system then provides the route variants to the user through a graphical user interface (GUI) in the EDA application and obtains, from the user, a selection of a route variant from the route variants through the GUI. Finally, the system uses the selected route variant as a route in the schematic. | 02-03-2011 |
| 20110029940 | METHOD AND APPARATUS FOR MODELING THIN-FILM TOPOGRAPHY EFFECT ON A PHOTOLITHOGRAPHY PROCESS - One embodiment of the present invention provides a system that determines image intensity at a location in a photoresist (PR) layer on a wafer. During operation, the system receives a set of masks which were used to generate one or more patterned layers of a multilayer structure on the wafer, wherein a patterned layer includes a set of reflectors on a top surface of the patterned layer, which correspond to patterns in a patterned-layer mask in the set of masks, wherein a reflector reflects light from a light source during a photolithography process. The system then generates a first virtual mask based on the first mask and the patterned-layer mask, wherein the first virtual mask uses a clear area to model a reflector in the set of reflectors. Next, the system determines the image intensity value at the location on the PR layer based at least on the first mask and the first virtual mask. | 02-03-2011 |
| 20110029299 | Hierarchical Order Ranked Simulation Of Electronic Circuits - A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary. | 02-03-2011 |
| 20110029118 | METHOD AND APPARATUS FOR MODELING CHEMICALLY AMPLIFIED RESISTS - Some embodiments provide a system for accurately and efficiently modeling chemically amplified resist. During operation, the system can determine a quenched acid profile from an initial acid profile by applying multiple quenching models which are associated with different acid concentration ranges to the initial acid profile. One quenching model may be expressed as H=H | 02-03-2011 |
| 20110025705 | LOOP REMOVAL IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates graphical object creation in an electronic design automation (EDA) application. During operation, the system uses a cursor to obtain a sequence of points from a user for creating a graphical object in a layout. Next, the system detects a loop in the graphical object based at least on the sequence of points and a current position of the cursor. Finally, the system modifies the sequence of points to remove the loop from the graphical object. | 02-03-2011 |
| 20110023006 | CONNECTION NAVIGATION IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system obtains a set of parameters associated with parameterized connections in a hierarchy of the design and a set of net assignments to the parameters. Next, the system displays the parameters and the net assignments to a user of the EDA application through a graphical user interface (GUI) associated with the EDA application. Finally, the system enables modifications to the net assignments by the user through the GUI. | 01-27-2011 |
| 20110023001 | DYNAMIC RULE CHECKING IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of the EDA application. Next, the system automatically applies a set of dynamic design rules to the schematic upon detecting the change. Finally, the system notifies the user of a rule violation if the schematic violates one or more of the dynamic design rules. The system allows the user to specify which dynamic rules to apply when the user is modifying the schematic. | 01-27-2011 |
| 20110022987 | CYCLE-TAPPING TECHNIQUE FOR SELECTING OBJECTS - A technique for selecting an object is described. During this technique, a computer system selects an object from multiple objects associated with a circuit design in an electronic-design-automation (EDA) environment based at least on a current cursor location and a current design command. For example, the computer system may select the object by determining distances between the cursor location and objects in at least a subset of the multiple objects, and then identifying the minimum distance in the distances. Furthermore, the object may be selected either with or without a user first providing an object-selection input. If the object-selection input is provided, the user may do so by performing one or more mouse clicks or a keyboard shortcut, as opposed to using a window (such as a dialog box or a drop-down menu) that can be displayed in the EDA environment. | 01-27-2011 |
| 20110019763 | USB 2.0 HS Voltage-Mode Transmitter With Tuned Termination Resistance - A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D− signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 Ω±10%) in the USB transceiver. | 01-27-2011 |
| 20110019086 | HDMI Controller Circuit For Transmitting Digital Data To Compatible Audio Device Using Address Decoder Where Values Are Written To Registers Of Sub-Circuits - The present invention provides a high definition media interface (HDMI) controller having a modular design internal bus structure, and applications thereof. The controller includes a circuit interface, an address decoder coupled to the circuit interface, a plurality of sub-circuits, wherein each sub-circuit includes registers used to configure and control the sub-circuit, and a bus that couples the registers of each sub-circuit to the address decoder. After startup of the controller, the sub-circuits are configured by using the circuit interface, address decoder, and bus to write values to the registers of the sub-circuits. The sub-circuits of the controller include a video pixel sampler, an audio sampler, a frame composer, and a power controller. The video sampler can be configured to convert one of a plurality of RGB and YCbCr signals to a common format signal used by other sub-circuits of the controller. | 01-27-2011 |
| 20110016438 | FLASH-BASED ANTI-ALIASING TECHNIQUES FOR HIGH-ACCURACY HIGH-EFFICIENCY MASK SYNTHESIS - Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout. | 01-20-2011 |
| 20110016423 | GENERATING WIDGETS FOR USE IN A GRAPHICAL USER INTERFACE - During a technique for generating a window, a description of an object and associated attributes, which include information other than a visual presentation of the object, are received from a user. Then, different types of widgets are generated based at least on the description of the object, the attributes and predefined widget rules. These widgets are arranged in a window based at least on the widgets and predefined layout rules. For example, the widgets may be dynamically resized based on the number of widgets and the size of the window. Then, the window is presented in a graphical user interface (GUI). Subsequently, the window and the attributes are dynamically updated to reflect changes to either one. In this way, the user may focus on the high-level aspects of what is to be presented in the GUI, instead of how to translate this information into the corresponding visual presentation. | 01-20-2011 |
| 20110016294 | TECHNIQUE FOR REPLAYING OPERATIONS USING REPLAY LOOK-AHEAD INSTRUCTIONS - A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation. Alternatively, if a blocking user-interface request occurred when the first operation was previously performed (such as a mandatory query), the replay look-ahead instruction may include one or more events associated with the user answer to the blocking user-interface request so that the same user answer may be provided when replaying the first operation. | 01-20-2011 |
| 20110016094 | TRANSACTION HISTORY WITH BOUNDED OPERATION SEQUENCES - A technique for maintaining a transaction history is described. This transaction history includes a sequence of commands or operations in an electronic-design-automation (EDA) environment. For subsets of one or more operations in the sequence of operations, the transaction history includes an associated transaction name, as well as a state of the of the subset, which is open after an initial EDA operation in the subset has been performed and is closed after a last EDA operation in the subset has been performed. This transaction history can be displayed in a window in a graphical user interface, and facilitates undoing and/or rolling back of changes to the data associated with one or more subsets. For example, if an error is detected, roll back of one or more subsets to a known software state or condition prior to the operations in the one or more subsets may be performed without user instructions using the transaction history. | 01-20-2011 |
| 20110010680 | Apparatus and Method of Delay Optimization - Aspect of the technology are a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is for use in forming a lithographic mask set for use in fabricating an integrated circuit. In the method the computer system divides a synthesized circuit design into cell partitions along critical paths of the synthesized circuit design. The computer system associates pins of the plurality of cell partitions with normalized pin timing values. The normalized pin timing values store magnitude differences between a reference timing slack and timing slacks of the plurality of pins. After optimizing the synthesized circuit design, the computer system repeats the method, and then the computer system determines whether to further optimize the plurality of cell partitions by comparing: (i) the pre-optimization normalized pin timing values of the plurality of cell partitions with (ii) the post-optimization normalized pin timing values of the plurality of cell partitions. | 01-13-2011 |
| 20100318592 | Multiplicative Division Circuit With Reduced Area - The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number. | 12-16-2010 |
| 20100291476 | Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers - A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers. | 11-18-2010 |
| 20100281445 | EFFICIENT EXHAUSTIVE PATH-BASED STATIC TIMING ANALYSIS USING A FAST ESTIMATION TECHNIQUE - One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path. | 11-04-2010 |
| 20100281444 | MULTIPLE-POWER-DOMAIN STATIC TIMING ANALYSIS - Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each power domain can be propagated during the full circuit graph-based STA to accurately perform STA without enumerating all paths. Some embodiments can use a tag-based engine to track power-domain crossing(s) during graph-based STA. If a power-domain is crossed in a path, pessimism may be added to the cumulative delay at the end point of the path. For those paths that do not cross a power domain, pessimism may be removed from the cumulative delay at their end points. In some embodiments, pessimism may be removed from the cumulative delay at end points for paths that cross power domains. | 11-04-2010 |
| 20100280814 | LOGIC SIMULATION AND/OR EMULATION WHICH FOLLOWS HARDWARE SEMANTICS - Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation. | 11-04-2010 |
| 20100280812 | Modeling critical-dimension (CD) scanning-electron-microscopy (CD-SEM) CD extraction - One embodiment of the present invention relates to a process that models critical-dimension (CD) scanning-electron-microscopy (CD-SEM) extraction during photolithography process model calibration. During operation, the process receives measured CD values which were obtained using a CD-SEM extraction process, wherein the CD-SEM extraction process determines a measured CD value for a feature by measuring multiple CD values of the feature along multiple electron beam scans. The process then determines simulated CD values, wherein a simulated CD value is determined based at least on a set of CD extraction cut-lines evenly placed around the target feature. During subsequent photolithography process model calibration, the process fits a parameter that models an aspect of the photolithography process based at least on both the measured CD values and the simulated CD values. | 11-04-2010 |
| 20100275169 | ADAPTIVE STATE-TO-SYMBOLIC TRANSFORMATION IN A CANONICAL REPRESENTATION - Some embodiments provide a system for adaptively performing state-to-symbolic transformation in a canonical representation which is used for generating random stimulus for a constrained-random simulation. The system can construct a canonical representation for a set of constraints using the set of random variables and the subset of the state variables in the constraints. Next, the system can use the canonical representation to generate random stimulus for the constrained-random simulation, and monitor parameters associated with the constrained-random simulation. Next, the system can add state variables to or remove state variables from the canonical representation based at least on the monitored parameters. The system can then use the modified canonical representation which has a different set of state variables to generate random stimulus for the constrained-random simulation. | 10-28-2010 |
| 20100275074 | RUNTIME PROGRAMMABLE BIST FOR TESTING A MULTI-PORT MEMORY DEVICE - One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence. | 10-28-2010 |
| 20100274376 | Method and Apparatus for Performing Stress Modeling of Integrated Circuit Material Undergoing Material Conversion - A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary. | 10-28-2010 |
| 20100270597 | METHOD AND APPARATUS FOR PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 10-28-2010 |
| 20100269078 | AUTOMATIC APPROXIMATION OF ASSUMPTIONS FOR FORMAL PROPERTY VERIFICATION - One embodiment provides a system, comprising methods and apparatuses, for simplifying a set of assumptions for a circuit design, and for verifying the circuit design by determining whether the circuit design satisfies a set of assertions when the simplified set of assumptions is satisfied. During operation, the system can simplify the set of assumptions by identifying, for an assertion in the set of assertions, a first subset of assumptions which, either directly or indirectly, shares logic with the assertion. Furthermore, the system can modify the first subset of assumptions to obtain a second subset of assumptions which either over-approximates or under-approximates the first subset of assumptions. Then, the system can refine the second subset of assumptions to either prove or falsify the assertion. | 10-21-2010 |
| 20100262946 | Model-based assist feature placement using inverse imaging approach - Some embodiments provide techniques and systems to identify locations in a target mask layout for placing assist features. During operation, an embodiment can determine a spatial sampling frequency to sample the target mask layout, wherein sampling the target mask layout at the spatial sampling frequency prevents spatial aliasing in a gradient of a cost function which is used for computing an inverse mask field. Next, the system can generate a grayscale image by sampling the target mask layout at the spatial sampling frequency. The system can then compute the inverse mask field by iteratively modifying the grayscale image. The system can use the gradient of the cost function to guide the iterative modification process. Next, the system can filter the inverse mask field using a morphological operator, and use the filtered inverse mask field to identify assist feature locations in the target mask layout. | 10-14-2010 |
| 20100235801 | METHOD AND APPARATUS FOR ACCELERATING PROJECT START AND TAPE-OUT - Some embodiments of the present invention provide systems and techniques that accelerate project start and tape-out. During operation, a system can receive a set of technology files and a set of libraries. Next, the system can identify deficiencies in the set of technology files and the set of libraries. The system can then construct update utilities that when executed by a computer system cause the computer system to fix the deficiencies in the technology files and the set of libraries. Further, a system can receive a set of checks that are performed by a foundry. Next, the system can construct tape-out scripts that when executed by a computer cause the computer to perform the set of checks on the circuit design. The update utilities and the tape-out scripts can then be provided to a customer with an electronic design automation software to accelerate project start and tape-out. | 09-16-2010 |
| 20100235799 | METHOD AND APPARATUS FOR GENERATING A FLOORPLAN USING A REDUCED NETLIST - One embodiment provides a system comprising methods and apparatuses that generate a floorplan for a hierarchical circuit design. More specifically, the system can receive a non-reduced netlist description for the hierarchical circuit design, and generate a reduced netlist which includes the interface logic elements of the netlist. The system can then generate the floorplan by using the reduced netlist as input. Note that the amount of computational resources and time required to generate a floorplan is substantially reduced because the system generates the floorplan using the reduced netlist instead of using the non-reduced netlist. | 09-16-2010 |
| 20100235795 | EXECUTION MONITOR FOR ELECTRONIC DESIGN AUTOMATION - Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur. | 09-16-2010 |
| 20100229136 | CROSSTALK TIME-DELAY ANALYSIS USING RANDOM VARIABLES - Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to calculate the total time delay in a signal path due to crosstalk from a group of crosstalk aggressors that are associated with a group of signal paths. In order to properly account for statistical behaviors in the switching times and directions of the switching patterns in the group of signal paths, the time-delay contribution from each of these crosstalk aggressors may be modeled as a corresponding statistical random variable. Because the number of crosstalk aggressors are usually much larger than the number of stages in the signal path, the calculated total path delay may be less pessimistic. Furthermore, in order to detect potential timing violations, the time-delay contributions from additional dominant crosstalk aggressors can be modeled using non-statistical worst-case deterministic values. | 09-09-2010 |
| 20100229132 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described. | 09-09-2010 |
| 20100223516 | Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time. | 09-02-2010 |
| 20100218160 | METHOD AND APPARATUS FOR DETERMINING A PROCESS MODEL THAT MODELS THE IMPACT OF A CAR/PEB ON THE RESIST PROFILE - An embodiment provides systems and techniques for determining a process model. During operation, the system may receive a first optical model which models a first optical system of a photolithography process. Next, the system may use the first optical model to determine a second optical model that models a second latent image that is formed by the first optical system at a second distance. The system may also use the first optical model to determine a third optical model that models a third latent image that is formed by the first optical system at a third distance. Next, the system may receive process data which is obtained by subjecting a test layout to the photolithography process. The system may then determine a process model using the first optical model, the second optical model, the third optical model, the test layout, and the process data. | 08-26-2010 |
| 20100201445 | Class D Amplifier Having PWM Circuit With Look-Up Table - A class D amplifier includes a noise-shaping modulator, a pulse width modulator, and a pulse amplifier. The noise-shaping modulator receive a pulse code modulated (PCM) signal and produces an oversampled PCM signal. The pulse width modulator produce a pulse width modulated (PWM) signal from the oversampled PCM signal. The pulse amplifier amplifies the PWM signal to produce an amplified PWM signal. The PWM uses a lookup table to convert from PCM to PWM. A compensation circuit optimizes amplifier performance. An optional demodulator filter converts the amplified PWM signal to an analog signal. The amplifier is ideal for integrated audio applications. | 08-12-2010 |
| 20100199255 | METHOD AND APPARATUS FOR CORRECTING ASSIST-FEATURE-PRINTING ERRORS IN A LAYOUT - One embodiment of the present invention provides a system that adjusts assist features in a layout to prevent assist features from printing. During operation, the system receives a layout. The system then identifies an assist-feature (AF)-printing hotspot in the layout, wherein the AF-printing hotspot includes a set of assist features and one or more target patterns in proximity to the set of assist features. At least one assist feature in the set of assist features is expected to print during a lithography process. Next, the system modifies the AF-printing hotspot by: (1) modifying the set of assist features; and (2) performing optical-proximity-correction (OPC) on the one or more target patterns. The system then performs a lithography simulation on the modified AF-printing hotspot to determine if: (1) a through-process-window associated with the modified AF-printing hotspot is acceptable; and (2) no assist feature in the modified set of assist features is expected to print. If so, the system replaces the AF-printing hotspot with the modified AF-printing hotspot. | 08-05-2010 |
| 20100199245 | Non-Linear Receiver Model For Gate-Level Delay Calculation - A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first capacitance value to match the delay characteristics of an actual receiver, and by using the second capacitance (in light of the use of the first capacitance) to match the slew characteristics of that actual receiver. Because typical EDA timing analyses focus mainly on delay and slew (and not the detailed profile of circuit signals), a two-capacitance receiver model can provide a high degree of accuracy without significantly increasing cell library size and computational complexity. | 08-05-2010 |
| 20100199236 | METHOD AND APPARATUS FOR PERFORMING RLC MODELING AND EXTRACTION FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT (3D-IC) DESIGNS - One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description. | 08-05-2010 |
| 20100198875 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system. | 08-05-2010 |
| 20100198539 | FAST AND ACCURATE ESTIMATION OF GATE OUTPUT LOADING - Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to analyze an electrical characteristic of a logic gate electrically coupled to an output network in a stage. In particular, during the analysis, the effective capacitance of an output network coupled to a logic gate is approximated as a function of a total resistance of the output network, a total capacitance of the output network, and a geometric parameter of the output network. For example, the effective capacitance may be approximated as a function of a ratio of the product of the total resistance and the total capacitance to the fanout count of the output network. Using the effective capacitance and other parameters, such as a slew rate of an electrical signal applied to an input of the logic gate, an electrical characteristic of the logic gate, such as an input capacitance, is determined. | 08-05-2010 |
| 20100194779 | METHOD AND SYSTEM FOR SIZING POLYGONS IN AN INTEGRATED CIRCUIT (IC) LAYOUT - One embodiment of the present invention provides a system that sizes a polygon in a layout. During operation, the system receives a polygon which is to be sized by a sizing amount. The system then selects one or more vertices of the polygon. Next, the system replaces each selected vertex with a set of replacement vertices, and subsequently assigns a projection path to each replacement vertex in the set of replacement vertices. The system next performs a sizing operation on the polygon according to the sizing amount. During the sizing operation, the system moves each replacement vertex in the set of replacement vertices along the assigned projection path, thereby creating a clipping on the angle associated with the selected vertex. Furthermore, this sizing operation is continuous: similar output polygons are obtained for similar sizing amounts. | 08-05-2010 |
| 20100192114 | METHOD AND APPARATUS FOR PERFORMING ABSTRACTION-REFINEMENT USING A LOWER-BOUND-DISTANCE - Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique. | 07-29-2010 |
| 20100192113 | METHOD AND APPARATUS FOR MANAGING VIOLATIONS AND ERROR CLASSIFICATIONS DURING PHYSICAL VERIFICATION - Some embodiments provide a system for managing violations during physical verification. The system may identify a design-rule-check (DRC) violation by applying a set of DRC rules to a layout. The system can then receive an error classification from the user which specifies how the DRC violation is to be handled. Next, the system can store the DRC violation, the user-selected error classification, and a user identifier associated with the user in a database. If the user is not authorized to approve the error classification, the database can indicate that the error classification has not been approved. Later, a user who is authorized to approve the error classification can approve the error classification. The system can determine if a cell is known, and if so, the system can use the violations and error classifications stored in the database to speed up the verification process. | 07-29-2010 |
| 20100192111 | PERFORMING LOGIC OPTIMIZATION AND STATE-SPACE REDUCTION FOR HYBRID VERIFICATION - One embodiment of the present invention provides a system that facilitates optimization and verification of a circuit design. The system can receive a set of assumptions associated with a circuit. The set of assumptions can specify a set of logical constraints on at least a set of primary inputs of the circuit. Note that the set of assumptions are expected to be satisfied during normal circuit operation. The system can generate a stimulus generator based in part on an assumption in the set of assumptions. The output values from the stimulus generator, which when assigned to the set of primary inputs of the circuit, cause the set of primary inputs to satisfy the assumption. Next, the system can generate a modified circuit by coupling the outputs of the stimulus generator with a set of primary inputs of the circuit. The system can then perform logic optimization on the modified circuit to obtain an optimized circuit. | 07-29-2010 |
| 20100192030 | METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TEST SOLUTION - Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module. | 07-29-2010 |
| 20100191679 | METHOD AND APPARATUS FOR CONSTRUCTING A CANONICAL REPRESENTATION - Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR-size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a combined CR. Next, the system can identify a problematic CR which when combined with the combined CR causes the CR-size limit to be exceeded. The system can then report the problematic CR and/or a logical function associated with the problematic CR to a user, thereby helping the user to identify an error in the set of logical functions. | 07-29-2010 |
| 20100191518 | COMPACT ABBE'S KERNEL GENERATION USING PRINCIPAL COMPONENT ANALYSIS - Some embodiments provide techniques for determining a set of Abbe's kernels which model an optical system of a photolithography process. During operation, the system can receive optical parameters (e.g., numerical aperture, wavelength, etc.) for the photolithography process's optical system. Next, the system can use the optical parameters to determine a point spread function for an Abbe's source. Note that the point spread function for the Abbe's source can be determined either by discretizing the optical system's light source using a set of concentric circles, or by discretizing the optical system's light source in an orthogonal fashion. The system can then determine a correlation matrix from the point spread function. Next, the system can determine the set of Abbe's kernels by performing an eigen decomposition of the correlation matrix using principal component analysis. The system can then use the set of Abbe's kernels to compute image intensity. | 07-29-2010 |
| 20100190277 | Power Network Stacked Via Removal For Congestion Reduction - A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded. | 07-29-2010 |
| 20100187609 | BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS - Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate. | 07-29-2010 |
| 20100179804 | Natural Language Assertion Processor - A method of processing natural language assertions (NLAs) can include identifying an NLA and then translating that NLA into a verification language assertion (VLA) using a natural language parser (NLP) and synthesis techniques. This VLA can be translated into an interpreted NLA (NLA*) using a VLA parser and pattern matching techniques. At this point, the process can allow user review of the NLA* and the NLA. When the user determines that the NLA* and the NLA are the same or have insignificant difference, then verification can be performed using the VLA. The results of the verification can then be back annotated on the NLA. In one fully-automatic embodiment, in addition to comparing the NLA and the NLA*, the VLA and a VLA* (generated from the NLA*) can be compared, thereby providing yet another test of accuracy for the user during verification. | 07-15-2010 |
| 20100146476 | MODELING MASK CORNER ROUNDING EFFECTS USING MULTIPLE MASK LAYERS - An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography process to the mask layout. The system may also receive an uncalibrated process model which may contain a set of MCR components. Next, the system may identify a set of corners in the mask layout. The system may then determine a set of mask layers, wherein at least some of the mask layers correspond to the MCR components. Next, the system may determine an improved process model by calibrating the uncalibrated process model using the set of mask layers, and the process data. | 06-10-2010 |
| 20100131913 | METHOD AND APPARATUS FOR SCALING I/O-CELL PLACEMENT DURING DIE-SIZE OPTIMIZATION - One embodiment of the present invention provides a system that scales an I/O-cell placement during die-size optimization. During operation, the system starts by receiving an initial die-size for a die and an initial I/O-cell placement for a set of I/O cells. The system also receives a target die-size for the die. The system then determines die-size changes between the initial die-size and the target die-size. Next, the system identifies available spaces between the set of I/O cells in the initial I/O-cell placement. The system subsequently scales the initial I/O-cell placement based on the identified available spaces and the die-size changes to obtain a new I/O-cell placement which fits in the target die-size. | 05-27-2010 |
| 20100131909 | FAST LITHOGRAPHY COMPLIANCE CHECK FOR PLACE AND ROUTE OPTIMIZATION - A computer is programmed to use at least one rule to identify from within a layout of an IC design, a set of regions likely to fail if fabricated unchanged. An example of such a rule of detection is to check for presence of two neighbors neither of which fully overlaps a short wire or an end of a long wire. The computer uses at least another rule to change at least one region in the set of regions, to obtain a second layout which is less likely to fail in the identified regions. An example of such a rule of correction is to elongate at least one of the two neighbors. The computer may perform optical rule checking (ORC) in any order relative to application of the rules, e.g. ORC can be performed between detection rules and correction rules i.e. performed individually on each identified region prior to correction. | 05-27-2010 |
| 20100121474 | Method and System for Enhancing the Yield In Semiconductor Manufacturing - Roughly described, a manufacturing process is enhanced by using TCAD and TCAD-derived models. A TCAD simulation model of the process is developed, which predicts, in dependence upon a plurality of process input parameters, a value for a performance parameter of a product to be manufactured using the process. Estimated, predicted or desired values for a calculated subset of the parameters (including either process input parameters or product performance parameters or both), are determined in dependence upon the process model, and further in dependence upon actual, estimated or desired values for a different subset of the parameters (again either process input parameters or product performance parameters or both). The determination is preferably made using a process compact model of the process, itself developed in dependence upon the simulation model. | 05-13-2010 |
| 20100115526 | METHOD AND APPARATUS FOR ALLOCATING RESOURCES IN A COMPUTE FARM - Some embodiments provide a system for allocating resources in a compute farm. During operation, the system can receive resource-requirement information for a project. Next, the system can receive a request to execute a new job in the compute farm. In response to determining that no job slots are available for executing the new job, and that the project associated with the new job has not used up its allocated job slots, the system may execute the new job by suspending or re-queuing a job that is currently executing, and allocating the freed-up job slot to the new job. If the system receives a resource-intensive job, the system may create dummy jobs, and schedule the dummy jobs on the same computer system as the resource-intensive job to prevent the queuing system from scheduling multiple resource-intensive jobs on the same computer system. | 05-06-2010 |
| 20100115489 | METHOD AND SYSTEM FOR PERFORMING LITHOGRAPHY VERIFICATION FOR A DOUBLE-PATTERNING PROCESS - One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask. | 05-06-2010 |
| 20100115486 | ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD - One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target patterns in response to changes in focus condition of the lithography system. Note that the contours of the target patterns substantially coincide with the edges of set of the polygons. Next, the system computes a cost-covariance field (CCF field) based on the focus-sensitive cost function, wherein the CCF field is a two-dimensional (2D) map representing changes to the focus-sensitive cost function due to an addition of a pattern at a given location within the post-OPC mask layout. Finally, the system generates assist features for the post-OPC mask layout based on the CCF field. | 05-06-2010 |
| 20100115481 | Shape-Based Geometry Engine To Perform Smoothing And Other Layout Beautification Operations - A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved. | 05-06-2010 |
| 20100115476 | CONGESTION OPTIMIZATION DURING SYNTHESIS - One embodiment of the present invention provides a system that optimizes a circuit design during a logic design stage to reduce routing congestion during a placement and routing stage. During operation, this system identifies a first circuit structure in the circuit design which is expected to cause routing congestion during the placement and routing stage. Next, the system generates a second circuit structure which is functionally equivalent to the first circuit structure, and is not expected to cause routing congestion during the placement and routing stage. The system then replaces the first circuit structure in the circuit design with the second circuit structure, thereby mitigating routing congestion during the placement and routing stage. | 05-06-2010 |
| 20100110307 | PROGRAMMABLE IF OUTPUT RECEIVER, AND APPLICATIONS THEREOF - A tuner system for receiving a plurality of frequency bands includes a low noise amplifier coupled with a band selection filter to select a desired band. The tuner system further includes a complex RF filter to produce a complex RF signal from the selected band. The tuner system includes two double-quadrature converters, the first double-quadrature converter frequency down-converts the complex RF signal to a complex baseband signal. The complex baseband signal passes through a baseband filter that contains two identical lowpass filters for obtaining a baseband in-phase (I) signal and a quadrature (Q) signal. The second double-quadrature converter up-converts the baseband I and Q signals to respective IF I and Q signals that are significantly free of the positive third IF harmonic. The third IF-harmonic free I and Q signals are further processed by a complex bandpass filter. The bandpass filter has a programmable frequency center and a programmable bandwidth. | 05-06-2010 |
| 20100109706 | USB 2.0 HS Voltage-Mode Transmitter With Tuned Termination Resistance - A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D− signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45Ω±10%) in the USB transceiver. | 05-06-2010 |
| 20100107220 | SECURE CONSULTATION SYSTEM - A secure consultation system is disclosed that enables an owner entity to securely store its most secure and private data such that designated entities of the owner entity and a consultant entity can execute application programs on that data and thus, to consult on the operation and correctness of the application programs and the data. | 04-29-2010 |
| 20100107132 | METHOD AND APPARATUS FOR MEMORY ABSTRACTION AND FOR WORD LEVEL NET LIST REDUCTION AND VERIFICATION USING SAME - A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced. | 04-29-2010 |
| 20100107131 | METHOD AND APPARATUS FOR MEMORY ABSTRACTION AND VERIFICATION USING SAME - A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced. | 04-29-2010 |
| 20100106476 | Fast Simulation Method For Integrated Circuits With Power Management Circuitry - In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output. | 04-29-2010 |
| 20100100781 | Fully X-Tolerant, Very High Scan Compression Scan Test Systems And Techniques - Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods. | 04-22-2010 |
| 20100097107 | TWO-PHASE CLOCK-STALLING TECHNIQUE FOR ERROR DETECTION AND ERROR CORRECTION - One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block. | 04-22-2010 |
| 20100095264 | METHOD AND APPARATUS FOR DETERMINING A PHOTOLITHOGRAPHY PROCESS MODEL WHICH MODELS THE INFLUENCE OF TOPOGRAPHY VARIATIONS - One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layout, the wafer can include topography variations which were caused by previous exposure-and-development steps. The process model can be used to predict patterns that are created on the wafer when the wafer is exposed to a second layout, wherein the wafer includes topography variations that were caused by resist features that were created when the wafer was exposed to a first layout. The process model can include a first term and a second term, wherein the first term is convolved with a sum of the first layout and the second layout, and wherein the second term is convolved with the second layout. | 04-15-2010 |
| 20100092880 | METHOD AND APPARATUS FOR USING A SYNCHROTRON AS A SOURCE IN EXTREME ULTRAVIOLET LITHOGRAPHY - One embodiment of the present invention provides a method to facilitate using a synchrotron as a source in an extreme ultraviolet lithography (EUVL) system, wherein the synchrotron's energy decreases over time. The EUVL system can includes a stepper which uses a step-and-repeat process or a step-and-scan process to transfer patterns from a reticle onto a wafer. The wafer is desired to be exposed to a substantially constant dose. During operation, the system can measure a synchrotron current, and adjust the stepper's exposure duration or the stepper's scan speed based on the synchrotron current so that the wafer is exposed to the substantially constant dose. Note that using the synchrotron current to control the stepper can enable the EUVL system to expose the wafer to the substantially constant dose without using additional equipment to monitor the source's energy. | 04-15-2010 |
| 20100086196 | METHOD AND APPARATUS FOR DETERMINING AN OPTICAL THRESHOLD AND A RESIST BIAS - One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The system can then determine multiple aerial-image-intensity values in proximity to the iso-focal pattern by convolving the layout with multiple optical models, wherein the multiple optical models model the photolithography process's optical system under different focus conditions. Next, the system can determine a location in proximity to the iso-focal pattern where the aerial-image-intensity values are substantially insensitive to focus variations. The system can then use the location and the associated aerial-image-intensity values to determine an optical threshold and a resist bias. The optical threshold and the resist bias can then be used for modeling the photolithography process. | 04-08-2010 |
| 20100083246 | SYSTEM AND METHOD FOR VERIFYING DELIVERED SOFTWARE - Some embodiments of the present invention provide a system that verifies software which was distributed from a master site to a user site. During operation, the system receives a master list from the master site at the user site, where the master list specifies items of software which could be installed on the user site. The system also generates an actual list on the user site indicating which items of software are actually installed on the user site. The system then compares the actual list with the master list, and if the actual list is inconsistent with the master list, the system performs a remedial action. | 04-01-2010 |
| 20100083243 | SYSTEM AND METHOD FOR DELIVERING SOFTWARE - Some embodiments of the present invention provide a system for delivering software. During operation, the system receives selections from a user, wherein the selections specify items of software to be delivered from a master site to a user site. The system also receives priority information from the user, wherein the priority information specifies a priority for delivery for the selected items of software. Next, the system determines an order of delivery for the selected items of software based on the priority information. Finally, the system delivers the selected items of software from the master site to the user site in accordance with the determined order of delivery. | 04-01-2010 |
| 20100083201 | Verification Technique Including Deriving Invariants From Constraints - A method of performing formal verification on a design for an integrated circuit can include accessing a set of constraints for the design. These constraints can be partitioned based on their variables, wherein any overlapping variables can result in the conjoining of their corresponding constraints. Binary decision diagrams (BDDs) can be generated based on such conjoining. Notably, invariants can be derived from the BDDs. These invariants can include constant, symmetric/implication, one-hot/zero-hot, and ternary invariants. Deriving the invariants can include cofactoring and counting of minterms of the BDDs. Using the invariants while performing formal verification on the design can advantageously optimize system performance. | 04-01-2010 |
| 20100083199 | Increasing Scan Compression By Using X-Chains - To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities. | 04-01-2010 |
| 20100077366 | METHOD AND APPARATUS FOR WORD-LEVEL NETLIST REDUCTION AND VERIFICATION USING SAME - A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes. | 03-25-2010 |
| 20100077184 | METHOD AND APPARATUS FOR REMOVING A PIPELINE BUBBLE - One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register has valid data and whether the pipeline is stalled. Next, the system gates the clock signal using the clock-enable signal. The augmented pipeline can determine whether a first register contains invalid data, which is associated with a bubble. Next, the augmented pipeline determines whether a second register contains valid data, wherein the second register is adjacent to and upstream from the first register. If the first register contains invalid data and the second register contains valid data, the augmented pipeline replaces the invalid data of the first register with valid data based on the valid data in the second register without propagating the invalid data to a downstream register. | 03-25-2010 |
| 20100070940 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data - An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. | 03-18-2010 |
| 20100070938 | Preconditioning For EDA Cell Library - A characterized cell library for EDA tools includes one or more mathematical models for each cell, and one or more preconditioning functions (and/or inverse preconditioning functions) for each mathematical model. Each mathematical model represents a performance parameter (e.g., delay, power consumption, noise) or a preconditioned performance parameter of the cell. The preconditioning functions convert an operating parameter (e.g., input slew, output capacitance) associated with the performance parameter into a preconditioned input variable for the mathematical models. In doing so, the preconditioning functions allow for more accurate modeling of complex data relationships without increasing the complexity (e.g., order and number of coefficients) of the mathematical models. Also, because the cell library can be substantially similar to conventional polynomial-based cell libraries except for the inclusion of preconditioning functions, preconditioning does not significantly increase storage requirements and conventional EDA tools can be readily adapted to use the preconditioned cell library. | 03-18-2010 |
| 20100070935 | Method and Apparatus for Merging EDA Coverage Logs of Coverage Data - An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. | 03-18-2010 |
| 20100058280 | BULK IMAGE MODELING FOR OPTICAL PROXIMITY CORRECTION - A method is described herein for predicting lateral position information about a feature represented in an integrated circuit layout for use with an integrated circuit fabrication process, where the process projects an image onto a resist. The method includes providing a lateral distribution of intensity values of the image at different depths with the resist. Next, the lateral position of an edge point of the feature is predicted in dependence upon a particular resist development time, and further in dependence upon the image intensity values at more than one depth within the resist. | 03-04-2010 |
| 20100050149 | Design and Layout of Phase Shifting Photolithographic Masks - A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts. | 02-25-2010 |
| 20100042958 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 02-18-2010 |
| 20100040965 | Exposure control for phase shifting photolithographic masks - Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. In one embodiment, the phase shifting mask and the trim mask are exposed using substantially the same exposure conditions. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures. | 02-18-2010 |
| 20100031217 | METHOD AND SYSTEM FOR FACILITATING FLOORPLANNING FOR 3D IC - One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value. | 02-04-2010 |
| 20100031214 | Method and Apparatus for Proximate Placement of Sequential Cells - Various methods and apparatuses (such as computer readable media implementing the method) are described that relate to proximate placement of sequential cells of an integrated circuit netlist. For example, the preliminary placement is received; and based on the preliminary placement, a group of sequential cells is identified as being subject to improved power and/or timing upon subsequent placement. In another example, identification is received of a group of sequential cells subject to improved power and/or timing upon subsequent placement; and proximate placement is performed of the identified group of sequential cells. In yet another example, a proximate arrangement of a group of sequential cells is received; and if proximate placement fails, then the group of sequential cells is disbanded and placement is performed of the sequential cells of the disbanded group. | 02-04-2010 |
| 20100031101 | Dynamically Reconfigurable Shared Scan-In Test Architecture - A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time. | 02-04-2010 |
| 20100029050 | STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion. | 02-04-2010 |
| 20100026251 | VOLTAGE REGULATOR WITH RIPPLE COMPENSATION - Embodiments of the present invention provide a voltage regulator. The voltage regulator includes a driving mechanism coupled to an output node (VREG), wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node. In addition, the voltage regulator includes a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in the output node voltage when a load coupled to the output node requires a transient switching current that is faster than the loop response time of the driving mechanism. Furthermore, the boost circuit is biased using a self-tracking mechanism to provide accurate duration and level of the current to the output node in a transient switching event. | 02-04-2010 |
| 20100025777 | METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE - A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer. | 02-04-2010 |
| 20100024978 | STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS - Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion. | 02-04-2010 |
| 20100023902 | ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE - Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation. | 01-28-2010 |
