SuVolta, Inc. Patent applications |
Patent application number | Title | Published |
20140248753 | ANALOG TRANSISTOR - An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped | 09-04-2014 |
20140167157 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 06-19-2014 |
20140119099 | DRAM-TYPE DEVICE WITH LOW VARIATION TRANSISTOR PERIPHERAL CIRCUITS, AND RELATED METHODS - A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region. | 05-01-2014 |
20140084385 | DEEPLY DEPLETED MOS TRANSISTORS HAVING A SCREENING LAYER AND METHODS THEREOF - A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure. | 03-27-2014 |
20140077312 | ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME - Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 03-20-2014 |
20140038386 | REDUCING OR ELIMINATING PRE-AMORPHIZATION IN TRANSISTOR MANUFACTURE - A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate. | 02-06-2014 |
20140035060 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXED METAL TYPES - A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device. | 02-06-2014 |
20140015067 | SOURCE/DRAIN EXTENSION CONTROL FOR ADVANCED TRANSISTORS - A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 | 01-16-2014 |
20130328129 | LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF - A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 12-12-2013 |
20130020639 | ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME - Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 01-24-2013 |
20130020638 | ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME - Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 01-24-2013 |
20120327725 | CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS - Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed. | 12-27-2012 |
20120299111 | ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME - Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 11-29-2012 |
20120223389 | SEMICONDUCTOR STRUCTURE WITH IMPROVED CHANNEL STACK AND METHOD FOR FABRICATION THEREOF - A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer. | 09-06-2012 |
20120009743 | DYNAMIC RANDOM ACCESS MEMORY HAVING JUNCTION FIELD EFFECT TRANSISTOR CELL ACCESS DEVICE - A method of fabricating a dynamic random access memory (DRAM) can include depositing a semiconductor electrode layer in contact with a surface of a semiconductor substrate; patterning the electrode layer to form a plurality of access junction field effect transistor (JFET) gate electrodes and a plurality of sense amplifier bipolar junction transistor (BJT) electrodes; and forming a charge storage structure coupled to a source of each access JFET. | 01-12-2012 |
20110309450 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION THEREOF WITH MIXED METAL TYPES - A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device. | 12-22-2011 |
20110303955 | Junction Field Effect Transistor Having A Double Gate Structure And Method of Making Same - A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region. | 12-15-2011 |
20110074498 | Electronic Devices and Systems, and Methods for Making and Using the Same - A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV | 03-31-2011 |
20100315128 | CIRCUIT CONFIGURATIONS HAVING FOUR TERMINAL DEVICES - Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode. | 12-16-2010 |
20100149854 | SEMICONDUCTOR DEVICE STORAGE CELL STRUCTURE, METHOD OF OPERATION, AND METHOD OF MANUFACTURE - A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and forming a control gate terminal from at least a portion of a semiconductor layer deposited on a substrate surface in contact with the channel region, the portion of the semiconductor layer being doped to the second conductivity type. | 06-17-2010 |