| SUBTRON TECHNOLOGY CO. LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120088117 | SUBSTRATE STRUCTURE - A substrate structure including a first metal substrate, a second metal substrate, a frame fixture, a first conductive layer, a second conductive layer, a first adhesive layer and a second adhesive layer is provided. The second metal substrate is stacked over the first metal substrate. The frame fixture is disposed around the first metal substrate and the second metal substrate. The first adhesive layer is disposed between the first conductive layer and the first metal substrate, and between the first conductive layer and the frame fixture. The first conductive layer is fixed on an upper surface of the frame fixture by the first adhesive layer. The second adhesive layer is disposed between the second conductive layer and the second metal substrate, and between the second conductive layer and the frame fixture. The second conductive layer is fixed on a lower surface of the frame fixture by the second adhesive layer. | 04-12-2012 |
| 20120070684 | THERMAL CONDUCTIVITY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thermal conductivity substrate including a metal substrate, a metal layer, an insulating layer, a plurality of conductive structures, a first conductive layer and a second conductive layer is provided. The metal layer is disposed on the metal substrate and entirely covers the metal substrate. The insulating layer is disposed on the metal layer. The conductive structures are embedded in the insulating layer and connected to a portion of the metal layer. The first conductive layer is disposed on the insulating layer. The second conductive layer is disposed on the first conductive layer and the conductive structures. The second conductive layer is electrically connected to a portion of the metal layer through the conductive structures. The second conductive layer and the conductive structures are integrally formed. | 03-22-2012 |
| 20120007252 | SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATING METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity. | 01-12-2012 |
| 20110253439 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates. | 10-20-2011 |
| 20110204021 | METHOD OF MAKING FINE-PITCH CIRCUIT LINES - A method of making fine-pitch circuit lines includes steps of preparing an insulative substrate, disposing a conductive metal layer on the insulative substrate, disposing on a whole or a part of a top surface of the conductive metal layer a hetero layer having an etching rate smaller than that of the conductive metal layer, forming a patterned mask of circuit lines on the hetero layer, wet etching the hetero layer and the conductive metal layer, and removing the patterned mask and the hetero layer so as to form fin-pitch circuit lines having a high etching factor on the insulative substrate. | 08-25-2011 |
| 20110154658 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer. | 06-30-2011 |
| 20110154657 | MANUFACTURING METHOD OF PACKAGE CARRIER - A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer. | 06-30-2011 |
| 20110151273 | LAMINATE FOR PRINTED CIRCUIT BOARD - A laminate for use in the production of a printed circuit board includes a main layer and a face layer made of a material different from the material that the main layer is made of. The main layer is made of a good electrically conductive metal and has a top surface. The face layer is disposed on the top surface of the main layer and made of a material having an etching rate substantially smaller than that of the material that the main layer is made of. The laminate can exhibit a high etching factor even if the laminate is etched by a conventional etchant. | 06-23-2011 |
| 20100206463 | FABRICATING PROCESS OF THERMAL ENHANCED SUBSTRATE - A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. A metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks. | 08-19-2010 |
| 20090314650 | PROCESS OF PACKAGE SUBSTRATE - A process of a package substrate is provided. A plurality of metal layers stacked in sequence is used as a foundation structure. A thick heat conductive core is fabricated from one of the metal layers for providing high heat dissipation capability, and a plurality of pads is fabricated from another one of the metal layers for electrically connecting an electronic package at the next level. | 12-24-2009 |
| 20090288859 | NON-CYLINDER VIA STRUCTURE AND THERMAL ENHANCED SUBSTRATE HAVING THE SAME - A thermal enhanced substrate having a non-cylinder via structure includes at least a metal layer disposed on an insulating base material and a number of thermal channels respectively constituted by at least a trough pattern penetrating the insulating base material and a conductive material deposited in the trough pattern. The trough pattern serves as a non-cylinder via structure having at least an elongated hole for heat dissipations so as to reduce a working temperature of an electronic device. | 11-26-2009 |
| 20090280617 | FABRICATING PROCESS FOR SUBSTRATE WITH EMBEDDED PASSIVE COMPONENT - A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component. | 11-12-2009 |
| 20090196979 | INKJET PRINTING PROCESS FOR CIRCUIT BOARD - An inkjet printing process for a circuit board includes the following procedures. Firstly, a substrate and a conductive layer disposed on the substrate are provided. Afterward, a roughening treatment is performed on the conductive layer so that the roughness of the conductive layer is between 0.1 μm and 5 μm. Then, a patterned mask layer is printed on the conductive layer for covering an area of the conductive layer prepared for forming a circuit pattern. | 08-06-2009 |
| 20090139756 | FABRICATING PROCESS OF CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT - A fabricating process of a circuit board with an embedded passive component is described. First, a conductive layer including a first surface and a second surface opposite thereto is provided. The first surface has at least one component region on which at least one passive component material layer is formed. A passivation layer is formed on the first surface to cover the passive component material layer. A brown oxidation process is performed on the conductive layer. A circuit unit and an insulation layer are provided, and the insulation layer is set between the circuit unit and the conductive layer. The conductive layer, the circuit unit and the insulation layer are laminated. The passive component material layer is between the insulation layer and the conductive layer. The conductive layer is patterned to form a circuit layer. | 06-04-2009 |
| 20080308925 | FABRICATING PROCESS AND STRUCTURE OF THERMAL ENHANCED SUBSTRATE - A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. First, a metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks. | 12-18-2008 |
