| STMICROELECTRONICS S.R.L. Patent applications |
| Patent application number | Title | Published |
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| 20120137022 | ELECTRONIC DEVICE WITH ADDRESS PROGRAMMABLE THROUGH REDUCED NUMBER OF TERMINALS - An electronic device includes a set of programming terminals for receiving corresponding programming signals, and assignment circuitry for assigning an address to the electronic device according to the programming signals. The assignment circuitry includes circuitry for providing a set of comparison signals, with at least part of the comparison signals that is variable during a non-zero comparison interval, and comparison circuitry for determining the address according to a comparison between the programming signals and the comparison signals during the comparison interval. | 05-31-2012 |
| 20120134060 | ELECTRONIC DEVICE WITH PROTECTION CIRCUIT - An electronic device comprises an application circuit; a first supply rail having a first electric potential; a second supply rail having a second electric potential different from the first electric potential; at least one terminal having a third electric potential, connected to the application circuit; and a protection circuit for protecting the application circuit from an injected current. The protection circuit comprises a first conductive line connected between the at least one terminal and the first supply rail, the first conductive line comprising a first switch having a first control input; and a first voltage amplifier circuit having a first input connected to the at least one terminal, a second input connected to the second supply rail and a first output connected to the first control input. | 05-31-2012 |
| 20120133151 | DEVICE AND RELATIVE METHOD FOR SCAVENGING ENERGY - An energy scavenging device includes an electromagnetic transducer adapted to generate a current in response to accelerations impressed thereto. The device also includes a power switching stage input with the current generated by the electromagnetic transducer, having a network of controlled switches adapted to alternately deliver on output nodes of the switching stage an output current that does not invert its sign and to short-circuit the transducer. There is an output capacitor coupled between the output nodes of the power stage. A controller having a sensor coupled to the electromagnetic transducer is to sense the current flowing therethrough, the controller being adapted to drive the switches of the power stage in order to either short-circuit the electromagnetic transducer or to direct the current flowing through the transducer to charge the output capacitor. | 05-31-2012 |
| 20120132711 | LARGE AREA MONITORING DEVICE - A monitoring device may include a core cell including a detection circuit, and a radio frequency (RF) tag antenna configured to exchange data with a data acquisition reader device, and a single-tier corolla having sensor cells around the core cell and covering a monitoring area. The sensor cells may be configured to convert a change of a parameter at the cell location. The detection circuit may be configured to detect a change in the parameter and location based upon excitation by the reader device. | 05-31-2012 |
| 20120132003 | MEMS BIAXIAL RESONANT ACCELEROMETER - A microelectromechanical detection structure for a MEMS resonant biaxial accelerometer is provided with: an inertial mass, anchored to a substrate by elastic elements to be suspended above the substrate. The elastic elements enabling inertial movements of the inertial mass along a first axis of detection and a second axis of detection that belong to a plane of main extension of said inertial mass, in response to respective linear external accelerations. At least one first resonant element and one second resonant element have a respective longitudinal extension, respectively along the first axis of detection and the second axis of detection, and are mechanically coupled to the inertial mass through a respective one of the elastic elements to undergo a respective axial stress when the inertial mass moves respectively along the first axis of detection and the second axis of detection. | 05-31-2012 |
| 20120128071 | APPARATUS AND METHOD FOR PERFORMING ERROR CONCEALMENT OF INTER-CODED VIDEO FRAMES - An embodiment relates to performing error concealment of a corrupted block in a video frame, which is capable of performing a real time reconstruction of corrupted blocks which allow to precisely recover small details and fine movements, in particular, the error concealment apparatus and method according to an embodiment selects a replacement block by taking into account the luminance distortion and the motion characteristics of the video sequence. The latter is represented by the distance of the motion vectors chosen as candidate replacements and the average value of the motion vectors of the blocks surrounding the missing block in the current frame. | 05-24-2012 |
| 20120127350 | METHOD AND DEVICE FOR DE-NOISING A DIGITAL VIDEO SIGNAL, AND CORRESPONDING COMPUTER PROGRAM PRODUCT - A method may denoise a digital video signal produced by a photoelectric sensor as a matrix of pixel signals affected by both thermal noise and impulsive noise. The method may include estimating the noise level associated to the pixel signals, and filtering the pixel signals with an attenuation factor that is a function of the estimated noise level. | 05-24-2012 |
| 20120126880 | IGBT DEVICE WITH BURIED EMITTER REGIONS - An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element. | 05-24-2012 |
| 20120120987 | Temperature-Current Transducer - A temperature-current transducer includes first and second voltage dividers, with the first voltage divider including a thermistor in an environment. An operational amplifier has a first input coupled to an intermediate node of the first voltage divider, and a second input coupled to an intermediate node of the second voltage divider. A cascode stage is configured to be biased in a conduction state and is controlled by the operational amplifier. The cascode stage includes a first current terminal coupled to the intermediate node of the second voltage divider. A current mirror is coupled to a second current terminal of the cascode stage, and is configured to mirror on an output line current flowing through the cascode stage that is representative of temperature differences between a temperature in an environment of the thermistor and a reference temperature. | 05-17-2012 |
| 20120119382 | SEMICONDUCTOR DEVICE WITH VERTICAL CURRENT FLOW AND LOW SUBSTRATE RESISTANCE AND MANUFACTURING PROCESS THEREOF - A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate. | 05-17-2012 |
| 20120119381 | SEMICONDUCTOR DEVICE WITH VERTICAL CURRENT FLOW AND LOW SUBSTRATE RESISTANCE AND MANUFACTURING PROCESS THEREOF - A semiconductor device with vertical current flow includes a body having a substrate made of semiconductor material. At least one electrical contact on a first face of the body. A metallization structure is formed on a second face of the body, opposite to the first face. The metallization structure is provided with metal vias, which project from the second face within the substrate so as to form a high-conductivity path in parallel with portions of said substrate. | 05-17-2012 |
| 20120116746 | SIMULATION SYSTEM FOR IMPLEMENTING COMPUTING DEVICE MODELS IN A MULTI-SIMULATION ENVIRONMENT - An embodiment of a simulation tool includes a path determiner and a simulator. The path determiner is configured to identify a first communication path between first and second devices of a system, and the simulator is configured to simulate a routing of a first item from one of the first and second devices to the other of the first and second devices via the identified path. The path determiner may also be configured to identify the communication path before the simulator simulates the routing of the item, or to identify the communication path while the simulator is inactive. | 05-10-2012 |
| 20120099344 | CONTROL DEVICE FOR A RESONANT CONVERTER - A control device controls a switching circuit of a resonant converter having an output direct current. The switching circuit includes at least a half-bridge of at least a first and a second transistor connected between an input voltage and a reference voltage. The half-bridge is adapted to generate a periodic square-wave voltage for driving the resonant circuit of said resonant circuit and the periodic square-wave voltage oscillates between a high voltage corresponding to the input voltage and a low voltage corresponding to the reference voltage. The control device comprises a generator adapted to generate a periodic square-wave signal for driving the half-bridge. The control device comprises a detector adapted to detect the phase-shift between the periodic square-wave signal generated by the generating means and the current flowing through the resonant circuit, and adapted to control the turning off of the half-bridge when the phase-shift exceeds a first phase-shift value. | 04-26-2012 |
| 20120098520 | METHOD AND RELATIVE DEVICE FOR SENSING AMPLITUDE AND PHASE OF AN ELECTRICAL SIGNAL - A method of sensing an amplitude and a phase of a varying electrical signal representing an impedance of an electrically conductive tissue through which an AC stimulation current is forced may include measuring a first amplitude value of the varying electrical signal corresponding to an arbitrary initial phase offset value and assuming the first amplitude value corresponds to the amplitude and assuming the arbitrary initial phase offset value corresponds to the phase. The method may include measuring a second amplitude value of the varying electrical signal at a phase offset different from the phase. The method may further include comparing the second amplitude value with the amplitude, and updating the amplitude and the phase to correspond to one of a maximum and a minimum amplitude value and to a corresponding phase offset. | 04-26-2012 |
| 20120098474 | APPARATUS FOR DETECTING THE POSITION OF A ROTOR OF AN ELECTRIC MOTOR AND RELATED METHOD - An apparatus detects the position of a rotor of an electric motor having three phases and a plurality of windings. The apparatus includes circuitry configured to connect at least two of said windings between first and second reference voltages according to a first current path disconnect said at least two windings, and allow the current stored in said two windings to be discharged through a second current path. The apparatus comprises a measuring circuit configured to measure the time period between the starting instant of storing the current in the two windings and the final instant of discharging the two windings and a rotor detector configured to detect the rotor position based at least in part on the measured time period. | 04-26-2012 |
| 20120098142 | ELECTRICAL CONTACT FOR A DEEP BURIED LAYER IN A SEMI-CONDUCTOR DEVICE - A semi-conductor device includes at least one deep buried layer with an electrical connection made thereto by an electrical contact. The electrical contact to the deep buried layer is made by formed an opening through the use of a first chemical attack and a second chemical attack after the first chemical attack. By making an opening, the electrical contact can be made with the deep buried layer without at the same time occupying excessively wide portions of the device. For example, it is possible to make electrical contacts having a width of less than 1.5 μm with deep layers having a depth of more than 5 μm. | 04-26-2012 |
| 20120098135 | INTEGRATED CIRCUITS WITH BACKSIDE METALIZATION AND PRODUCTION METHOD THEREOF - An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer. | 04-26-2012 |
| 20120096928 | METHOD FOR MANUFACTURING A SENSOR DEVICE OF A GASEOUS SUBSTANCE OF INTEREST - A method manufactures a sensor device for sensing a gaseous substance and includes a thin film transistor, which includes a source electrode, a drain electrode and a gate electrode; and an element sensitive to the gaseous substance. In particular, the method includes: forming a first metallic layer on a substrate; defining and patterning the first metallic layer for realizing the gate electrode; depositing a dielectric layer above the gate electrode; depositing a second metallic layer above the layer of dielectric material, defining and patterning the second metallic layer for realizing the source electrode and the drain electrode, and forming the sensitive element by filling a channel region of the thin film transistor with an active layer sensitive to the gaseous substance. | 04-26-2012 |
| 20120089352 | MODULAR DEVICE FOR PROTECTING AND MONITORING A BATTERY - A modular device having at least one master integrated circuit, and one or more slave integrated circuit modules coupled to the at least one master integrated circuit with each slave integrated circuit module of the one or more slave integrated circuit modules coupled to and associated with only a single cell of the battery. Each slave integrated circuit module of the one or more slave integrated circuit modules further comprises: detection circuitry adapted to detect data comprising one or more of the temperature, voltage or charge status, and malfunctioning of the single cell associated with and monitored by the slave integrated circuit; and an interface operable to send said detected data to the at least one master integrated circuit. The at least one master integrated circuit is adapted to send commands to a slave integrated circuit module in response to the detected data detected by the slave integrated circuit module. | 04-12-2012 |
| 20120081137 | TESTING METHOD FOR SEMICONDUCTOR INTEGRATED ELECTRONIC DEVICES AND CORRESPONDING TEST ARCHITECTURE - A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method. | 04-05-2012 |
| 20120079438 | INTEGRATED CIRCUIT DESIGN FRAMEWORK COMPRISING AUTOMATIC ANALYSIS FUNCTIONALITY - An embodiment of an integrated circuit design framework comprises a user interface which automatically initializes a three-dimensional simulation tool for simulating or analyzing the characteristics of a complex metallization system. In some illustrative embodiments the user interface may additionally provide electrically simulated parameter values for an input parameter, such as the channel resistance of a power transistor, thereby enabling a simulation of a portion of interest of the metallization system without actually requiring the provision of the design data of the power transistor. | 03-29-2012 |
| 20120079154 | TRANSACTION REORDERING ARRANGEMENT - An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued. | 03-29-2012 |
| 20120079148 | REORDERING ARRANGEMENT - An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are configured to provide respective responses to respective requests. The network-on-chip further includes an interconnect for routing said requests and respective responses to said requests to and from the plurality of sources and at least one transaction reordering arrangement. The transaction reordering arrangement is configured to reorder said responses such that said responses are provided to a respective source in an order which corresponds to an order in which the requests are issued by said respective source. A respective transaction reordering arrangement is associated with a respective source. | 03-29-2012 |
| 20120076162 | DEVICE FOR TRANSFORMING ELECTROMAGNETIC IR ENERGY FROM SPATIALLY INCOHERENT, LOW-POWER DENSITY, BROAD-BAND RADIATION IN SPATIALLY COHERENT, HIGH-POWER DENSITY, QUASI-MONOCHROMATIC RADIATION - A device to be positioned between a heat source and a heat sink may transform infrared electromagnetic (IR-EM) energy exchanged therebetween from a first form to a second form. The device may include a pair of layers facing each other and having dielectric material with molecular excitability characteristics to produce the second form of IR-EM energy. The pair of layers may define a gap therebetween. The device may include a conversion circuit configured to convert the second form of IR-EM energy into electrical energy. | 03-29-2012 |
| 20120075010 | DISCHARGE CIRCUIT FOR VOLTAGE MULTIPLIERS - An embodiment of a discharge circuit for evacuating electric charge accumulated in circuit nodes of a charge pump during a discharge phase consequent to a shutdown of the charge pump is proposed. The charge pump is configured to bias each circuit node with a corresponding pump voltage during an operational phase of the charge pump. The discharge circuit includes a generator circuit configured to generate a discharge current during the discharge phase. The discharge circuit further includes means for evacuating the electric charge stored in each circuit node of the charge pump during a corresponding portion of the discharge phase; such means for evacuating include a respective discharge stage for each circuit node of the charge pump. Each discharge stage includes a first discharge circuit branch and a second discharge circuit branch coupled to the corresponding circuit node. The discharge stage is configured to cause the discharge current flowing through the first discharge circuit branch—during the portion of the discharge phase of the corresponding circuit node—when the pump voltage of the corresponding circuit node is higher than a respective threshold, and through the second discharge circuit branch when the pump voltage of the corresponding circuit node is lower than said respective threshold. | 03-29-2012 |
| 20120071365 | Detection Device Having Increased Detection Rate, and Method for Quick Detection of Biological Molecules - A biological molecule detection device that includes a detection array, arranged on a body and having one or more probes for detecting corresponding electrically charged molecules, wherein a time varying electric field generating circuit is provided for generating at least one time varying electric field around the detection array within the detection region. The time varying electric field moves the electrical charged molecules repeatedly back and forth over the probes, thus providing increased opportunities for interaction and speeding the detection process. | 03-22-2012 |
| 20120069994 | METHOD FOR GENERTAING A DIGITAL SIGNATURE - A method for generating a digital signature includes calculating a first magnitude representative of the inverse of a random number raised to the power two; obtaining a first element of the digital signature by executing scalar multiplication between an established point of the elliptic curve and the random number; obtaining a second magnitude by executing modular multiplication, with modulus corresponding to the established elliptic curve's order between the first magnitude and the secret encryption key; obtaining a third magnitude by executing a modular multiplication, with modulus corresponding to the established elliptic curve's order between the random number and the secret encryption key; obtaining a first addend of a second element of the digital signature by executing a modular multiplication, with modulus corresponding to the established elliptic curve's order between the second magnitude and the third magnitude; and generating a second element of the digital signature based on the first addend. | 03-22-2012 |
| 20120068725 | SENSING STRUCTURE OF ALIGNMENT OF A PROBE FOR TESTING INTEGRATED CIRCUITS - A sensing structure for use in testing integrated circuits on a substrate. The sensing structure includes at least two sensing regions connectable to a probe and at least one first sensing element. Each of the at least one first sensing elements is directly connected to two sensing regions such that for each sensing region a different value of an electrical parameter is measurable between the sensing region and a first reference potential so as to reliably determine a drift direction of a probe. | 03-22-2012 |
| 20120059622 | LOCATION SYSTEM FOR STREET LIGHT MONITORING - A street light monitoring system has a small fraction of the street lights in the system being anchor nodes that are configured to detect and store their own actual fixed position, thereby acting as reference points. Further, the other street lights are referred to as blind nodes and do not have their actual fixed position but can derive their position using the coordinates of the anchor nodes and estimating their distance to them. The distance estimation for any blind node can be performed using a received signal strength indication (RSSI) measured at the respective blind node for small distances of up to a threshold value and a link quantization technique takes advantage of the typical placement of the street lights. Inferred distances between the street lights can be assigned to pre-determined categories of distances for a coarse estimation and further position adjustment to a closest possible “real” position. | 03-08-2012 |
| 20120057379 | POWER SUPPLY CIRCUIT FOR REMOTELY TURNING-ON ELECTRICAL APPLIANCES - A power supply circuit for an electrical appliance, including a turning-on stage configured for determining a transition from a turned-off state, in which the power supply circuit is off and does not supply electric power, to a turned-on state of the power supply circuit. The turning-on stage includes a transducer of the remote-control type configured for triggering the transition in response to the reception of a wireless signal. | 03-08-2012 |
| 20120056200 | INTEGRATED ELECTRONIC DEVICE WITH EDGE-TERMINATION STRUCTURE AND MANUFACTURING METHOD THEREOF - An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region. | 03-08-2012 |
| 20120045076 | ELECTRONIC CIRCUIT FOR DRIVING A SWITCHING AMPLIFIER - An electronic circuit is disclosed for driving a switching amplifier. The electronic circuit is configured for generating, when operating in a switch-on mode, a driving signal for driving the switching amplifier. The driving signal carries a plurality of pulses having: an pulse width increasing between contiguous pulses of the plurality of pulses according to a step value having modulus equal to two and odd values; a polarity alternating between the contiguous pulses. | 02-23-2012 |
| 20120040856 | METHOD FOR DETECTING THE PRESENCE OF LIQUIDS IN A MICROFLUIDIC DEVICE, DETECTING APPARATUS AND CORRESPONDING MICROFLUIDIC DEVICE - A method for detecting the presence of liquids includes detecting an initial temperature in a channel accommodating a liquid; heating the channel for a pre-determined test time; detecting a test temperature; determining a temperature variation on the basis of the initial temperature, the test temperature, and the test time; and comparing the temperature variation with at least one threshold. Before detecting an initial temperature, an ambient temperature is read, the channel is heated to the initial temperature, and is kept at the initial temperature for a time period. | 02-16-2012 |
| 20120033806 | METHOD OF ENCRYPTING A DATA STREAM - The disclosure relates to a method of encrypting or of decrypting a binary data stream by generating a binary encryption stream and combining by a reversible logic operation each bit of the binary data stream with a bit of the binary encryption stream, the generation of the binary encryption stream including generating an input block by applying a cryptographic function using a secret key to a data block, and generating the binary encryption stream from the input block by combining the bits of the input block with each other by logic operations in a manner so as to prevent the input block from being determined from the binary encryption stream. | 02-09-2012 |
| 20120032285 | Electronic Device Including MEMS Devices And Holed Substrates, In Particular Of The LGA Or BGA Type - An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free. | 02-09-2012 |
| 20120029900 | SIMULATION METHOD AND SYSTEM FOR SIMULATING A MULTI-CORE HARDWARE PLATFORM - Embodiments of the invention relate to methods and systems for simulating a multi-core hardware platform the devices of which are modeled by functional or cycle-based models. In order to improve the simulation speed, a computer implemented method utilizes functional models that include an execution time in the reply to a transaction while maintaining the simulation accuracy relative to a cycle-based simulation of the same hardware platform. The execution time indicates an estimated number of cycles of a main clock which the represented device would have required for executing the operation. The simulation system initiates a transaction by a master model to request the execution of an operation by a slave model. The slave model executes the requested operation, and replies to the transaction returning a result of the executed operation to the master model, and where the slave model is a functional model, the execution time. | 02-02-2012 |
| 20120026766 | CONTROL DEVICE OF A SWITCHING POWER SUPPLY - A control device controls a switching converter that converts an alternating supply voltage to a regulated voltage and comprises a switch connected to an inductor. The control device is adapted to control the on period and the off period of said switch for each cycle. The control device comprises a ramp generator adapted to generate a ramp voltage, a comparator adapted to determine the final instant of the on period of the switch by crossing the ramp voltage with a first voltage. The control device has a first signal representing a current through the inductor and a second signal representative of the current flowing through at least one element of the converter. The control device is adapted to control the closing of said switch according to said first signal and comprises a synchronizer adapted to synchronize the start of the ramp voltage with the zero crossing of said second signal. | 02-02-2012 |
| 20120026765 | CONTROL DEVICE OF A SWITCHING POWER SUPPLY - A control device controls a switching converter having an input alternating supply voltage and a regulated direct voltage at the output terminal. The converter comprises a switch and the control device is adapted to control the on time period and the off time period of said switch for each cycle. The control device has a first input signal representative of the current flowing through at least one element of the converter and comprises a zero crossing detector adapted to detect at least one pair of first and second zero crossings of said first signal for each switching cycle, said second zero crossing immediately following the first zero crossing and occurring in opposite direction with respect to the first zero crossing. The control device comprises a synchronizer adapted to synchronize the start of the on period with each second zero crossing of said first signal. | 02-02-2012 |
| 20120025745 | CONTROL CIRCUIT OF AN ELECTRIC MOTOR WITH A MEASURE DELAY COMPENSATION AND MOTOR SYSTEM COMPRISING THE CIRCUIT - A control circuit controls an electric motor and includes: a measuring device configured to measure a first phase current of the motor and provide a corresponding first analog signal; an analog-to-digital converter structured to convert the first analog signal into a first digital signal; a conversion module for generating a first converted digital signal representative of the first digital signal expressed in a rotating reference system; a node structured to compare the first converted digital signal into a first reference signal and generate a first error signal; and a measure control circuit structured to provide a timing signal of the analog-to-digital converter depending on the first error signal and a time delay introduced by the measuring device. | 02-02-2012 |
| 20120025344 | TRACEABLE INTEGRATED CIRCUITS AND PRODUCTION METHOD THEREOF - An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible. | 02-02-2012 |
| 20120025166 | METHOD OF FABRICATING NANOSIZED FILAMENTARY CARBON DEVICES OVER A RELATIVELY LARGE-AREA - Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material. | 02-02-2012 |
| 20120024389 | INTEGRATED ELECTROMAGNETIC ACTUATOR, IN PARTICULAR ELECTROMAGNETIC MICRO-PUMP FOR A MICROFLUIDIC DEVICE BASED ON MEMS TECHNOLOGY, AND MANUFACTURING PROCESS - An integrated electromagnetic actuator comprising: a first structural layer; a flexible membrane, extending over the first structural layer and comprising regions of ferromagnetic material; a chamber, delimited between the first structural layer and the flexible membrane; a winding, comprising a plurality of turns of conductive material and extending within the first structural layer; and a core element made of ferromagnetic material, extending within the first structural layer, inside the winding. | 02-02-2012 |
| 20120018819 | PROCESS FOR MANUFACTURING A MICROMECHANICAL STRUCTURE HAVING A BURIED AREA PROVIDED WITH A FILTER - A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity. | 01-26-2012 |
| 20120014057 | INTEGRATED POWER ADAPTER SYSTEM FOR PORTABLE COMPUTERS - An integrated power adapter system for a portable computer may include a power adapter for providing power to the portable computer, extractable elements for connection to an external socket, and a dissipation grid for reducing the temperature of the cover screen. The power adapter system may be a slim power adapter system being removable from and integrated with the cover screen of the portable computer. | 01-19-2012 |
| 20120009722 | ARRAY OF MUTUALLY INSULATED GEIGER-MODE AVALANCHE PHOTODIODES, AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region. | 01-12-2012 |
| 20120008603 | CONTENTION BASED PERIOD BEAMFORMING - Contention based period beamforming includes the establishment of synchronized communications between a beamforming initiator and a beamforming responder to precisely define a start time for beamforming training. Synchronization between the beamforming initiator and beamforming responder begins with the sending of control information to the responder so that the start of the beamforming process will be synchronized. With beamforming training synchronized, beamforming is initiated using the sector sweep process. | 01-12-2012 |
| 20120007663 | INTEGRATED CIRCUIT WITH DEVICE FOR ADJUSTMENT OF THE OPERATING PARAMETER VALUE OF AN ELECTRONIC CIRCUIT AND WITH THE SAME ELECTRONIC CIRCUIT - An integrated circuit includes an electronic circuit and a device for adjustment of the operating parameter value of the electronic circuit. The electronic circuit comprises a resistive stage. The device comprises a first circuit portion adapted to adjust said operating parameter when the device is active and the electronic circuit is inactive, and adapted to be inactive when the electronic circuit is active, and a second circuit portion adapted to determine the active or inactive state of the device in response to the value of an external control signal. The integrated circuit comprises a first external terminal for the connection to ground, a second external terminal for inputting said control signal, a further external terminal for inputting a further external signal and a deactivation circuit driven by said further external signal to deactivate the electronic circuit when the device is active. | 01-12-2012 |
| 20120007150 | INTEGRATED DEVICE OF THE TYPE COMPRISING AT LEAST A MICROFLUIDIC SYSTEM AND FURTHER CIRCUITRY AND CORRESPONDING INTEGRATION PROCESS - An embodiment relates to a device integrated on a semiconductor substrate of a type comprising at least one first portion for the integration of at least one microfluidic system, and a second portion for the integration of an additional circuitry. The microfluidic system comprises at least one cavity realized in a containment layer of the integrated device closed on top by at least one portion of a polysilicon layer, this polysilicon layer being a thin layer shared by the additional circuitry and the closing portion of the cavity realizing a piezoresistive membrane for the microfluidic system. | 01-12-2012 |
| 20120006114 | MICROELECTROMECHANICAL GYROSCOPE WITH OPEN LOOP READING DEVICE AND CONTROL METHOD - A microelectromechanical gyroscope that includes a first mass oscillatable according to a first axis; an inertial sensor, including a second mass, drawn along by the first mass and constrained so as to oscillate according to a second axis, in response to a rotation of the gyroscope; a driving device coupled to the first mass so as to form a feedback control loop and configured to maintain the first mass in oscillation at a resonance frequency; and an open-loop reading device coupled to the inertial sensor for detecting displacements of the second mass according to the second axis. The driving device includes a read signal generator for supplying to the inertial sensor at least one read signal having the form of a square-wave signal of amplitude that sinusoidally varies with the resonance frequency. | 01-12-2012 |
| 20120003921 | SOLUTION FOR THE SCALABILITY OF BROADCAST FORWARDING IN VEHICULAR NETWORKS BY MAP-REFERENCED INFORMATION ON NODE POSITION - An embodiment of an apparatus includes a receiver operable to receive a message, and a processor operable to determine whether to broadcast the message. For example, the receiver and processor may be disposed on a first vehicle, and the receiver may receive the message from a second vehicle, where the message includes information related to a traffic-related event. The processor may determine whether to broadcast the message to other vehicles based on, e.g., the location of the first vehicle, the location of the second vehicle, the location of the event, or whether the processor has received the message more than once. The processor may determine not to broadcast the message if, based on these or other factors, it determines that the benefit of broadcasting the message is outweighed by the potential of the message, if broadcast, to “clog” a channel over which such traffic-related-event messages are broadcast. | 01-05-2012 |
| 20120002479 | CIRCUIT FOR THE OPTIMIZATION OF THE PROGRAMMING OF A FLASH MEMORY - A non volatile memory device is provided. The memory device includes a plurality of memory cells and programming means. The programming circuitry is configured to select a group of memory cells, receive a first data word and program memory cells of the selected group based on the data word. the program means includes a program circuit configured to receive at least one second data word, and, for each second data word, select a corresponding portion of memory cells of the group and send a program current in parallel to discriminated memory cells of the portion based on the corresponding second data word during a corresponding program phase. The memory device further includes an optimization circuit configured to generate said at least one second data word from the first data word. Each of said at least one second data word is such to cause during each program phase that the number of discriminated memory cells is maximized compatibly with a maximum predetermined limit of the total program current provided by the program circuit. | 01-05-2012 |
| 20120002473 | BACKGROUND POWER CONSUMPTION REDUCTION OF ELECTRONIC DEVICES - An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition. | 01-05-2012 |
| 20120002460 | DYNAMICALLY CONFIGURABLE SRAM CELL FOR LOW VOLTAGE OPERATION - An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively. The memory device may further include biasing means for modifying a value of a threshold voltage of at least one of the main transistors to a first threshold voltage value or to a second threshold voltage value and for modifying a threshold voltage value of at least one of the complementary transistors to the second threshold voltage value or to the first threshold voltage value during a write operation of the first logic value or of the second logic value, respectively, in the memory cell. | 01-05-2012 |
| 20120002459 | 5T SRAM MEMORY FOR LOW VOLTAGE APPLICATIONS - An embodiment of a memory device of SRAM type integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells each for storing a binary data having a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of field effect main storage transistors coupled to the main terminal for maintaining the main terminal at the reference voltage corresponding to the stored logic value or to a complement thereof, a set of field effect complementary storage transistors coupled to the complementary terminal for maintaining the complementary terminal at the reference voltage corresponding to the complement of the logic value associated with the main terminal—and a field effect access transistor for accessing the main terminal. The chip includes an isolated well, the access transistor and at least one of the complementary storage transistors being formed in the isolated well. | 01-05-2012 |
| 20120002381 | METHOD FOR MANUFACTURING A LIQUID-TIGHT ELECTRONIC DEVICE, AND LIQUID-TIGHT ELECTRONIC DEVICE - A method for manufacturing a liquid-tight electronic device includes: providing a first printed-circuit board having a first connector; providing a supporting structure having a first opening; forming a first assembly by coupling the supporting structure and the first printed-circuit board in such a way that the first connector extends through the first opening and delimits a bottom gap; and forming a second assembly having a protective shell. The method further includes: depositing a first layer of liquid resin within the bottom gap, and hardening the first layer of liquid resin; depositing a second layer of liquid resin within the second assembly; coupling the first and second assemblies in such a way that the second layer of liquid resin hermetically closes a first interstitial area between the protective shell and the supporting structure; and hardening the second layer of liquid resin. | 01-05-2012 |
| 20120001679 | HIGH-PRECISION RESISTOR AND TRIMMING METHOD THEREOF - An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion. | 01-05-2012 |
| 20120001662 | CONTROL OF A RESONANT SWITCHING SYSTEM WITH MONITORING OF THE WORKING CURRENT IN AN OBSERVATION WINDOW - Controlling a resonant switching system, which includes a first switch and a second switch in a half-bridge configuration for driving a resonant load. A corresponding control system includes command means for switching on and switching off the switches alternatively according to a working frequency of the switching system. The control system includes detection means for detecting a zeroing of a working current being supplied by the switching system to the resonant load in a temporal observation window; the observation window follows each switching off of at least one of the switches, and has a length equal to a fraction of a working period of the switching system. Correction means are then provided for modifying the working frequency in response to each detection of the zeroing in the observation window. | 01-05-2012 |
| 20120001593 | APPARATUS FOR POWER WIRELESS TRANSFER BETWEEN TWO DEVICES AND SIMULTANEOUS DATA TRANSFER - A system for the wireless transfer of power includes a first device connected to a power supply source and provided with a first resonant circuit at a first frequency, a second device comprising at least one battery, provided with a second resonant circuit at said first frequency, arranged at a distance smaller than the wavelength associated with said first frequency and not provided with wires for the electrical connection with said first device. The first device is adapted to transfer a first signal representing the power to be sent to the second device for charging said at least one battery and comprises means adapted to modulate the frequency of said first signal for transferring data from the first device to the second device simultaneously with the power transfer. The second device comprises means adapted to demodulate the received signal, corresponding to the first signal sent from the first device, to obtain the transmitted data. | 01-05-2012 |
| 20120001224 | IGBT TRANSISTOR WITH PROTECTION AGAINST PARASITIC COMPONENT ACTIVATION AND MANUFACTURING PROCESS THEREOF - An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region. | 01-05-2012 |
| 20120000287 | MICROELECTROMECHANICAL THREE-AXIS CAPACITIVE ACCELEROMETER - A micromechanical structure for a MEMS three-axis capacitive accelerometer is provided with: a substrate; a single inertial mass having a main extension in a plane and arranged suspended above the substrate; and a frame element, elastically coupled to the inertial mass by coupling elastic elements and to anchorages, which are fixed with respect to the substrate by anchorage elastic elements. The coupling elastic elements and the anchorage elastic elements are configured so as to enable a first inertial movement of the inertial mass in response to a first external acceleration acting in a direction lying in the plane and also a second inertial movement of the inertial mass in response to a second external acceleration acting in a direction transverse to the plane. | 01-05-2012 |
| 20110320916 | METHOD OF LIST DECODING AND RELATIVE DECODER FOR LDPC CODES - A method is for generating, for each check node related to a parity check equation of a LDPC code, signals representing a first output table of corrected values of symbols of a word received through a communication channel and transmitted according to the LDPC code, and signals representing a second output table of the logarithm of the ratio between the respective probability of correctness of the values of same coordinates in the first output table and their corresponding maximum probability of correctness. The method is implemented by processing the components of a first input table of values of a Galois Field of symbols that may have been transmitted and of a second input table of corresponding probability of correctness of each value. | 12-29-2011 |
| 20110320795 | POWER MANAGEMENT USING CONSTRAINTS IN MULTI-DIMENSIONAL PARAMETER SPACE - An embodiment of a method and system are provided for managing both system resources and power consumption of a computer system, involving different layers of the system: an application layer, a middle layer where the operating system is running and where a power manager is provided, and a hardware layer used for communicating with the hardware devices. Hardware devices have different operating modes which provide distinct trade-offs between performances and power consumption. Performance requirements defined at the level of the application layer, as well as the device power status of the system, set constraints on the system resources. The middle layer power manager may be in charge of retrieving performance requirements in form of constraints set on system parameters, aggregating these constraints opportunely and communicating corresponding information to the device drivers which may then select a best operating mode. | 12-29-2011 |
| 20110320669 | COMMUNICATION SYSTEM AND METHOD - A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted. | 12-29-2011 |
| 20110319015 | METHOD FOR VERIFYING THE ALIGNMENT BETWEEN INTEGRATED ELECTRONIC DEVICES - A method for verifying alignment between first and second integrated devices coupled together using a reference and a coupling capacitor, including: transmitting a reference signal on a transmission electrode of the reference capacitor; receiving a coupling signal on a reception electrode of the reference capacitor; amplifying the coupling signal, generating a reception reference signal; generating a reception control signal as a function of the reception reference signal; transmitting a communication signal on an electrode of the coupling capacitor; receiving a reception signal on an electrode of the coupling capacitor; amplifying the reception signal, generating a first compensated signal; controlling a level of amplification of amplifying the coupling signal and the reception signal as a function of the reception control signal; and detecting a possible misalignment between the first and second devices based on an amplitude of the communication signal and an amplitude of the compensated signal. | 12-29-2011 |
| 20110319014 | ELECTRONIC CIRCUIT FOR COMMUNICATING THROUGH CAPACITIVE COUPLING - A device and method to compensate for distortions of amplitude that afflict systems for communicating through capacitive coupling. A circuit includes a first transmitter stage, a first receiver stage, and a first coupling capacitor, coupled between the first transmitter stage and the first receiver stage. The first receiver stage includes a calibration amplifier of a variable-gain type coupled between the first coupling capacitor and an output of the electronic circuit. The electronic circuit includes a reference channel formed by: a transmission calibration stage; a reception calibration stage; and a reference capacitor coupled between the transmission calibration stage and the reception calibration stage. The reception calibration stage includes: a reception amplifier of a variable-gain type, having an input coupled to the reference capacitor, and a gain controller, having an input coupled to an output of the reception amplifier and an output coupled to control terminals of the reception and calibration amplifiers. | 12-29-2011 |
| 20110318840 | FLUIDIC CARTRIDGE FOR DETECTING CHEMICALS IN SAMPLES, IN PARTICULAR FOR PERFORMING BIOCHEMICAL ANALYSES - A fluidic cartridge for detecting chemicals, formed by a casing, hermetically housing an integrated device having a plurality of detecting regions to bind with target chemicals; part of a supporting element, bearing the integrated device; a reaction chamber, facing the detecting regions; a sample feeding hole and a washing feeding hole, self-sealingly closed; fluidic paths, which connect the sample feeding and washing feeding holes to the reaction chamber; and a waste reservoir, which may be fluidically connected to the reaction chamber by valve elements that may be controlled from outside. The integrated device is moreover connected to an interface unit carried by the supporting element, electrically connected to the integrated device and including at least one signal processing stage and external contact regions. | 12-29-2011 |
| 20110316173 | ELECTRONIC DEVICE COMPRISING A NANOTUBE-BASED INTERFACE CONNECTION LAYER, AND MANUFACTURING METHOD THEREOF - An electronic device including a first region belonging to a semiconductor device having a first surface; a second region having a second surface; and an adhesion layer, set between the first and second regions, including first fibrils each having respective first and second ends. The first fibrils extend between the first and second surfaces and are fixed in a chemico-physical way to the first and second surfaces at the respective first and second ends. | 12-29-2011 |
| 20110310958 | SYSTEM FOR ENTROPY DECODING OF H.264 VIDEO FOR REAL TIME HDTV APPLICATIONS - An embodiment relates to a decoder for decoding CABAC encoded video data in real time for HDTV applications. The decoder comprises a binary arithmetic decoder block for converting an input bit stream into a bin string, a context memory for storing a plurality of context values, and a plurality of finite state machines. Each of the finite state machines is adapted for decoding a particular one of the H.264 syntax elements by providing the binary arithmetic decoder block with an index of the relevant context value within the context memory and by converting the resulting bin stream into a value of the current syntax element. In this manner, a performance of one bin per cycle may be achieved. | 12-22-2011 |
| 20110309532 | SEMICONDUCTOR STRUCTURE WITH ALIGNMENT CONTROL MASK - A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction. | 12-22-2011 |
| 20110305096 | CIRCUIT FOR READING NON-VOLATILE MEMORY CELLS AND MEMORY SYSTEM COMPRISING THE CIRCUIT - A circuit for reading memory cells includes: a sense node connectable to a memory cell; a sense device connected to the sense node and configured to be activated in a precharging step which precedes a cell reading step and to provide such an output signal to assume logic values dependant on an electric signal present at the sense node; a precharging circuit connected to said sense node and configured to be activated to make said sense node reach a precharging voltage and to be deactivated upon switching said output signal occurred in the precharging step. | 12-15-2011 |
| 20110305092 | NON-VOLATILE MEMORY DEVICE WITH CONTROLLED DISCHARGE - An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material is proposed. The memory device includes a plurality of sectors of memory cells each one being formed in a respective well of the chip; each sector includes a plurality word lines each one for accessing a corresponding block of memory cells of the sector; the memory device includes a first biasing line of the wells and a second biasing line of the word lines, biasing circuitry for providing a first bias voltage to the first biasing line and a second bias voltage to the second biasing line, selection circuitry for selectively connecting the first biasing line to the well of at least one selected sector and for selectively connecting the second biasing line to at least one selected word line of each selected sector, first charge transfer circuitry for bringing the first biasing line from the first bias voltage to a target voltage according to a pilot transient trend, the target voltage being between the first bias voltage and the second bias voltage, second charge transfer circuitry for bringing the second biasing line from the second bias voltage to the target voltage. The second charge transfer circuitry includes circuitry for binding the second biasing line to bring itself from the second bias voltage to the target voltage according to a transient trend being scaled with respect to the pilot transient trend. | 12-15-2011 |
| 20110298405 | METHOD OF CONTROLLING A THREE-PHASE PERMANENT MAGNET SYNCHRONOUS MOTOR FOR REDUCING ACOUSTIC NOISE AND RELATIVE CONTROL DEVICE - A method of controlling a synchronous motor that may include windings and a power driving stage coupled to the windings, may include using a feedback loop including using a feedback circuit coupled to the windings to generate current feedback components, using current controllers for generating respective voltage signals, and using an anti-transform circuit for generating control signals for the power driving stage. Using the feedback loop may include generating additional compensation signals for compensating the control signals, and adding the additional compensation signals from the current controllers by one of generating the additional compensation signals as quadrature and direct voltage compensation signals and adding them to the voltage signals to generate compensated quadrature and direct signals, and supplying the compensated quadrature and direct signals to the power driving stage by providing the compensated quadrature and direct signals to the anti-transform circuit. | 12-08-2011 |
| 20110298087 | ELECTRICAL FUSE DEVICE BASED ON A PHASE-CHANGE MEMORY ELEMENT AND CORRESPONDING PROGRAMMING METHOD - A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST. | 12-08-2011 |
| 20110291679 | TESTING INTEGRATED CIRCUITS - A method of testing integrated circuits is provided. The method includes establishing at least one first physical communication channel between a test equipment and a respective group of integrated circuits under test by having probes of the test equipment contacting at least one corresponding physical contact terminal of each integrated circuit of the respective group. The method further includes having the test equipment exchanging, over the at least one first physical communication channel, the same test stimuli with each integrated circuit of the group. The method still further includes having each integrated circuit of the group establishing a corresponding second physical communication channel with the test equipment by having at least one physical contact terminal of the integrated circuit contacted by a corresponding probe of the test equipment. The method further includes having each integrated circuit of the group exchanging, over the second physical communication channel, a corresponding test response signal based on the received test stimuli with the test equipment. The test stimuli are exchanged by modulating at least one first carrier wave based on the test stimuli; the at least one first carrier wave has at least one first frequency. The test response signals of each integrated circuit of the group are exchanged by modulating at least one respective second carrier wave based on the test response signals; each second carrier wave have at least one respective second frequency. | 12-01-2011 |
| 20110291103 | TRENCH SIDEWALL CONTACT SCHOTTKY PHOTODIODE AND RELATED METHOD OF FABRICATION - A Schottky photodiode may include a monocrystalline semiconductor substrate having a front surface, a rear surface, and a first dopant concentration and configured to define a cathode of the Schottky photodiode, a doped epitaxial layer over the front surface of the monocrystalline semiconductor substrate having a second dopant concentration less than the first dopant concentration, and parallel spaced apart trenches in the doped epitaxial layer and having of a depth less than a depth of the doped epitaxial layer. The Schottky photodiode may include a metal filler in the parallel spaced apart trenches to form a Schottky rectifying contact with the doped epitaxial layer, an anode current distributor metal layer on a surface of the doped epitaxial layer and in electrical contact with the metal filler of the parallel spaced apart trenches, a dielectric passivation layer on the anode current distributor metal layer, and a conductive metal layer over the rear surface of the monocrystalline semiconductor substrate and configured to provide an ohmic contact with the cathode. | 12-01-2011 |
| 20110289266 | GARBAGE COLLECTION IN STORAGE DEVICES BASED ON FLASH MEMORIES - A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space. | 11-24-2011 |
| 20110289253 | INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP - Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue. | 11-24-2011 |
| 20110287363 | HIGH-RESOLUTION PHOTOLITHOGRAPHIC METHOD FOR FORMING NANOSTRUCTURES, IN PARTICULAR IN THE MANUFACTURE OF INTEGRATED ELECTRONIC DEVICES - A photolithographic process, wherein a photosensitive layer is formed on a surface of a body to be defined; the photosensitive layer is exposed through a photolithographic mask having zones with lower transparency and zones with higher transparency so as to obtain exposed portions and shielded portions of the photosensitive layer; selective portions of the photosensitive layer chosen between the exposed portions and the shielded portions of the photosensitive layer are removed; and portions of the body under the selective portions of the photosensitive layer are selectively removed. The composite layer includes photoresist and carbon nanotubes, which are embedded in the photoresist and extend in a direction generally transverse to, and in electrical contact with, the body. | 11-24-2011 |
| 20110285370 | DC-DC CONVERTER CIRCUIT - An embodiment of a voltage conversion unit is proposed. The voltage conversion unit comprises a switching DC-DC converter including an input terminal for receiving an input voltage from a source, a control terminal adapted to receive a pulse width modulated driving signal oscillating at a first frequency, and an output terminal for providing to a load an output voltage generated from the input voltage according to the driving signal. The voltage conversion unit further comprises a switching control unit configured to receive the output voltage and a reference voltage and to set a duty cycle of the driving signal based on a comparison between the output voltage and the reference voltage. The switching DC-DC converter and the switching control unit form a feedback loop having a loop gain defining a corresponding operating bandwidth of the voltage conversion unit. The load is configured to drain a current pulse train having a second frequency; the values of the first and second frequencies are such to cause the occurrence of beat oscillations at frequencies comprised within the operating bandwidth. The switching control unit comprises means for reducing the beat oscillations by increasing the loop gain at least for a frequency interval comprised within the operating bandwidth. | 11-24-2011 |
| 20110279936 | INTEGRATED CIRCUIT WITH DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit includes a substrate of semiconductive material, a first circuit environment made from the substrate which includes an output terminal and a first pair of power supply terminals for receiving a first power supply voltage applicable between the terminals. The integrated circuit also includes a second circuit environment made from the semiconductor substrate which includes an input terminal electrically coupled to the output terminal and also includes a second pair of power supply terminals for receiving a second power supply voltage applicable between the second pair of terminals of said second pair. The circuit further includes a device providing protection from electrostatic discharges which includes an integrated resistive device coupled between the input and output terminals. | 11-17-2011 |
| 20110279137 | PROBES FOR TESTING INTEGRATED ELECTRONIC CIRCUITS AND CORRESPONDING PRODUCTION METHOD - An embodiment of a method is proposed for producing cantilever probes for use in a test apparatus of integrated electronic circuits; the probes are configured to contact during the test corresponding terminals of the electronic circuits to be tested. An embodiment comprises forming probe bodies of electrically conductive materials. In an embodiment, the method further includes forming on a lower portion of each probe body that, in use, is directed to the respective terminal to be contacted, an electrically conductive contact region having a first hardness value equal to or greater than 300 HV; each contact region and the respective probe body form the corresponding probe. | 11-17-2011 |
| 20110278955 | LOW ON-RESISTANCE MOSFET IMPLEMENTED, BY-PASS DIODE OR CIRCUIT BREAKER AND RELATED SELF-POWERING AND CONTROL CIRCUIT - A MOSFET implemented self-powered current by-pass or circuit breaker device is based on the use of a high multiplication factor (HMF) inductive voltage booster, adapted to boost a voltage as low as few tens of mV up to several Volts, assisted by a start-up low multiplication factor (LMF) charge pump made with low threshold transistors for providing a supply voltage to a polarity inversion detecting comparator of the drain-to-source voltage difference of a power MOSFET connected in parallel to a DC source or string of series connected DC sources or battery, in series to other DC sources during normal operation of the parallel connected DC source or string of series connected DC sources or battery. The inductance for the high multiplication factor, inductive voltage booster for most of the considered power applications is on the order of a few pH and such a relatively send inductor may be included as a discrete component in a compact package or “system-in-package” of monolithically integrated circuits. | 11-17-2011 |
| 20110278568 | MANUFACTURING PROCESS OF INTEGRATED ELECTRONIC CIRCUITS AND CIRCUITS THEREBY OBTAINED - An embodiment of a manufacturing process of an integrated electronic circuit is proposed; the process comprises forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe and running an electric test of the electronic circuit. In an embodiment, the process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe. | 11-17-2011 |
| 20110275018 | CIRCUIT ARCHITECTURE ON AN ORGANIC BASE AND RELATED MANUFACTURING METHOD - A method comprises providing a bottom electrode, depositing, on the bottom electrode, an active material comprising a first structural portion having an absorption peak at a UV wavelength, wherein such first structural portion is photo-activatable at such wavelength and which is constituted by monomers or oligomers that, when irradiated at said wavelength, undergo a photo-polymerization and/or photo-cross-linking reaction, or constituted by a polymer that at a UV wavelength undergoes a photo-degradation reaction, and a second electrically active or activatable structural portion which is substantially transparent to such predetermined UV wavelength; exposing a portion of the active material, through a photomask, to UV radiation having such UV wavelength, with photo-activation of the exposed portion of such film; selectively removing either the exposed photo-activated portion or the non-exposed portion, with exposure of a respective portion of the bottom electrode; depositing a head electrode. | 11-10-2011 |
| 20110274299 | ENCAPSULATED MICRO-ELECTRO-MECHANICAL DEVICE, IN PARTICULAR A MEMS ACOUSTIC TRANSDUCER - An encapsulated micro-electro-mechanical device, wherein a MEMS chip is encapsulated by a package formed by a first, a second, and a third substrates that are bonded together. The first substrate has a main surface bearing the MEMS chip, the second substrate is bonded to the first substrate and defines a chamber surrounding the MEMS chip, and the third substrate is bonded to the second substrate and upwardly closes the chamber. A grid or mesh structure of electrically conductive material is formed in or on the third substrate and overlies the MEMS chip; the second substrate has a conductive connection structure coating the walls of the chamber, and the first substrate incorporates an electrically conductive region, which forms, together with the conductive layer and the grid or mesh structure, a Faraday cage. | 11-10-2011 |
| 20110272561 | METHOD OF DETECTING IMPINGING POSITION OF PHOTONS ON A GEIGER-MODE AVALANCHE PHOTODIODE, RELATED GEIGER-MODE AVALANCHE PHOTODIODE AND FABRICATION PROCESS - A Geiger-mode avalanche photodiode may include an anode, a cathode, an output pad electrically insulated from the anode and the cathode, a semiconductor layer having resistive anode and cathode regions, and a metal structure in the semiconductor layer and capacitively coupled to a region from the resistive anode and resistive cathode regions and connected to the output pad. The output pad is for detecting spikes correlated to avalanche events. | 11-10-2011 |
| 20110269044 | SYSTEM FOR GENERATING ELECTRIC POWER WITH MICRO FUEL CELLS AND CORRESPONDING PROCESS - Embodiment of a system for generating electric power with micro fuel cells comprising at least one first micro cell and at least one second micro cell, each micro cell having an anode and a cathode with a membrane being sandwich-wise interposed, the system comprising a spacer element having an annular element that surrounds a cavity, said spacer element being associated with said anode of said first micro cell and with said anode of said second micro cell to realize a common diffusion chamber for the fuel of said first micro cell a of said second micro cell. | 11-03-2011 |
| 20110267725 | PROTECTION APPARATUS AGAINST ELECTROSTATIC DISCHARGES FOR AN INTEGRATED CIRCUIT AND RELATED INTEGRATED CIRCUIT - There is described a protection apparatus against electrostatic discharges for an integrated circuit; said integrated circuit comprises a radiofrequency or higher frequencies internal circuit. The internal circuit has a first and a second terminals for the output or the input of a radiofrequency or higher frequencies signal. The apparatus comprises first means for electrically connecting said first and second terminals of the internal circuit to at least a PAD and the integrated circuit comprises at least a first and a second supply circuital lines and at least a first and a second protection devices against electrostatic discharges connected to said first and second supply lines. First means have a resistive component and each of said first and second protection devices against the electrostatic discharges have a parasitic capacitive component. The apparatus comprises second means configured to connect said first means and said first and second protection devices against the electrostatic discharges to at least a common circuital point preventing the resistive component of said first means or said internal circuit from combining with the parasitic capacitive components of said first and second protection devices against the electrostatic discharges. | 11-03-2011 |
| 20110267086 | TEST CIRCUIT OF AN INTEGRATED CIRCUIT ON A WAFER - A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus. | 11-03-2011 |
| 20110264407 | INERTIAL DEVICE WITH PEDOMETER FUNCTION AND PORTABLE ELECTRIC APPLIANCE INCORPORATING SAID INERTIAL DEVICE - An inertial device that is integratable in a portable electronic device includes: an inertial sensor for generating at least one raw acceleration signal in response to accelerations caused by movements of walking and running of a user of the pedometer; and a processing unit, associated to the inertial sensor for counting a number of steps of the user of the pedometer on the basis of the raw acceleration signal. The inertial sensor and the processing unit are both encapsulated within a single package for integrated circuits, which can be coupled to a circuit board of an electronic device and is provided with at least one connection terminal for making the number of steps available to the outside world. | 10-27-2011 |
| 20110260974 | MANUAL POINTING DEVICE FOR A COMPUTER SYSTEM WITH INERTIAL CLICK EVENT DETECTION AND CORRESPONDING CLICK EVENT DETECTION METHOD - A manual pointing device for a computer system, the device having at least one key that can be actuated manually by a user, a click-event detection module coupled to the key to detect actuation thereof on first, second, and third detection axes via an inertial sensing circuit elastically coupled to a casing with a board, the inertial-sensor circuit structured to be carried on the board so as to oscillate and to rotate about the second detection axis. | 10-27-2011 |
| 20110260332 | MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME - A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via. | 10-27-2011 |
| 20110260314 | DIE PACKAGE AND CORRESPONDING METHOD FOR REALIZING A DOUBLE SIDE COOLING OF A DIE PACKAGE - A die package is provided, including a die positioned on and in direct contact with a first heat sink element, and also including a package case and leads made of conductive material, protruding from the package case. The die package further includes a second heat sink element shaped as a spring element, in contact between the die and the leads, and emerging from a side of the package case opposite the first heat sink element. | 10-27-2011 |
| 20110258499 | SYSTEM FOR PERFORMING THE TEST OF DIGITAL CIRCUITS - A system performs the test of a digital circuit. The system comprises a controller configured for executing the test of the digital circuit, a memory configured for storing a status of the digital circuit, and a state machine configured for controlling, before the execution of the test, the storage into the memory of the status of the digital circuit and configured for controlling, after the execution of the test, the restore into the digital circuit of the status stored into the memory. | 10-20-2011 |
| 20110254580 | METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN FOR SEMICONDUCTOR DEVICE TESTING - A method provides an improved checking of repeatability and reproducibility of a measuring chain, in particular for quality control by semiconductor device testing. The method includes testing steps provided for multiple and different devices to be subjected to measurement or control through a measuring system that includes at least one chain of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement or control. Advantageously, the method comprises checking repeatability and reproducibility of each type of unit that forms part of the measuring chain and, after the checking, making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement or control. | 10-20-2011 |
| 20110248720 | TESTING SYSTEM FOR INTEGRATED CIRCUITS - A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit. | 10-13-2011 |
| 20110248397 | SEMICONDUCTOR DEVICE HAVING STACKED COMPONENTS - A semiconductor device includes at least one first component ( | 10-13-2011 |
| 20110244344 | DEVICE FOR PRODUCING GASEOUS HYDROGEN, SYSTEM FOR PRODUCING ELECTRIC POWER, AND CORRESPONDING METHOD FOR PRODUCING GASEOUS HYDROGEN - An embodiment of a device for producing gaseous hydrogen comprising a reaction chamber having a solution with catalyst, a tank chamber comprising a reactant suitable for reacting with the solution with catalyst for the production of gaseous hydrogen, the tank chamber being provided with removable partition means suitable for defining a first storage chamber, for the reactant, and a second storage chamber, for the reaction by-products, the partition means being adjustable so that the volume of the first storage chamber and the volume of the second storage chamber are variable in a complementary way with respect to each other. | 10-06-2011 |
| 20110241158 | ISOLATION TRENCHES - A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having a protective cap. The method allows obtaining, in an easy way, filled isolation trenches exhibiting excellent functional and morphological properties. The method therefore allows the obtainment of effective filled isolation trenches which help provide elevated, reliable and stable isolation properties. | 10-06-2011 |
| 20110241149 | GEIGER-MODE AVALANCHE PHOTODIODE WITH HIGH SIGNAL-TO-NOISE RATIO, AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of a geiger-mode avalanche photodiode includes: a body of semiconductor material, having a first surface and a second surface; a cathode region of a first type of conductivity, which extends within the body; and an anode region of a second type of conductivity, which extends within the cathode region and faces the first surface, the anode and cathode regions defining a junction. The anode region includes at least two subregions, which extend at a distance apart within the cathode region starting from the first surface, and delimit at least one gap housing a portion of the cathode region, the maximum width of the gap and the levels of doping of the two subregions and of the cathode region being such that, by biasing the junction at a breakdown voltage, a first depleted region occupies completely the portion of the cathode region within the gap. | 10-06-2011 |
| 20110230155 | MILLIMETER WAVE OSCILLATOR - An oscillator is described, comprising at least one transistor having a first terminal connected to a power supply voltage. The oscillator comprises at least one inductive element connected to a second terminal of the transistor and to a bias voltage and at least one capacitive element coupled between a third terminal of the transistor and ground. The oscillator further comprises means to collect the output signal of said oscillator on the second terminal of the transistor. The oscillator is of the millimeter wave type, i.e., both the inductive element and the capacitive element are sized such that the oscillation frequency is between 30 and 300 gigahertz. | 09-22-2011 |
| 20110223738 | FORMING PHASE CHANGE MEMORY CELLS - Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore. | 09-15-2011 |
| 20110221498 | SYSTEM FOR SYNCHRONIZING OPERATION OF A CIRCUIT WITH A CONTROL SIGNAL, AND CORRESPONDING INTEGRATED CIRCUIT - A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops. | 09-15-2011 |
| 20110218727 | METHOD AND ASSOCIATED DEVICE FOR SENSING THE AIR/FUEL RATIO OF AN INTERNAL COMBUSTION ENGINE - A method of sensing the air/fuel ratio in a combustion chamber of an internal combustion engine that may be easily implemented by a respective low-cost device includes a pressure sensor and a learning machine that generates a sensing signal representing the air/fuel ratio by processing the waveform of the pressure in at least one cylinder of the engine. In practice, the learning machine extracts characteristic parameters of the waveform of the pressure and as a function of a certain number of them generates the sensing signal. | 09-08-2011 |
| 20110213944 | SYNCHRONIZATION SYSTEM AND RELATED INTEGRATED CIRCUIT - A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency. | 09-01-2011 |
| 20110212566 | OPTICALLY CONTROLLED ELECTRICAL-SWITCH DEVICE BASED UPON CARBON NANOTUBES AND ELECTRICAL-SWITCH SYSTEM USING THE SWITCH DEVICE - Described herein is an optically controlled electrical-switch device which includes a first current-conduction terminal and a second current-conduction terminal, and a carbon nanotube connected between the first and the second current-conduction terminals, the carbon nanotube being designed to be impinged upon by electromagnetic radiation and having an electrical conductivity that can be varied by varying the polarization of the electromagnetic radiation incident thereon. In particular, the carbon nanotube may for example, in given conditions of electrical biasing, present a high electrical conductivity when it is impinged upon by electromagnetic radiation having a given wavelength and a polarization substantially parallel to the axis of the carbon nanotube itself, and a reduced electrical conductivity when it is impinged upon by electromagnetic radiation having a given wavelength and a polarization substantially orthogonal to the axis of the carbon nanotube itself. | 09-01-2011 |
| 20110211316 | TAILORABLE FLEXIBLE SHEET OF MONOLITHICALLY FABRICATED ARRAY OF SEPARABLE CELLS EACH COMPRISING A WHOLLY ORGANIC, INTEGRATED CIRCUIT ADAPTED TO PERFORM A SPECIFIC FUNCTION - A flexible sheet of organic polymer material, may include a monolithically fabricated array of one or more types of cells juxtaposed among them to form a multi-cell sheet. Each cell may include a self consistent, organic base integrated circuit, replicated in each cell of same type of the array, and shares, in common with other cells of same type, at least a conductor layer of either an electrical supply rail of the integrated circuit or of an input/output of the integrated circuit. A piece of the multi-cell, sheet including any number of self consistent integrated circuit cells, may be severed from the multi-cell sheet by cutting the sheet along intercell boundaries or straight lines, with a reduced affect on the operability of any cell spared by the cutting. | 09-01-2011 |
| 20110211098 | NOISE FILTER FOR BAYER PATTERN IMAGE DATA - A method of filtering an image filter is disclosed. The filter is provided for a digital camera including image sensors sensitive to light, a color filter placed over sensitive elements of the sensors and patterned according to a Bayer mosaic pattern layout and an interpolation algorithm joining together the digital information provided by differently colored adjacent pixels in said Bayer pattern. The filter is adaptive and includes a noise level computation block for operating directly on a said Bayer pattern data set of for each color channel thus removing noise while simultaneously preserving picture detail. | 09-01-2011 |
| 20110210722 | INTEGRATED MAGNETIC SENSOR FOR DETECTING HORIZONTAL MAGNETIC FIELDS AND MANUFACTURING PROCESS THEREOF - The integrated magnetic sensor for detecting an external magnetic field, is formed by a body of semiconductor material having a surface; an insulating layer covering the body of semiconductor material; a magnetically sensitive region, for example a Hall cell, extending inside the body; and a concentrator of ferromagnetic material, extending on the Hall cell and having a planar portion extending parallel to the surface of the substrate on the insulating layer. The concentrator terminates with a tip protruding peripherally from, and transversely to, the planar portion toward the Hall cell. When the magnetically sensitive region is a sensing coil of a fluxgate sensor, it is formed on the substrate, embedded in the insulating layer, and the tip of the concentrator can reach as far as the sensing coil. | 09-01-2011 |
| 20110209524 | INTEGRATED CHEMICAL SENSOR FOR DETECTING ODOROUS MATTERS - A cartridge-like chemical sensor is formed by a housing having a base and a cover fixed to the base and provided with an input opening, an output hole and a channel for a gas to be analyzed. The channel extends in the cover between the input opening and the output hole and faces a printed circuit board carrying an integrated circuit having a sensitive region open toward the channel and of a material capable to bind with target chemicals in the gas to be analyzed. A fan is arranged in the housing, downstream of the integrated device, for sucking the gas after being analyzed, and is part of a thermal control system for the integrated circuit. | 09-01-2011 |
| 20110208028 | DEVICE FOR MEASURING IMPEDANCE OF BIOLOGIC TISSUES - A device for measuring impedance of biological tissue may include a pair of electrodes for contacting the biological tissue, and a drive circuit coupled to the pair of electrodes and configured to drive an alternating current (AC) through the biological tissue and to sense an AC voltage. The AC voltage is towards a reference voltage on at least one of the pair of electrodes. The device may include at least one single-ended amplitude modulation (AM) demodulator configured to demodulate the AC voltage and to generate a corresponding baseband voltage representing the impedance, and an output circuit configured to generate output signals representative of DC and AC components of the baseband voltage. | 08-25-2011 |
| 20110205028 | ELECTRONIC COMMUNICATIONS DEVICE WITH ANTENNA AND ELECTROMAGNETIC SHIELD - An embodiment of an electronic communications device, including: a body of semiconductor material defining at least one integrated electronic circuit and having a top surface; an electromagnetic shield; a radiant element; and a capacitive element formed by a first electrode and a second electrode, the radiant element being set on the top surface and being ohmically coupled to the first electrode and the second electrode by means of a first connection element and a second connection element, respectively, the electromagnetic shield being set between the radiant element and the top surface and forming at least the second electrode. | 08-25-2011 |
| 20110202799 | PROCESS FOR MAKING AN ELECTRIC TESTING OF ELECTRONIC DEVICES - The disclosure relates to a process for making an electric testing of electronic devices DUT, of the type comprising the steps of: connecting at least one electronic device DUT to an automatic testing apparatus or ATE apparatus suitable for making the testing of digital circuits; sending, through said ATE apparatus, control signals for the electric testing to said electronic device DUT. Advantageously, the process also comprises the steps of: making the electric testing of said electronic device DUT through at least one reconfigurable digital interface RDI connected to said ATE apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information; and sending from said electronic device DUT to said ATE apparatus response messages, if any, containing measures, failure information and data in response to said control signals and through said digital communication channel. | 08-18-2011 |
| 20110199794 | METHOD FOR CONTROLLING A SWITCHING REGULATOR AND RELATED SWITCHING REGULATOR - An embodiment of a power-supply controller comprises a switching-control circuit, an error amplifier, and a signal generator. The switching-control circuit is operable to control a switch coupled to a primary winding of a transformer, and the error amplifier has a first input node operable to receive a feedback signal, a second input node operable to receive a comparison signal, and an output node operable to provide a control signal to the switching-control circuit. The signal generator is operable to generate either the feedback signal or the comparison signal in response to a compensation signal that is isolated from a secondary winding of the transformer and that is proportional to a load current through a conductor disposed between the secondary winding and a load. | 08-18-2011 |
| 20110197675 | MICROELECTROMECHANICAL GYROSCOPE WITH INVERSION OF ACTUATION FORCES, AND METHOD FOR ACTUATING A MICROELECTROMECHANICAL GYROSCOPE - A microelectromechanical gyroscope includes a body and a driving mass, which is movable with respect to the body according to a driving axis and is capacitively coupled to the body. The gyroscope moreover includes a driving device, which forms a microelectromechanical control loop with the body and the driving mass and is configured for supplying to the driving mass driving signals having a common-mode component and respective differential components so as to maintaining the driving mass in oscillation according to the driving axis. The driving device is provided with an actuation stage configured for inverting in a controlled way the sign of the differential components of the driving signals. | 08-18-2011 |
| 20110196615 | Processing of biological signals - A method processes a signal by storing a template sequence composed of a number N of consecutive digital samples of the signal; calculating a sequence of extended sums that includes, for each digital sample, an extended sum of absolute values of differences between N most recent digital samples and the samples of the template sequence; detecting minima of the sequence of extended sums; and estimating a period of the signal as a time interval between two consecutive minima of the sequence of extended sums. The method also estimates the noise level of the signal as a ratio between most recently-detected minimum and maximum of said sequence of extended sums. The method also generates a reduced-noise replica of the signal as a weighted average of the template sequence and of the current samples of the signal processed between two consecutive minima of said extended sum, the weighted average being calculated using weights based on the estimated noise level. | 08-11-2011 |
| 20110193601 | FRACTIONAL TYPE PHASE-LOCKED LOOP CIRCUIT WITH COMPENSATION OF PHASE ERRORS - A fractional-type phase-locked loop circuit is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a correction value accumulating the incremental value, and means for conditioning the control signal according to the correction value. | 08-11-2011 |
| 20110187384 | ELECTRICAL INTERCONNECTION INTEGRATED DEVICE WITH FAULT DETECTING MODULE AND ELECTRONIC APPARATUS COMPRISING THE DEVICE - An electrical interconnection integrated device is described, comprising: a plurality of electrical terminals connectable to an integrated electronic circuit on a chip common to said interconnection device; at least an inside electrical device provided with a respective input connected to a first terminal of said plurality and a respective output; a fault detecting logic module having a first input connected to said output of the inner electrical device and provided with a detecting terminal for supplying a fault detecting signal. | 08-04-2011 |
| 20110186838 | CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER - A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group. | 08-04-2011 |
| 20110184297 | METHOD AND DEVICE FOR ESTIMATING MORPHOLOGICAL FEATURES OF HEART BEATS - A method estimates morphological features of heart beats from an ECG signal. Peaks of the R wave of the ECG are detected and classified using a parallel filtering structure. The first branch implements a bandpass filtering with cut off frequencies of about 10 Hz and 35 Hz, enhancing the signal-to-noise ratio (SNR) of the QRS complex. The second branch estimates morphological features of the heart beat from an alternating current (AC) replica of the ECG signal, that may be used to classify the beat and potentially detect arrhythmias. | 07-28-2011 |
| 20110181323 | METHOD FOR GENERATING A SIGNAL REPRESENTATIVE OF THE CURRENT DELIVERED TO A LOAD BY A POWER DEVICE AND RELATIVE POWER DEVICE - An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track. | 07-28-2011 |
| 20110180843 | CHARGE-BALANCE POWER DEVICE COMPRISING COLUMNAR STRUCTURES AND HAVING REDUCED RESISTANCE, AND METHOD AND SYSTEM OF SAME - An embodiment of a charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columns of a second conductivity type, which extend through the epitaxial layer. A first and a second surface region of the second conductivity type extend along the surface of the epitaxial layer on top of, and in contact with, a respective one of the columns, and a second and a third surface region of the first conductivity type extends within the first and the second surface region, respectively, facing the surface of the epitaxial layer. The columns extend at a distance from each other and are arranged staggered to one another with respect to a first direction and partially facing one another with respect to a second direction transversal to the first direction. | 07-28-2011 |
| 20110179864 | DUAL ACCELEROMETER DETECTOR FOR CLAMSHELL DEVICES - A clamshell device having a dual accelerometer detector includes a first keyboard portion including a first accelerometer, a second display portion including a second accelerometer, a hinge for coupling the first portion to the second portion, and circuitry coupled to the first and second accelerometers for providing an output signal in response to the position of the first and second portions of the clamshell device. The output signal is provided to indicate a shutdown or standby mode, tablet operation mode, a partially shut or power savings mode, a normal operating mode, or an unsafe operating mode. | 07-28-2011 |
| 20110176653 | LOW CONSUMPTION FLIP-FLOP CIRCUIT WITH DATA RETENTION AND METHOD THEREOF - The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated. | 07-21-2011 |
| 20110175650 | DRIVER CIRCUIT AND METHOD FOR REDUCING ELECTROMAGNETIC INTERFERENCE - An apparatus and a method switch a load through a power transistor. The apparatus includes: a first current generator for generating a current to charge a capacitance of a control terminal of the power transistor during power on of the power transistor; a second current generator for generating a current to discharge the capacitance during power off of the power transistor. The apparatus is equipped with control circuitry having a storage element for storing a voltage value representative of the potential difference between the control terminal and a conduction terminal of the power transistor when the power transistor operates in the saturation region and a discharge circuit for generating an additional current to discharge the capacitance during the power-off process. The additional current is a function of the potential difference of the control terminal and the stored voltage value from the conduction terminal. | 07-21-2011 |
| 20110175191 | ISOLATION TRENCHES FOR SEMICONDUCTOR LAYERS - A method is for the formation of at least one isolation trench filled with thermal oxide in a semiconductor layer and a semiconductor device include at least one isolation trench filled with thermal oxide. The method allows obtaining in an easy way, isolation trenches exhibiting excellent functional morphological properties. The method is based on the idea of exploiting the properties of the thermal oxidation mechanism of a semiconductor material in order to obtain at least an isolation trench filled with thermal oxide. | 07-21-2011 |
| 20110171906 | COMMUNICATION CELL FOR AN INTEGRATED CIRCUIT, CHIP COMPRISING SAID COMMUNICATION CELL, ELECTRONIC SYSTEM INCLUDING THE CHIP, AND TEST APPARATUS - An embodiment of communication cell for enabling data communication between an integrated circuit and an electronic unit distinct from the integrated circuit, comprising a contact pad unit, configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device, including signal-amplifying means, coupled between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal correlated to the input signal; signal-selection means receiving the intermediate signal, the input signal, and providing an output signal which is the intermediate signal during the first operating condition, and the input signal during the second operating condition; and an input stage, connectable between the integrated circuit and the output terminal of the signal-selection means, configured for receiving the output signal and providing the output signal to the integrated circuit. | 07-14-2011 |
| 20110170319 | METHOD FOR CONTROLLING A SWITCHING REGULATOR AND RELATED SWITCHING REGULATOR - An embodiment of a power-supply controller comprises a switching-control circuit, an error amplifier, and a signal generator. The switching-control circuit is operable to control a switch coupled to a primary winding of a transformer, and the error amplifier has a first input node operable to receive a feedback signal, a second input node operable to receive a comparison signal, and an output node operable to provide a control signal to the switching-control circuit. The signal generator is operable to generate either the feedback signal or the comparison signal in response to a compensation signal that is isolated from a secondary winding of the transformer and that is proportional to a load current through a conductor disposed between the secondary winding and a load. | 07-14-2011 |
| 20110169822 | METHOD AND SYSTEM FOR SIGNAL PROCESSING, FOR INSTANCE FOR MOBILE 3D GRAPHIC PIPELINES, AND COMPUTER PROGRAM PRODUCT THEREFOR - A system renders a primitive of an image to be displayed, for instance in a mobile 3D graphic pipeline, the primitive including a set of pixels. The system locates the pixels in the area of the primitive, generates, for each pixel located in the area, a set of associated sub-pixels, borrows a set of sub-pixels from neighboring pixels, subjects the set of associated sub-pixels and the borrowed set of pixels to adaptive filtering to create an adaptively filtered set of sub-pixels, and further filters the adaptively filtered set of sub-pixels to compute a final pixel for display. Preferably, the set of associated sub-pixels fulfils at least one of the following: the set includes two associated sub-pixels and the set includes associated sub-pixels placed on pixel edges. | 07-14-2011 |
| 20110161457 | METHOD AND SYSTEMS OF DISTRIBUTING MEDIA CONTENT AND RELATED COMPUTER PROGRAM PRODUCT - Information codes are arranged in pieces comprised of chunks of bytes over a network, such as a Peer-to-Peer overlay network, including a set of peer terminals. A first peer identifies missing chunks in the received pieces and requests such missing chunks from other peers. The chunks are subjected to a fountain code encoding wherein the chunks in a piece are X-ORed. The first peer is therefore capable of reconstructing a received piece encoded with fountain codes from a combination of linearly independent chunks corresponding to the piece. The chunks are transmitted over the network with a connection-less protocol, without retransmission of lost packets, preferably with a UDP protocol. | 06-30-2011 |
| 20110160912 | METHOD AND SYSTEM FOR CONTROLLING ELECTRICAL MACHINES - An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities. The calculation of the square root includes: calculating an approximated value of the square root, having a first precision, and then calculating a corrective value and combining said approximated value with said corrective value to obtain a square root value having a second precision greater than the first precision. | 06-30-2011 |
| 20110159384 | CARTRIDGE FOR HYDROGEN PRODUCTION, SYSTEM FOR HYDROGEN PRODUCTION AND CORRESPONDING PROCESS OF MANUFACTURE - An embodiment of a cartridge for hydrogen production comprises a reaction chamber having a catalyst and a tank chamber comprising a reactant suitable for reacting with said catalyst for the production of gaseous hydrogen and comprising a fluidic conduit of connection between the tank chamber and the reaction chamber, the cartridge comprising a single body associated with a piston element, said piston element being suitable for defining in said single body said tank chamber and said reaction chamber, said piston element being activated for regulating the flow of the reactant in said fluidic conduit. | 06-30-2011 |
| 20110158511 | METHOD AND APPARATUS FOR FILTERING RED AND/OR GOLDEN EYE ARTIFACTS - Processing method of a digital image to filter red and/or golden eye artifacts, the digital image comprising a plurality of pixel each comprising at least one digital value represented on a plurality of bits, the method comprising: a step of selecting at least one patch of pixels of the digital image comprising pixels potentially representative of a red and/or golden eye artifact; a step of classifying the at least one patch of pixels as “eye” or “non-eye”; a step of filtering said potentially representative pixels if said patch of pixels is classified as “eye”; wherein the classifying step comprises the operations of: converting the digital values of said patch of pixels into a Gray Code representation, overall obtaining a plurality of bit maps from said patch of pixels, each bit map being associated with a respective bit of said Gray Code; an operation of individually comparing said bit maps with corresponding bit map models belonging to a patch classifier produced by a statistical analysis of bit maps obtained by converting patches of pixels of digital images containing or not red and/or golden eye artifacts into said Gray Code representation. | 06-30-2011 |
| 20110157977 | FTP MEMORY DEVICE WITH SINGLE SELECTION TRANSISTOR - An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate. An embodiment, the memory device further includes means for applying a first programming voltage to the first wells and a second programming voltage to the control gates of a subset of the memory cells including at least one memory cell to be programmed (with a difference between the first programming voltage and the second programming voltage that is capable of injecting electric charge into the floating gate of each memory cell to be programmed), for applying the first programming voltage to the third region of each memory cell to be programmed, and for applying a third programming voltage (3.5V) comprised between the first programming voltage and the second programming voltage to the third region of each memory cell of the subset not to be programmed (with a difference between the first programming voltage and the third programming voltage that inhibits the injection of electric charge into the corresponding floating gate). | 06-30-2011 |
| 20110157972 | FTP MEMORY DEVICE PROGRAMMABLE AND ERASABLE AT CELL LEVEL - An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of conductivity. Each memory cell includes a first region and a second region of the second type of conductivity, which are formed in the storage region for defining a storage transistor of floating gate MOS type of the first type of conductivity; the memory cell likewise includes a further first region and a further second region of the first type of conductivity, which are formed in the further storage region for defining a further storage transistor of floating gate MOS type of the second type of conductivity. The memory cell also includes a common floating gate of the storage transistor and the further storage transistor. The memory device further includes programming means for programming each memory cell individually by programming the corresponding floating gate through the corresponding storage transistor, and erasing means for erasing each memory cell individually by erasing the corresponding floating gate through the corresponding further storage transistor. | 06-30-2011 |
| 20110157954 | SRAM MEMORY DEVICE - An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage. Said second logic gate includes a pull-up branch coupled between a terminal for providing the supply voltage and the second output terminal, and a pull-down branch coupled between the second output terminal and a terminal for providing the reference voltage. Said memory device includes variation means adapted to selectively vary a gain factor of at least one between the pull-down branch and the pull-up branch of said first logic gate and second logic gate depending on the operation performed by the reading and writing means. | 06-30-2011 |
| 20110157926 | INTEGRATED CIRCUIT FOR AN OSCILLATOR STRUCTURED TO DRIVE A CONTROL DEVICE OF A SWITCHING RESONANT CONVERTER - A circuit for an oscillator structured to drive a control device of a switching resonant converter; the converter having a switching circuit structured to drive a resonant load provided with at least one transformer with at least a primary winding and at least a secondary winding. The control device structured to drive the switching circuit, and the converter structured to convert an input signal into an output signal, the integrated circuit includes a first circuit structured to charge and discharge a capacitor by a first current signal such that the voltage at the ends of the capacitor is between first and second reference voltages, the current signal having a second current signal indicating the output voltage of the converter; the integrated circuit including a second circuit structured to rectify a signal indicating the current circulating in the primary winding. | 06-30-2011 |
| 20110157920 | CHARGE-MODE CONTROL DEVICE FOR A RESONANT CONVERTER - A control device for a resonant converter includes a first circuit structured to rectify a signal indicating the current circulating in the primary winding, a second circuit adapted to integrate at least the rectified signal and structured to generate at least a control signal of the switching circuit according to the integrated signal, and a third circuit adapted to send a reset command to the second circuit so as to inhibit the operation over a time period between the instant when the integrated signal reaches or exceeds a first signal and the instant of the next zero crossing of the signal, indicating the current circulating in the primary winding. | 06-30-2011 |
| 20110156785 | TRIMMING OF A PSEUDO-CLOSED LOOP PROGRAMMABLE DELAY LINE - An embodiment is proposed for trimming a programmable delay line in an integrated device, which delay line is adapted to delay an input signal being synchronous with a synchronization signal of the integrated device—by a total delay. An embodiment of a corresponding method includes the steps of: preliminary programming the delay line to provide a selected nominal value of the total delay equal to a period of the timing signal, and trimming the delay line to vary an actual value of the total delay until the actual value of the total delay matches the period of the synchronization signal. | 06-30-2011 |
| 20110156622 | DRIVING APPARATUS FOR ELECTRIC MOTOR AND RELATED METHOD - A driving apparatus drives a brushless motor that includes a plurality of windings. The apparatus comprises a plurality of switch half-bridges connected to a power line and to the windings, a memory adapted to contain a plurality of signal profiles to be cyclically applied to the plurality of windings of the motor, a multiplier for multiplying the profile values of the signals from the memory by a scale factor, a control circuit adapted to generate PWM signals for the switches of the plurality of switch half-bridges according to values output by the multiplier, a polarity detector configured to detect the polarity of the current passing trough at least one winding of the motor and a scale factor controller configured to modify the scale factor according to the detected current polarity and so as to make each signal profile to be applied to each winding of the motor either higher than the back-electromotive force or equal to the back-electromotive force generated by the motor. | 06-30-2011 |
| 20110156207 | MIM CAPACITOR WITH PLATE HAVING HIGH MELTING POINT - A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C. | 06-30-2011 |
| 20110156140 | METHOD FOR MANUFACTURING A POWER DEVICE BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE, IN PARTICULAR HAVING A FIELD PLATE VERTICAL STRUCTURE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device integrated on a semiconductor substrate comprising the steps of: growth on said substrate of an epitaxial layer; photo-lithography and etching of said epitaxial layer for the formation of at least one deep trench; deposition of a dielectric layer with partial filling of the at least one trench; complete filling of the at least one trench with a layer of sacrificial material; selective etching of the dielectric layer with consequent retrocession below the layer of sacrificial material; selective etching of the layer of sacrificial material with consequent formation of an empty region within the at least one trench; growth of a layer of gate oxide; formation of at least one gate region, of at least one buried source region, of at least one body region and of at least one source region; deposition of a dielectric layer; simultaneous formation of at least one gate contact, at least one body/source contact and at least one buried source contact; formation of a source contact region and of a gate contact region through deposition, masking and etching of a metallisation layer. An embodiment of the method also comprises the step of formation of the at least one gate region and of the at least one buried source region, electrically insulated, through a single deposition of a conductive filling material on the epitaxial layer, on the vertical walls of the trench and within the empty region; and through etching of the conductive filling material forming a first spacer and a second spacer, suitable for serving as a gate electrode and forming a buried source electrode within the empty region. | 06-30-2011 |
| 20110155996 | BISTABLE CARBAZOLE COMPOUNDS - Bistable carbazole compounds of formula (I) | 06-30-2011 |
| 20110155201 | PROCESS FOR REALIZING A SYSTEM FOR RECOVERING HEAT, IN PARTICULAR BASED ON THE SEEBECK'S EFFECT, AND CORRESPONDING SYSTEM - An embodiment of a process for realizing a system for recovering heat is described, the process comprising the steps of: formation on a substrate of a plurality of L-shaped down metal structures; deposition of a dielectric layer on the substrate and the plurality of L-shaped down metal structures by using a screen printing approach; definition and opening in the dielectric layer of upper contacts and lower contacts of the L-shaped down metal structures; formation of a plurality of L-shaped up metal structures being connected to the plurality of L-shaped down metal structure in correspondence of the upper and lower contacts so as to form a plurality of serially connected thermocouples, each comprising at least one L-shaped down metal structure and at least one L-shaped up metal structure, being made of different metal materials and interconnected at a junction, the serially connected thermocouples thus realizing the system for recovering heat. | 06-30-2011 |
| 20110154898 | INTEGRATED MICROELECTROMECHANICAL GYROSCOPE WITH IMPROVED DRIVING STRUCTURE - An integrated MEMS gyroscope, is provided with: at least a first driving mass driven with a first driving movement along a first axis upon biasing of an assembly of driving electrodes, the first driving movement generating at least one sensing movement, in the presence of rotations of the integrated MEMS gyroscope; and at least a second driving mass driven with a second driving movement along a second axis, transverse to the first axis, the second driving movement generating at least a respective sensing movement, in the presence of rotations of the integrated MEMS gyroscope. The integrated MEMS gyroscope is moreover provided with a first elastic coupling element, which elastically couples the first driving mass and the second driving mass in such a way as to couple the first driving movement to the second driving movement with a given ratio of movement. | 06-30-2011 |
| 20110149735 | ON-CHIP INTERCONNECT METHOD, SYSTEM AND CORRESPONDING COMPUTER PROGRAM PRODUCT - In a method for making an on-chip interconnect for conveying between a set of initiators and a set of targets in which traffic is organized in classes of service, priority values representing the classes of service are associated with the traffic. The method further includes propagating the priority values towards the points of the network where an arbitration is performed between two classes of service of the traffic, and providing arbitration as a function of the priority values. | 06-23-2011 |
| 20110149614 | DUAL MODE FLYBACK CONVERTER AND METHOD OF OPERATING IT - A DC-DC converter includes a power switching device and a mode control logic circuit to control the power switching device and generate an ON-pulse. A flip-flop is configured to be set by the mode control logic circuit. A current mode comparator is configured to reset the flip-flop and to compare a signal based upon current flowing through the power switching device with a signal based upon an output voltage of the dual mode flyback DC-DC converter. A transformer is driven by the current mode comparator. The mode control logic circuit includes a timer starting when a gate driver control signal applied to the power switching device turns the power switching device off and configured to generate a pulse when an off time interval elapses, a zero current detector circuit configured to sense a voltage on the transformer and generate a pulse when the voltage drops below a trigger threshold, and a combinatory logic circuit configured to compare pulse signals generated by the timer and the zero current detector circuit and generate the ON-pulse based thereupon. | 06-23-2011 |
| 20110148536 | CIRCUIT ARRANGEMENT OF A VOLTAGE CONTROLLED OSCILLATOR - A circuit for a voltage controlled oscillator has a bridge structure including two cross-coupled N-type transistors and two cross-coupled P-type transistors. A current mirror is coupled to the two N-type cross-coupled transistors and configured to generate a bias current. An LC resonator is coupled in parallel between the two cross-coupled N-type transistors and the two P-type cross-coupled transistors. The LC resonator includes two pairs of differential inductors mutually coupled by a mutual inductance coefficient, each pair comprising a first inductor arranged on a respective branch of an external loop, and a second inductor arranged on a respective branch of an internal loop. A first varactor is coupled to a common node and a first branch of the internal loop. A second varactor is coupled to the common node and the second branch of the internal loop. | 06-23-2011 |
| 20110148372 | SWITCHING VOLTAGE REGULATOR AND RELATED FEED-FORWARD CONTROL METHOD - A method of controlling a pulse width modulated (PWM) voltage regulator including a control circuit of a power stage, and a circuit configured to determine a duration of charge phases and further configured to receive a charge signal and to generate a logic command may include controlling, using the control circuit, switches of the power stage as a function of the logic command at an end of a charge phase and at a start of a discharge phase of an output capacitance. The method may also include generating the charge signal to be one of enabled and disabled during charge phases and another of enabled and disabled during discharge phases, and delaying, at each PWM cycle, the logic command with respect to a previous PWM cycle to compensate at least one of a phase and a frequency difference between each PWM cycle and a reference clock signal. | 06-23-2011 |
| 20110146403 | MICROELECTROMECHANICAL DEVICE HAVING AN OSCILLATING MASS, AND METHOD FOR CONTROLLING A MICROELECTROMECHANICAL DEVICE HAVING AN OSCILLATING MASS - A microelectromechanical device includes a body, a movable mass, elastically connected to the body and movable in accordance with a degree of freedom, and a driving device, coupled to the movable mass and configured to maintain the movable mass in oscillation at a steady working frequency in a normal operating mode. The microelectromechanical device moreover includes a start-up device, which is activatable in a start-up operating mode and is configured to compare a current oscillation frequency of a first signal correlated to oscillation of the movable mass with a reference frequency, and for deciding, on the basis of the comparison between the current oscillation frequency and the reference frequency, whether to supply to the movable mass a forcing signal packet so as to transfer energy to the movable mass. | 06-23-2011 |
| 20110146402 | MICROELECTROMECHANICAL GYROSCOPE WITH CONTINUOUS SELF-TEST FUNCTION, AND METHOD FOR CONTROLLING A MICROELECTROMECHANICAL GYROSCOPE - A microelectromechanical gyroscope includes a body and a sensing mass, which is movable with a degree of freedom in response to rotations of the body about an axis. A self-test actuator is capacitively coupled to the sensing mass for supplying a self-test signal. The capacitive coupling causes, in response to the self-test signal, electrostatic forces that are able to move the sensing mass in accordance with the degree of freedom at an actuation frequency. A sensing device detects transduction signals indicating displacements of the sensing mass in accordance with the degree of freedom. The sensing device is configured for discriminating, in the transduction signals, spectral components that are correlated to the actuation frequency and indicate the movement of the sensing mass as a result of the self-test signal. | 06-23-2011 |
| 20110140693 | INTEGRATED TRIAXIAL MAGNETOMETER OF SEMICONDUCTOR MATERIAL MANUFACTURED IN MEMS TECHNOLOGY - Two suspended masses are configured so as to be flowed by respective currents flowing in the magnetometer plane in mutually transversal directions and are capacitively coupled to lower electrodes. Mobile sensing electrodes are carried by the first suspended mass and are capacitively coupled to respective fixed sensing electrodes. The first suspended mass is configured so as to be mobile in a direction transversal to the plane in presence of a magnetic field having a component in a first horizontal direction. The second suspended mass is configured so as to be mobile in a direction transversal to the plane in presence of a magnetic field having a component in a second horizontal direction, and the first suspended mass is configured so as to be mobile in a direction parallel to the plane and transversal to the current flowing in the first suspended mass in presence of a magnetic field having a component in a vertical direction. | 06-16-2011 |
| 20110134705 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions. | 06-09-2011 |
| 20110133825 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND SAMPLED CONTROL SIGNALS - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal. | 06-09-2011 |
| 20110133186 | PROCESS FOR MANUFACTURING A SEMICONDUCTOR WAFER HAVING SOI-INSULATED WELLS AND SEMICONDUCTOR WAFER THEREBY MANUFACTURED - A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region. | 06-09-2011 |
| 20110128083 | MICROELECTROMECHANICAL RESONANT STRUCTURE HAVING IMPROVED ELECTRICAL CHARACTERISTICS - The present disclosure is directed to a MEMS resonant structure, provided with a substrate of semiconductor material; a mobile mass suspended above the substrate and anchored to the substrate by constraint elements to be free to oscillate at a resonance frequency; and a fixed-electrode structure capacitively coupled to the mobile mass to form a capacitor with a capacitance that varies as a function of the oscillation of the mobile mass; the fixed-electrode structure arranged on a top surface of the substrate, and the constraint elements being configured in such a way that the mobile mass oscillates, in use, in a vertical direction, transverse to the top surface of the substrate, keeping substantially parallel to the top surface. | 06-02-2011 |
| 20110122660 | CURRENT MODE DIGITAL CONTROL OF THE OUTPUT VOLTAGE OF A SWITCHING POWER SUPPLY - A method of controlling an output voltage of a pulse width modulation (PWM) converter with a PWM signal driving a power switch of the converter may include using a comparator to compare a reference voltage with a scaled output voltage of the converter, incrementing or decrementing an up/down counter at each pulse of a clock signal applied to the counter depending on a state of the comparator, and controlling the comparator to generate the PWM signal with a control voltage selected from a look-up table using a value of the counter. | 05-26-2011 |
| 20110122485 | ELECTRICALLY PUMPED LATERAL EMISSION ELECTROLUMINESCENT DEVICE INTEGRATED IN A PASSIVE WAVEGUIDE TO GENERATE LIGHT OR AMPLIFY A LIGHT SIGNAL AND FABRICATION PROCESS - An electrically pumped lateral emission electroluminescent device may include a slotted waveguide including a top silicon layer having a thickness between 150 nm and 300 nm and a refraction index associated therewith, and a bottom silicon layer having a thickness between 150 nm and 300 nm and a refraction index associated therewith. A core layer may include silicon oxide between the top and bottom layers and a thickness less than 70 nm. A core layer refraction index may be greater than each of the top and bottom layer refraction indices. A core layer portion may be in a direction of light propagation and may be doped with erbium, and may include silicon nanocrystals. A portion of each of the top and bottom layers may coincide with the core layer portion and may be doped so that the top and bottom layer portions are electrically conductive to define top and bottom plates. | 05-26-2011 |
| 20110109255 | SYSTEM AND METHOD FOR DETERMINING THE START POSITION OF A MOTOR - A system and method for determining the start position of a motor. According to an embodiment, a voltage pulse signal may be generated across a pair of windings in a motor. A current response signal will be generated and based upon the position of the motor, the response signal will be greater in one pulse signal polarity as opposed to an opposite pulse signal polarity. The response signal may be compared for s specific duration of time or until a specific integration threshold has been reached. Further, the response signal may be converted into a digital signal such that a sigma-delta circuit may smooth out glitches more easily. In this manner, the position of the motor may be determined to within 60 electrical degrees during a startup. | 05-12-2011 |
| 20110102058 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE - An embodiment of a bandgap voltage reference circuit for generating a bandgap voltage reference. Said embodiment comprises a current generator controlled by a first driving voltage for generating a first current depending on the driving voltage, and a first reference circuit element coupled to the controlled current generator for receiving the first current and generating a first reference voltage in response to the first current. The circuit further comprises a second reference circuit element for receiving a second current corresponding to the first current; said second reference circuit element is adapted to generate a second reference voltage in response to the second current. Said circuit further comprises a third reference circuit element for receiving a third current corresponding to the first current and generating the bandgap reference voltage in response to the third current, and an operational amplifier. The operational amplifier has a first input terminal coupled to the first circuit element for receiving a first reference voltage input based on the first reference voltage, a second input terminal coupled to the second reference circuit element for receive a second input voltage based on the second reference voltage and an output terminal coupled to the controlled current generator to provide the first driving voltage to the current generator according to the difference between the first input voltage and the second input voltage. The circuit also comprises a control circuit comprising first capacitive means and second capacitive means. The first capacitive means have a first terminal coupled to the first reference circuit element to receive the first reference voltage and a second terminal coupled to the first input terminal to provide the first input voltage. The second capacitive means comprise a first terminal coupled to the second reference circuit element for receiving the second reference voltage and a second terminal coupled to the second input terminal to provide the second input voltage. The control circuit also comprises biasing means to selectively provide a common-mode voltage to the second terminals of the first and second capacitive means. | 05-05-2011 |
| 20110102049 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE WITH COMPENSATION OF THE OFFSET VOLTAGE - An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current. | 05-05-2011 |
| 20110096816 | METHOD AND DEVICE FOR CHANNEL ESTIMATION, AND CORRESPONDING COMPUTER PROGRAM PRODUCT - An embodiment of the time-variant channel estimation in an OFDM transmission system envisages the operations of: a) determining the received signal vector Y | 04-28-2011 |
| 20110096037 | METHOD FOR DETERMINING THE POSITION OF A CONTACT ON A TOUCH PANEL AND CORRESPONDING SYSTEM - A method for determining the position of a contact on a panel envisages, during a detection operation, detecting vibration signals at a plurality of detection areas fixed with respect to the panel as a function of vibrations generated by the contact; determining detection values of temporal differences between times of detection of the vibrations at pairs of said detection areas; and determining the position of the contact as a function of said temporal differences. A characterization operation, preceding that of detection, envisages defining contact areas (key | 04-28-2011 |
| 20110095304 | PROCESS FOR FORMING AN INTERFACE BETWEEN SILICON CARBIDE AND SILICON OXIDE WITH LOW DENSITY OF STATES - An embodiment of a process for forming an interface between a silicon carbide (SiC) layer and a silicon oxide (SiO | 04-28-2011 |
| 20110089962 | TESTING OF ELECTRONIC DEVICES THROUGH CAPACITIVE INTERFACE - An embodiment of a test apparatus for executing a test of a set of electronic devices having a plurality of electrically conductive terminals, the test apparatus including a plurality of electrically conductive test probes for exchanging electrical signals with the terminals, and coupling means for mechanically coupling the test probes with the electronic devices. In an embodiment, the coupling means includes insulating means for keeping each one of at least part of the test probes electrically insulated from at least one corresponding terminal during the execution of the test. Each test probe and the corresponding terminal form a capacitor for electro-magnetically coupling the test probe with the terminal. | 04-21-2011 |
| 20110089491 | POWER MOS ELECTRONIC DEVICE AND CORRESPONDING REALIZING METHOD - Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges. | 04-21-2011 |
| 20110087832 | WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 04-14-2011 |
| 20110087453 | RELIABILITY TEST WITH MONITORING OF THE RESULTS - An embodiment for executing a reliability test is proposed. A corresponding electronic device includes functional means for implementing a functionality of the electronic device, and testing means for executing a test of the functional means including a plurality of test operations on the functional means; the testing means returns an indication of a result of each test operation. In an embodiment, the electronic device further includes control means for causing the testing means to reiterate the test, monitoring means for monitoring the result of each test operation to detect a failure of the test operation, and storage means for storing failure information indicative of temporal characteristics of each failure. | 04-14-2011 |
| 20110085628 | ADAPTIVE DATA DEPENDENT NOISE PREDICTION (ADDNP) - A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and the adapted one or more filter coefficients. | 04-14-2011 |
| 20110085355 | CONTROL DEVICE FOR RESONANT CONVERTERS - A control device for a switching circuit of a resonant converter having a direct current at the output, the switching circuit having at least one half bridge of at least first and second transistors connected between an input voltage and a reference voltage. The half bridge is adapted to generate a periodic square wave voltage to drive the resonant circuit of the resonant converter; The control device has a circuit to proportionally generate a first voltage to a switching period, and a circuit adapted to limit the voltage at the ends of a capacitor between a reference voltage and the first voltage, and a further circuit structured to control the switching off of a first or second transistor at the time instant in which the voltage across the capacitor has reached the first voltage. | 04-14-2011 |
| 20110081759 | POWER MOS ELECTRONIC DEVICE AND CORRESPONDING REALIZING METHOD - Power MOS device of the type comprising a plurality of elementary power MOS transistors having respective gate structures and comprising a gate oxide with double thickness having a thick central part and lateral portions of reduced thickness. Such device exhibiting gate structures comprising first gate conductive portions overlapped onto said lateral portions of reduced thickness to define, for the elementary MOS transistors, the gate electrodes, as well as a conductive structure or mesh. Such conductive structure comprising a plurality of second conductive portions overlapped onto the thick central part of gate oxide and interconnected to each other and to the first gate conductive portions by means of a plurality of conducive bridges. | 04-07-2011 |
| 20110081739 | ELECTRONIC DEVICE INCLUDING MEMS DEVICES AND HOLED SUBSTRATES, IN PARTICULAR OF THE LGA OR BGA TYPE - An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free. | 04-07-2011 |
| 20110079869 | MULTIPLEXED OUTPUT TWO TERMINAL PHOTODIODE ARRAY FOR IMAGING APPLICATIONS AND RELATED FABRICATION PROCESS - A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel. | 04-07-2011 |
| 20110079794 | METHOD FOR MANUFACTURING ELECTRONIC DEVICES INTEGRATED IN A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICES - A method manufactures a vertical power MOS transistor on a semiconductor substrate comprising a first superficial semiconductor layer of a first conductivity type, comprising: forming trench regions in the first semiconductor layer, filling in said trench regions with a second semiconductor layer of a second conductivity type, to form semiconductor portions of the second conductivity type contained in the first semiconductor layer, carrying out an ion implantation of a first dopant type in the semiconductor portions for forming respective implanted body regions of said second conductivity type, carrying out an ion implantation of a second dopant type in one of the implanted body regions for forming an implanted source region of the first conductivity type inside one of the body regions, carrying out an activation thermal process of the first and second dopant types with low thermal budget suitable to complete said formation of the body and source regions. | 04-07-2011 |
| 20110075452 | DETECTING DEVICE FOR THE MIDPOINT VOLTAGE OF A TRANSISTOR HALF BRIDGE CIRCUIT - A detecting device detects the midpoint voltage of a half bridge circuit of transistors. The circuit comprises a bootstrap capacitor having one terminal connected to the midpoint node of the half bridge circuit and another terminal connected to a supply circuit. The device comprises a further capacitor connected between a second terminal of the bootstrap capacitor and circuit means adapted to form a low impedance node for a current signal circulating in said further capacitor during the transitions from the low value to the high value and from the high value to the low value of the midpoint voltage. The device comprises a detector to detect said current signal circulating in said further capacitor and to output at least a first signal indicating the transitions from the low value to the high value or from the high value to the low value according to said current signal. | 03-31-2011 |
| 20110074374 | DRIVING APPARATUS FOR AN ELECTROMAGNETIC LOAD AND RELATED METHOD - A driving apparatus for an electromagnetic load, said apparatus having at least one pair of first and second transistors arranged so as to form a current path with the electromagnetic load for discharging the current produced by the electromagnetic load. The first transistor has an inherent diode between the non-drivable terminals and the apparatus is configured to control switching of the pair of first and second transistors, to diode-connect the second transistor, with said first and second transistors switched off, so that the current produced by said electromagnetic load, crossing said inherent diode, creates an overvoltage between the terminals of the second diode-configured transistor such to exceed the conduction threshold voltage thereof. | 03-31-2011 |
| 20110074221 | ELECTRONIC DEVICE FOR REGULATING A VARIABLE CAPACITANCE OF AN INTEGRATED CIRCUIT - The present disclosure relates to an electronic regulation device of a variable capacitance of an integrated circuit having a time parameter depending on the variable capacitance. The regulation device includes a regulation loop, and is configured to generate in output a plurality of binary regulation signals. | 03-31-2011 |
| 20110073966 | INDEXING OF ELECTRONIC DEVICES DISTRIBUTED ON DIFFERENT CHIPS - An embodiment of a method is proposed for indexing electronic devices. The embodiment includes the steps of forming a plurality of first chips in a first wafer, forming a plurality of second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device; the index is indicative of a position of the corresponding first chip in the first wafer. In an embodiment, the step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip. | 03-31-2011 |
| 20110073960 | INTEGRATED DEVICE WITH RAISED LOCOS INSULATION REGIONS AND PROCESS FOR MANUFACTURING SUCH DEVICE - An embodiment of an integrated device includes a semiconductor body, in which an STI insulating structure is formed, laterally delimiting first active areas and at least one second active area in a low-voltage region and in a power region of the semiconductor body, respectively. Low-voltage CMOS components are housed in the first active areas. Formed in the second active area is a power component, which includes a source region, a body region, a drain-contact region, and at least one LOCOS insulation region, arranged between the body region and the drain-contact region and having a prominent portion that emerges from a surface of the semiconductor body, and an embedded portion inside it. The prominent portion of the LOCOS insulation region has a volume greater than that of the embedded portion. | 03-31-2011 |
| 20110073945 | PROCESS FOR MANUFACTURING AN INTEGRATED DEVICE WITH "DAMASCENE" FIELD INSULATION, AND INTEGRATED DEVICE MADE BY SUCH PROCESS - An integrated device includes a semiconductor body, in which an STI insulation structure is formed, which delimits laterally first active areas and at least one second active area, respectively, in a low-voltage region and in a power region of the semiconductor body. The integrated device moreover includes low-voltage CMOS components, accommodated in the first active areas, and a power component in the second active area. The power component has a source region, a body region, a drain-contact region, and at least one field-insulating region, set between the body region and the drain-contact region. The field-insulating region is provided entirely on the semiconductor body. | 03-31-2011 |
| 20110069753 | METHODS AND SYSTEM FOR ENCODING/DECODING SIGNALS INCLUDING SCRAMBLING SPECTRAL REPRESENTATION AND DOWNSAMPLING - A method for encoding and decoding media signals, includes the operations of generating at a transmitting side multiple descriptions associated to data of the media signals through a downsampling operation performed on the data, and decoding at a receiving side the multiple descriptions for reconstructing the data by merging the multiple descriptions. The operation of generating multiple descriptions further includes the operations of obtaining a spectral representation of the data, including bands associated to different ranges, the bands being obtained by a suitable quantization operation and including at least one highly quantized band, that is subjected to a higher degree of quantization. A scrambling operation is performed on the spectral representation by moving the at least one highly quantized band to a different range, the scrambling operation being performed prior the downsampling operation. In decoding, a descrambling operation is performed before the merging operation on the multiple descriptions. | 03-24-2011 |
| 20110069563 | VOLTAGE SHIFTER FOR HIGH VOLTAGE OPERATIONS - A voltage shifter has a supply line receiving a supply voltage that varies between a first operating value in a first operating condition and a second high operating value, in a second operating condition. A latch stage is connected to an output branch and to a selection circuit, which receives a selection signal that controls switching of the latch stage. The latch stage is coupled to the supply line and to a reference potential line, which receives a reference voltage that can vary between a first reference value, when the supply voltage has the first operating value, and a second reference value, higher than the first reference value, when the supply voltage has the second operating value. An uncoupling stage is arranged between the latch stage and the selection circuit and uncouples them in the second operating condition, when the supply voltage and the reference voltage are at their second, high, value. | 03-24-2011 |
| 20110069562 | LOW CONSUMPTION VOLTAGE REGULATOR FOR A HIGH VOLTAGE CHARGE PUMP, VOLTAGE REGULATION METHOD, AND MEMORY DEVICE PROVIDED WITH THE VOLTAGE REGULATOR - A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator. | 03-24-2011 |
| 20110069554 | SENSE-AMPLIFIER CIRCUIT FOR NON-VOLATILE MEMORIES THAT OPERATES AT LOW SUPPLY VOLTAGES - A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror. | 03-24-2011 |
| 20110068857 | LATCH CHARGE PUMP WITH EQUALIZATION CIRCUIT - A charge pump including first and a second charge-pump stages electrically coupled, four pump capacitors connected between two enable terminals and four internal nodes, two pump transistors connected to the pump capacitors and to the internal nodes, and having respective control terminals, two biasing capacitors, connected between the control terminals and the enable terminals, and an equalization circuit connected between the control terminals and structured to limit the voltage between the control terminals within a first range of values. | 03-24-2011 |
| 20110068179 | METHOD FOR BIASING AN EEPROM NON-VOLATILE MEMORY ARRAY AND CORRESPONDING EEPROM NON-VOLATILE MEMORY DEVICE - Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation. | 03-24-2011 |
| 20110060975 | SYSTEM FOR DETECTING OPERATING ERRORS IN INTEGRATED CIRCUITS - Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse. | 03-10-2011 |
| 20110060786 | DEVICE FOR COMPUTING QUOTIENTS, FOR EXAMPLE FOR CONVERTING LOGICAL ADDRESSES INTO PHYSICAL ADDRESSES - A device for calculating the quotient q and remainder r of the division (y·k | 03-10-2011 |
| 20110058672 | MESSAGE DECIPHERING METHOD, SYSTEM AND ARTICLE - A method for decrypting the encrypted messages sent by a transmission device to a first electronic device associated with a first trusted authority and to a second electronic device (ME). In one embodiment, first and second tokens are generated and exchanged, respectively, by the first and second electronic devices, which then generate a joint decryption key in order to decrypt the encrypted message. | 03-10-2011 |
| 20110058632 | METHOD AND DEVICE FOR SOFT-OUTPUT DETECTION IN MULTIPLE ANTENNA COMMUNICATION SYSTEMS - An embodiment of a method and device for detecting a signal and generating bit soft-output of a multiple-input multiple-output system is provided. The device includes at least one channel estimates pre-processing unit, one received vector processing and one detection and soft-output generation unit. The pre-processing unit calculates multiple QR Decompositions of the input channel estimation matrix. The detection and soft-output generation unit computes near optimal bit soft output information with a deterministic complexity and latency. It may implement a reduced complexity search method. Globally, embodiments of the invention may allow achieving low complexity, high data rate, scalability in terms of the dimension of the MIMO system and flexibility versus the supported modulation order, all potentially key factors for most MIMO wireless transmission applications. | 03-10-2011 |
| 20110052053 | DIGITAL IMAGE PROCESSING APPARATUS AND METHOD - An image processing apparatus suitable for processing a digital image in YCrCb color space, the image having an initial luminance plane Y and two initial Cr, Cb chrominance planes, the processing apparatus including a first block that receives the initial luminance plane Y of the digital image and processes and modifies the initial luminance plane Y in order to provide a modified luminance plane Y in output; a color artifact correction block, operating in parallel with the first block, the correction block receiving the initial planes Y, Cr, Cb of the image and modifying the initial chrominance planes Cr and Cb through a pixel by pixel processing approach with a mobile working window, the correction block having a false colors correction sub-block and a purple fringing correction sub-block, or both, the sub-blocks structured to modify values of the initial Cr, Cb chrominance planes based on information contained in the initial Cr, Cb chrominance planes and also based on information contained in the initial luminance plane Y. | 03-03-2011 |
| 20110050267 | ELECTROMAGNETIC SHIELD FOR TESTING INTEGRATED CIRCUITS - An embodiment of a probe card is proposed. The probe card comprises a plurality of probes. Each probe is adapted to contact a corresponding terminal of a circuit integrated in at least one die of a semiconductor material wafer during a test phase of the wafer. Said plurality of probes includes at least one probe adapted to provide and/or receive a radio frequency test signal to/from the corresponding terminal during the test phase. Said probe card comprises at least one electromagnetic shield structure corresponding to the at least one probe adapted to provide and/or receive the radio frequency test signal for the at least partial shielding of an electromagnetic field irradiated by such at least one probe adapted to provide and/or receive the radio frequency test signal. | 03-03-2011 |
| 20110049728 | METHOD TO PERFORM ELECTRICAL TESTING AND ASSEMBLY OF ELECTRONIC DEVICES - A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package. | 03-03-2011 |
| 20110049638 | STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS - An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench. | 03-03-2011 |
| 20110049616 | SEMICONDUCTOR STRUCTURE FOR A POWER DEVICE AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:—an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;—an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions. | 03-03-2011 |
| 20110043394 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER - A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components. | 02-24-2011 |
| 20110042739 | MOS DEVICE RESISTANT TO IONIZING RADIATION - An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode region overlying the dielectric gate region; and body regions having a second type of conductivity, formed within the surface semiconductor layer, laterally and partially underneath the gate structure. In particular, the dielectric gate region is formed by a central region having a first thickness, and by side regions having a second thickness, smaller than the first thickness; the central region overlying an intercell region of the surface semiconductor layer, set between the body regions. | 02-24-2011 |
| 20110034010 | PROCESS FOR MANUFACTURING A MULTI-DRAIN ELECTRONIC POWER DEVICE INTEGRATED IN SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - A process manufactures a multi-drain power electronic device on a semiconductor substrate of a first conductivity type and includes: forming a first semiconductor layer of the first conductivity type on the substrate, forming a second semiconductor layer of a second conductivity type on the first semiconductor layer, forming, in the second semiconductor layer, a first plurality of implanted regions of the first conductivity type using a first implant dose, forming, above the second semiconductor layer, a superficial semiconductor layer of the first conductivity type, forming in the surface semiconductor layer body regions of the second conductivity type, thermally diffusing the implanted regions to form a plurality of electrically continuous implanted column regions along the second semiconductor layer, the plurality of implanted column regions delimiting a plurality of column regions of the second conductivity type aligned with the body regions. | 02-10-2011 |
| 20110032036 | PERFORMANCE TUNING USING ENCODED PERFORMANCE PARAMETER INFORMATION - A multi-chip system in which at least one of the chips includes a performance parameter encoded thereon. After system assembly, the performance parameter can be obtained by a companion chip and used to automatically or semi-automatically fine tune the companion chip to the specific parameters of the at least one chip. | 02-10-2011 |
| 20110031567 | PROCESS FOR MANUFACTURING MEMS DEVICES HAVING BURIED CAVITIES AND MEMS DEVICE OBTAINED THEREBY - A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity. | 02-10-2011 |
