| STMicroelectronics S.A. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120133021 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA, AND FABRICATION METHOD - A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via. | 05-31-2012 |
| 20120133020 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA AND FABRICATION METHOD - A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode. | 05-31-2012 |
| 20120126230 | METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP STACK DEVICE - A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array. | 05-24-2012 |
| 20120126094 | ANALOG TO DIGITAL RAMP CONVERTER - A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal. | 05-24-2012 |
| 20120120716 | SECURE NON-VOLATILE MEMORY - A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope. | 05-17-2012 |
| 20120119942 | RADAR WAVE TRANSMIT/RECEIVE DEVICE - Device for transmitting/receiving frequency modulated type radar waves that includes: a circuit for generating radar waves which includes a voltage-controlled oscillator coupled to a circulator which is itself connected to a transmit/receive antenna; a detection circuit including a first mixer which is fed by the circulator and the voltage-controlled oscillator, wherein voltage-controlled oscillator incluing an input for injecting a signal generated by an additional circuit, the additional circuit having its input fed by the output signal of voltage-controlled oscillator and including a second mixer which is fed by two signals generated on the basis of the output signal of voltage-controlled oscillator. | 05-17-2012 |
| 20120117391 | Method and System for Managing the Power Supply of a Component - A method and system for managing the power supply of a component and of a memory cooperating with the component are disclosed. The component and the memory are powered with a first variable power supply source having a first power supply voltage level greater than a minimum operating voltage of the memory. When a voltage level of the first power supply source drops and reaches a threshold that is greater than or equal to the minimum operating voltage of the memory, the power supply of the memory is toggled to a second power supply source having a second voltage level that is greater than or equal to the minimum operating voltage of the memory. | 05-10-2012 |
| 20120112948 | COMPACT SAR ADC - A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage. | 05-10-2012 |
| 20120106120 | TRANSMISSION LINE FOR ELECTRONIC CIRCUITS - A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip. | 05-03-2012 |
| 20120098684 | Device and Method for Processing an Analogue Signal - Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset. | 04-26-2012 |
| 20120086608 | Antenna Array for Transmission/Reception Device for Signals with a Wavelength of the Microwave, Millimeter or Terahertz Type - Transmission/reception device for signals having a wavelength of the microwaves, millimeter or terahertz type, comprising an antenna array. The antenna array comprises a first group of first omni-directional antennas and a second group of second directional antennas disposed around the first group of antennas. | 04-12-2012 |
| 20120086091 | BACKSIDE IMAGE SENSOR - A backside image sensor including an assembly of pixels, each pixel including, in a vertical stack, a photosensitive area and a filtering element topping the photosensitive area on the back surface side, wherein at least two adjacent filtering elements of adjacent pixels are separated by a vertical metal wall extending over at least eighty percent of the height of the filtering elements or over a greater height. | 04-12-2012 |
| 20120081978 | READ BOOST CIRCUIT FOR MEMORY DEVICE - A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground. | 04-05-2012 |
| 20120074527 | INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT - The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element. | 03-29-2012 |
| 20120062313 | TRANSISTOR SUBSTRATE DYNAMIC BIASING CIRCUIT - A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage. | 03-15-2012 |
| 20120062288 | Device and Method for Generating a Signal of Parametrizable Frequency - Device for generating a signal of parametrizable frequency comprising a phase locked loop including a generator of a reference signal, a phase-frequency comparator comprising a first input for receiving the reference signal, an oscillator controlled on the basis of the result output by the phase-frequency comparator, a fractional divider coupled between an output of the oscillator and a second input of the phase-frequency comparator, and a selector selectively linking an input of the oscillator either with an input of the generator, or with the output of the oscillator as a function of the multiplication ratio of the fractional divider. | 03-15-2012 |
| 20120042292 | METHOD OF SYNTHESIS OF AN ELECTRONIC CIRCUIT - A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors. | 02-16-2012 |
| 20120032291 | Stand-Alone Device - A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device. | 02-09-2012 |
| 20120018619 | Method of Resetting a Photosite, and Corresponding Photosite - A method of resetting a photosite is disclosed. Photogenerated charges accumulated in the photosite are reset by recombining the photogenerated charges with charges of opposite polarity. | 01-26-2012 |
| 20120012891 | VOLTAGE-CONTROLLED BIDIRECTIONAL SWITCH - A voltage-controlled vertical bi-directional monolithic switch, referenced with respect to the rear surface of the switch, formed from a lightly-doped N-type semiconductor substrate, in which the control structure includes, on the front surface side, a first P-type well in which is formed an N-type region, and a second P-type well in which is formed a MOS transistor, the first P-type well and the gate of the MOS transistor being connected to a control terminal, said N-type region being connected to a main terminal of the MOS transistor, and the second main terminal of the MOS transistor being connected to the rear surface voltage of the switch. | 01-19-2012 |
| 20120007686 | MULTIBAND VOLTAGE CONTROLLED OSCILLATOR WITHOUT SWITCHED CAPACITOR - A controlled oscillator includes, connected in parallel, a capacitor configured to be tuneable based upon a first signal, an inductor, and an active impedance. The active impedance is formed by a pair of cross-coupled transistors connected so as to produce a negative resistive component at the terminals of the active impedance. Circuitry produces a degeneracy tuneable by a second signal in the cross-coupled pair, such that the cross-coupled pair produces a capacitive component tuneable based upon the second signal at the terminals of the active impedance. | 01-12-2012 |
| 20120007201 | MONOLITHIC PHOTODETECTOR - A photodetector including a photodiode formed in a semiconductor substrate and a waveguide element formed of a block of a high-index material extending above the photodiode in a thick layer of a dielectric superposed to the substrate, the thick layer being at least as a majority formed of silicon oxide and the block being formed of a polymer of the general formula R | 01-12-2012 |
| 20120006980 | PHOTOSENSITIVE INTEGRATED CIRCUIT EQUIPPED WITH A REFLECTIVE LAYER AND CORRESPONDING METHOD OF PRODUCTION - A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers. | 01-12-2012 |
| 20120004016 | FILTERING CIRCUIT WITH COUPLED BAW RESONATORS AND HAVING IMPEDANCE MATCHING ADAPTATION - A filtering circuit includes a substrate; an acoustic mirror or a membrane destined to act as a mechanical support of acoustic resonators and to isolate these resonators from the substrate; a first section comprising an upper resonator and a lower resonator coupled to each other by at least one acoustic coupling layer; and a second section comprising an upper resonator and a lower resonator coupled to each other by at least one acoustic coupling layer. The filtering circuit also includes metallic vias implementing an inter stage connection between the lower resonator of a section and the upper resonator of the other section. Preferably, the upper resonators exhibit a piezoelectric layer having a thickness selected in order to achieve an optimal impedance matching between the said first and second sections. | 01-05-2012 |
| 20120001665 | FRACTIONAL FREQUENCY DIVIDER - A fractional frequency divider including a frequency division unit for generating a reduced frequency timing signal having j pulses for every k pulses of an original timing signal, wherein j and k are each integers; and phase correction circuitry adapted to selectively shift each jth pulse of the reduced frequency timing signal by a first fixed time period. | 01-05-2012 |
| 20110316587 | Bistable CML Circuit - A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch. | 12-29-2011 |
| 20110298554 | METHOD OF ADJUSTMENT DURING MANUFACTURE OF A CIRCUIT HAVING A CAPACITOR - A method of adjustment during manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the electrical signal between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode. | 12-08-2011 |
| 20110298491 | Dual-Edge Register and the Monitoring Thereof on the Basis of a Clock - Sequential electronic circuit ( | 12-08-2011 |
| 20110298010 | Cell Library, Integrated Circuit, and Methods of Making Same - A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion. | 12-08-2011 |
| 20110293015 | METHOD AND DEVICE FOR IMAGE INTERPOLATION SYSTEMS BASED ON MOTION ESTIMATION AND COMPENSATION - A motion estimation method and device are provided for processing images to be inserted, between a preceding original image and a following original image, into a sequence of images. Each image is divided into pixel blocks associated with motion vectors. For a current block of an image being processed, motion vectors associated with blocks of the image being processed and/or associated with blocks of a processed image are selected. Candidate vectors are generated from selected motion vectors. An error is calculated for each candidate vector. A penalty is determined for a subset of candidate vectors on the basis of the values of the pixels of the pixel block in the preceding original image from which the candidate motion vector points to the current block and/or on the basis of the values of the pixels of the pixel block in the following original image to which the candidate motion vector points from the current block. | 12-01-2011 |
| 20110291696 | Method for Protecting a Logic Circuit Against External Radiation and Associated Electronic Device - A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times. | 12-01-2011 |
| 20110279196 | LOW-PASS FILTER WITH ADJUSTABLE CUT-OFF FREQUENCY - A low-pass filter includes an integrator having an adjustable unity frequency. The integrator includes a first input, first output and feedback loop between the first input and output of the integrator. The first input is connected to a branch that includes a first impedance, to which is applied a first input voltage of the low-pass filter. The feedback loop includes a second impedance and the first output of the integrator is the first output of the low-pass filter. | 11-17-2011 |
| 20110272801 | SEMICONDUCTOR DEVICE WITH CONNECTION PADS PROVIDED WITH INSERTS - A semiconductor device includes an integrated circuit and external electrical connection pads. Each pad includes cavities that are at least partially filled with a material different from the material forming the pads, so as to form inserts. | 11-10-2011 |
| 20110246811 | METHOD FOR ESTIMATING THE RELIABILITY OF AN ELECTRONIC CIRCUIT, CORRESPONDING COMPUTERIZED SYSTEM AND COMPUTER PROGRAM PRODUCT - The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component. | 10-06-2011 |
| 20110243321 | SCRAMBLING OF A CALCULATION PERFORMED ACCORDING TO AN RSA-CRT ALGORITHM - A method and a circuit for scrambling an RSA-CRT algorithm calculation by an electronic circuit, in which a result is obtained from two modular exponentiation calculations, each providing a partial result, and from a recombination step, and in which a first step adds a digital quantity to at least one first partial result before said recombination step; and a second step cancels the effects of this quantity after the recombination step. | 10-06-2011 |
| 20110237068 | METHOD FOR FORMING ELECTRIC VIAS - A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings. | 09-29-2011 |
| 20110234310 | Second-Order Low-Pass Filter - A low-pass filter, including: between a first terminal and a second terminal, a series association of a first resistor, of a second resistor, and of a first amplifier; in parallel with the second resistor, a series association of a second amplifier and of a first capacitor; a second capacitor between an input of the first amplifier and a third terminal of application of a reference voltage; and a third capacitor between the second terminal and the third terminal. | 09-29-2011 |
| 20110227194 | METHOD FOR FORMING A THREE-DIMENSIONAL STRUCTURE OF METAL-INSULATOR-METAL TYPE - A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure. | 09-22-2011 |
| 20110221944 | CMOS IMAGE SENSOR HAVING A WIDE LINEAR DYNAMIC RANGE - The disclosure relates to a process of controlling a pixel cell of an image sensor of the CMOS type, comprising the steps of: initializing a sense node and a read node of the pixel cell; partially transferring electrical charges accumulated at the sense node to the read node; completely evacuating electrical charges accumulated at the read node; partially transferring electrical charges accumulated at the sense node to the read node; measuring the electrical charges accumulated at the read node to obtain a pixel signal corresponding to a quantity of electrical charges accumulated during a short integration period; completely transferring electrical charges accumulated at the sense node to the read node, without a prior initialization of the read node, and measuring the electrical charges at the read node to obtain a pixel voltage corresponding thus to the sum of the electrical charges accumulated during the short and long integration periods. | 09-15-2011 |
| 20110221035 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING A METAL-INSULATOR-METAL CAPACITOR AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit is fabricated by producing metallization levels in insulating regions, the insulating region being formed of a first material having a first dielectric constant. At least one metal-insulator-metal capacitor is formed by providing metal electrodes in the metallization level, and locally replacing the first material, which is located between the metal electrodes, with a second material having a second dielectric constant greater than the first dielectric constant. | 09-15-2011 |
| 20110214012 | SECURED COPROCESSOR COMPRISING AN EVENT DETECTION CIRCUIT - A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards. | 09-01-2011 |
| 20110213944 | SYNCHRONIZATION SYSTEM AND RELATED INTEGRATED CIRCUIT - A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency. | 09-01-2011 |
| 20110205098 | SWITCHED CAPACITOR AMPLIFIER - A switched capacitor amplifier having an amplification unit adapted to amplify a differential signal; a first switched capacitor block including a first plurality of capacitors operable to sample a first differential input signal during a first sampling phase and to drive the amplification unit during a first drive phase; and a second switched capacitor block including a second plurality of capacitors operable to sample a second differential input signal during a second sampling phase and to drive the amplification unit during a second drive phase. | 08-25-2011 |
| 20110200152 | Continuous Time Analogue/Digital Converter - Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD | 08-18-2011 |
| 20110194734 | METHOD FOR CAPTURING IMAGES COMPRISING A MEASUREMENT OF LOCAL MOTIONS - A method for capturing a sequence of video images, using an imager including an estimation of the parameters of a model of global motion between successive images. The method may include measurement of local motions on edges of the images, with the estimation of the parameters of the global motion model performed using the result of the measurement of local motions on the edges of the images. | 08-11-2011 |
| 20110180689 | COMPACT IMAGE SENSOR ARRANGEMENT - An image sensor having a number of pixel zones delimited by isolation trenches, each pixel zone including a photodiode; a transfer gate associated with each of the pixel zones and arranged to transfer charge from the photodiode to a sensing node; and a read circuit for reading a voltage at one of the sensing nodes, the read circuitry including a number of transistors of which at least one is positioned at least partially over a pixel zone of the pixel zones. | 07-28-2011 |
| 20110175887 | METHOD FOR CONTROLLING A DISPLAY SCREEN, IN PARTICULAR A PLASMA DISPLAY SCREEN, AND DEVICE FOR SAME - A display screen is controlled through successive scans of the display screen. Each scan of the display screen includes a successive selection of rows of the display screen. For each row selected, and in accordance with a normal selection, a first column selection mode is implemented wherein a first selection signal is generated for the column, that first selection signal going from a first state towards a second state with an intermediate plateau level being reached therebetween. In an alternative operation, a second column selection mode is provided which replaces the first column selection mode, the second column selection mode including the generation of a second selection signal going from the first state to the second state without any intermediate plateau level being reached therebetween. At least at the start of each scan, the first selection mode is replaced by the second selection mode and this second selection mode is maintained for a given column, at the latest, for as long as no deselection of the column has been effected. | 07-21-2011 |
| 20110169572 | PHASE-SHIFT AMPLIFIER - A cascode amplifier comprising at least two phase-shift stages controllable between an input transistor having a control terminal connected to an input terminal of the amplifier, and an output terminal of the amplifier. | 07-14-2011 |
| 20110156816 | Biasing Circuit for Differential Amplifier - The invention concerns a biasing circuit for controlling the current flowing through a differential pair ( | 06-30-2011 |
| 20110153245 | METHOD OF IDENTIFYING AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit. | 06-23-2011 |
| 20110149468 | THREE-DIMENSIONAL CAPACITOR AND TOPOLOGICAL DESIGN METHOD FOR SUCH A CAPACITOR - A three-dimensional capacitor is formed from a multilayer of superposed electrodes. The electrodes are formed within respective metallization levels of an integrated circuit. At least two additional superposed electrodes are formed on top of the multilayer. Each additional electrode is formed from a branched rectilinear structure including at least one bar aligned in a first direction and a plurality of branches extending from that at least one bar in a second direction. | 06-23-2011 |
| 20110148542 | TRANSFORMER AND METHOD FOR USING SAME - Method for improving the symmetry of the differential output signals of an integrated transformer of the symmetric-asymmetric type comprising an inductive primary circuit and an inductive secondary circuit, characterized in that the capacitive coupling between the primary and secondary circuits is reduced. | 06-23-2011 |
| 20110140802 | Electrical Coupler and Communication Apparatus Comprising Such an Electrical Coupler - Device comprising a first input configured to receive a first input signal of given wavelength, several distinct pairs of outputs, the two outputs of each pair of outputs being configured to deliver a differential output signal, and an electrically conducting transmission means forming a closed circuit and coupled between the first input and the outputs, at least one length of the portion of the transmission means, coupled between two outputs of a pair of outputs, being substantially equal to an even multiple of a quarter of the said wavelength, the lengths of those portions of the transmission means which couple two homologous outputs of two pairs of outputs being substantially equal, and at least one length of the portion of the transmission means, coupled between the first input and the output closest to the said first input, being substantially equal to a quarter of the said wavelength. | 06-16-2011 |
| 20110140220 | MICROELECTRONIC DEVICE, IN PARTICULAR BACK SIDE ILLUMINATED IMAGE SENSOR, AND PRODUCTION PROCESS - A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer. | 06-16-2011 |
| 20110134304 | OPTICAL IMAGING ELEMENT AND MODULE FOR AN OPTICAL SEMICONDUCTOR COMPONENT, METHOD FOR PROCESSING AN OPTICAL IMAGING ELEMENT AND IMAGE CAPTURE APPARATUS - An optical element or module is designed to be placed in front of an optical sensor of a semiconductor component. At least one optically useful part of the element or module is provided through which the image to be captured is designed to pass. A method for obtaining such an optical element or module includes forming at least one through passage between a front and rear faces of the element or module. The front and rear faces are covered with a mask. Ion doping is introduced through the passage. As a result, the element or module has a refractive index that varies starting from a wall of the through passage and into the optically useful part. An image capture apparatus includes an optical imaging module having at least one such element or module. | 06-09-2011 |
| 20110126065 | MICROPROCESSOR COMPRISING SIGNATURE MEANS FOR DETECTING AN ATTACK BY ERROR INJECTION - A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. Current cumulative signatures are produced using deterministic address, control or data logic signals involved in the execution of the sequence and taken off at various points of the integrated circuit. A final cumulative signature is compared with an expected signature and an error signal is produced if the two signatures are not identical. Particularly useful to secure integrated circuits for smart cards. | 05-26-2011 |
| 20110115053 | RESISTOR IN AN INTEGRATED CIRCUIT - A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes. | 05-19-2011 |
| 20110113304 | METHOD FOR DECODING A SUCCESSION OF BLOCKS ENCODED WITH AN ERROR CORRECTION CODE AND CORRELATED BY A TRANSMISSION CHANNEL - A method is for decoding a block of N information items encoded with an error correction code and mutually correlated. The method includes carrying out a first decorrelation of the N information items of a block is carried out, and storing the block decorrelated. The method also includes a performing a processing for decoding a group of P information items of the block, and decorrelating at least part of the P decoded information items. The processing for decoding the group of P information items and the decorrelation are repeated with different successive groups of P information items of the block until the N information items of the block have been processed, until a decoding criterion is satisfied. | 05-12-2011 |
| 20110109521 | ELECTRONIC DEVICE COMPRISING A SEMICONDUCTOR COMPONENT INTEGRATING AN ANTENNA - An electronic device includes a semiconductor component having a support substrate in the form of a wafer. On one side of this substrate integrated circuits including an RF circuit and an antenna connected to this RF circuit are formed. A metal layer is situated on the other side of the substrate, facing the antenna. At least on metal via is provided in a through-hole in the substrate, this via being connected at one end to the metal layer and at the other end to the RF circuit, at the same reference potential node as the antenna. | 05-12-2011 |
| 20110108939 | METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR - A method for manufacturing a back-side illuminated image sensor, including the steps of: forming, inside and on top of an SOI-type silicon layer, components for trapping and transferring photogenerated carriers and isolation regions; forming a stack of interconnection levels on the silicon layer and attaching, on the interconnect stack, a semiconductor handle; removing the semiconductor support; forming, in the insulating layer and the silicon layer, trenches reaching the isolation regions; depositing a doped amorphous silicon layer, more heavily doped than the silicon layer, at least on the walls and the bottom of the trenches and having the amorphous silicon layer crystallize; and filling the trenches with a reflective material. | 05-12-2011 |
| 20110108801 | SINGLE-CRYSTAL SEMICONDUCTOR LAYER WITH HETEROATOMIC MACRO-NETWORK - A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism. | 05-12-2011 |
| 20110095437 | INTERFACE PLATE BETWEEN INTEGRATED CIRCUITS - An interface plate capable of being mounted between first and second surface-mounted electronic chips. The plate includes a plurality of first, second, and third through openings, the first openings being filled with a conductive material and being arranged to be in front of pads of the first and second chips during the assembly, the second openings being filled with a second material, the third openings being filled with a third material, the second and third materials forming two complementary components of a thermoelectric couple. | 04-28-2011 |
| 20110085626 | RECEIVE UNIT FOR RECEPTION OF MULTIPLE SATELLITE SIGNALS - A satellite receive unit for receiving a plurality of satellite signals from a plurality of satellites, the satellite receive unit including: a plurality of low noise blocks each for receiving one or more of the satellite signals and providing a received signal, at least one of the low noise blocks receiving a plurality of the satellite signals; and a satellite signal processing unit including a plurality of branches each arranged to receive a corresponding one of the received signals from the plurality of low noise blocks, each branch having a multiplier arranged to weight the received signal by multiplying by a corresponding coefficient; and an adder arranged to add the weighted signals of each branch to generate an output satellite signal. | 04-14-2011 |
| 20110084748 | FLIP-FLOP WITH SINGLE CLOCK PHASE AND WITH REDUCED DYNAMIC POWER - A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase. | 04-14-2011 |
| 20110084398 | SEMICONDUCTOR DEVICE COMPRISING AN ELECTROMAGNETIC WAVEGUIDE - A semiconductor device includes a substrate. On at least one face of that substrate, integrated circuits are formed. At least one electromagnetic waveguide is also included, that waveguide including two metal plates that are placed on either side of at least one part of the thickness of the substrate and are located facing each other. Two longitudinal walls are placed facing each other and are formed by metal vias made in holes passing through the substrate in its thickness direction. The metal vias electrically connect the two metal plates. | 04-14-2011 |
| 20110080687 | METHOD OF ADJUSTMENT ON MANUFACTURING OF A CIRCUIT HAVING A RESONANT ELEMENT - A method of adjustment in the manufacture of a capacitance of a capacitor supported by a substrate, the method including the steps of: a) forming a first electrode parallel to the surface of the substrate and covering it with a dielectric layer; b) forming, on a first portion of the dielectric layer, a second electrode; c) measuring the capacitance between the first electrode and the second electrode, and deducing therefrom the capacitance to be added to obtain the desired capacitance; d) thinning down a second portion of the dielectric layer, which is not covered by the second electrode, so that the thickness of this second portion is adapted to the forming of the deduced capacitance; and e) forming a third electrode on the thinned-down portion and connecting it to the second electrode. | 04-07-2011 |
| 20110080233 | METHOD FOR MANUFACTURING BAW RESONATORS ON A SEMICONDUCTOR WAFER - A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator. | 04-07-2011 |
| 20110080232 | METHOD FOR MANUFACTURING A BAW RESONATOR WITH A HIGH QUALITY FACTOR - A method for manufacturing a bulk acoustic wave resonator, each resonator including: above a substrate, a piezoelectric resonator, and next to the piezoelectric resonator, a contact pad connected to an electrode of the piezoelectric resonator; and, between the piezoelectric resonator and the substrate, a Bragg mirror including at least one conductive layer extending between the pad and the substrate and at least one upper silicon oxide layer extending between the pad and the substrate, the method including the steps of: depositing the upper silicon oxide layer; and decreasing the thickness unevenness of the upper silicon oxide layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each pad. | 04-07-2011 |
| 20110078894 | METHOD FOR MANUFACTURING MONOLITHIC OSCILLATOR WITH BAW RESONATORS - A method of adjustment on manufacturing of a monolithic oscillator including circuit elements and a BAW resonator, this method including the steps of: a) forming the circuit elements and the resonator and electrically connecting them; b) covering the resonator with a frequency adjustment layer; c) measuring the output frequency of the oscillator; d) modifying the thickness of the frequency adjustment layer to modify the output frequency of the oscillator. | 04-07-2011 |
| 20110073976 | BACK-SIDE IMAGE SENSOR - A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam. | 03-31-2011 |
| 20110068381 | IMAGE SENSOR PIXEL CIRCUIT - A pixel circuit of an image sensor includes a sense node for storing a charge transferred from one or more photodiodes, a source follower transistor having its gate coupled to the sense node and its source node coupled to an output line of the pixel circuit via a read transistor, wherein a body contact of the source follower transistor is connected to the output line. | 03-24-2011 |
| 20110066917 | Method and Apparatus for Elementary Updating a Check Node During Decoding of a Block Encoded with a Non-binary LDPC Code - Method of elementary updating a check node of a non-binary LDPC code during, comprising receiving a first input message (U) and a second input message (V) each comprising n | 03-17-2011 |
| 20110063087 | RESISTIVE AND CAPACITIVE MODULATION IN AN ELECTROMAGNETIC TRANSPONDER - The selection of at least one back-modulation element of an electromagnetic transponder from among a plurality of resistive and/or capacitive modulation elements of the load of an oscillating circuit of the transponder, including selecting the modulation element(s) according to a binary message received from a read/write terminal. | 03-17-2011 |
| 20110062601 | GENERATING AN INTEGRATED CIRCUIT IDENTIFIER - The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier. | 03-17-2011 |
| 20110057759 | Integrated Inductive Device - Integrated inductive device comprising a central loop arranged between two outer loops mutually coupled to the central loop so as to form two patterns roughly in the form of an eight having a common portion corresponding to said central loop. | 03-10-2011 |
| 20110053053 | CELL HOLDER FOR FUEL CELL - A porous silicon wafer including, on its upper surface side, multiple recesses, this upper surface being coated with a porous silicon layer having pores smaller than those of the wafer bulk. | 03-03-2011 |
| 20110042747 | STRUCTURE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - A structure for protecting an integrated circuit against electrostatic discharges, including a device for removing overvoltages between first and second power supply rails; and a protection cell connected to a pad of the circuit including a diode having an electrode, connected to a region of a first conductivity type, connected to the second power supply rail and having an electrode, connected to a region of a second conductivity type, connected to the pad and, in parallel with the diode, a thyristor having an electrode, connected to a region of the first conductivity type, connected to the pad and having a gate, connected to a region of the second conductivity type, connected to the first rail, the first and second conductivity types being such that, in normal operation, when the circuit is powered, the diode is non-conductive. | 02-24-2011 |
| 20110037752 | CIRCUIT FOR DISCHARGING AN ELECTRICAL LOAD, POWER OUTPUT STAGE COMPRISING SUCH A DISCHARGE CIRCUIT FOR THE CONTROL OF PLASMA DISPLAY CELLS; AND RELATED SYSTEM AND METHOD - An embodiment of a discharge circuit comprises an output circuit with one output connected to an electrical load to absorb a discharge current given by the load when a logic signal commands a discharge of the load. The discharge circuit also comprises a control circuit to give the output circuit an appropriate control signal so that a slope of an output potential of the output circuit diminishes gradually when the logic signal commands a discharge of the load. Limiting the slope of the output potential gradually (and not suddenly) may limit the electromagnetic radiation generated by these variations. | 02-17-2011 |
| 20110037137 | BACK-SIDE ILLUMINATED IMAGE SENSOR PROTECTED AGAINST INFRARED RAYS - An image sensor including a first substrate having a first surface intended to be illuminated and a second surface on the side of which is formed a plurality of photodetection areas, said second surface being covered with a stack of interconnect levels including metal layers topped with insulating material, and of a second substrate placed on the insulating material of the last interconnect level, in which are formed vias in contact with connection elements of the interconnect levels, at least one of the interconnect levels including conductive shielding areas aligned with the photodetection areas. | 02-17-2011 |
| 20110032032 | DIGITAL PREDISTORTER FOR VARIABLE SUPPLY AMPLIFIER - An adaptive predistorter for applying a predistortion gain to an input signal to be amplified by a power amplifier having a variable supply voltage, the predistorter including: a predistortion gain block adapted to apply a complex gain to a complex input signal; a first table implemented in a first memory and comprising a 2-dimensional array of cells storing complex gain values, the first table adapted to output the complex gain values based on an amplitude of the input signal and the value of the variable supply voltage of the power amplifier; and a second table implemented in a second memory and including a 2-dimensional array of cells storing gain update values for updating the complex gain values of the first table, the gain update values being generated based on an output signal of said power amplifier. | 02-10-2011 |
| 20110022738 | DESIGN METHOD FOR A DMA-COMPATIBLE PERIPHERAL - The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated. | 01-27-2011 |
| 20110018637 | RADIOFREQUENCY SIGNAL POWER AMPLIFICATION METHOD AND DEVICE - A radiofrequency signal power amplification circuit may include a signal input for receiving the radiofrequency signal, an amplification stage coupled to the signal input and having at least one power transistor, a biasing stage for delivering a bias voltage to the amplification stage, and a processing stage. The processing stage may include a processing input coupled to the signal input, a processing output for delivering a bias current modulated at least in amplitude to the biasing stage, and an amplitude modulator coupled between the processing input and the processing output and configured to determine an envelope signal representative of the envelope of the radiofrequency signal, for modulating the amplitude of the envelope signal based on a variable voltage setpoint and for generating the amplitude-modulated bias current based on the modulated envelope signal. | 01-27-2011 |
| 20110012693 | BULK-MODE RESONATOR - A method for forming a resonator including a resonant element, the resonant element being at least partly formed of a body at least partly formed of a first conductive material, the body including open cavities, this method including the steps of measuring the resonator frequency; and at least partially filling said cavities. | 01-20-2011 |
| 20110010605 | METHOD FOR TRANSMITTING A BINARY INFORMATION WORD - A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the appearance of erroneous bits after the transmission, and is obtained by carrying out a Euclidian division of the information word (MI) to be transmitted by a generator polynomial coded on at most s bits. The generator polynomial is chosen so that it satisfies at least one of the following conditions, namely that the Hamming weight of the multiples of the generator polynomial is greater than or equal to a chosen threshold, or the generator polynomial allows the detection of at least 2 | 01-13-2011 |
| 20110006721 | CONTROL OF AN ASYNCHRONOUS MOTOR - The invention relates to a device for controlling the speed and the rotation direction of an asynchronous motor ( | 01-13-2011 |
| 20100328011 | MODE-SWITCHING TRANSFORMER - A mode-switching transformer comprising a first line in common mode and a second line in differential mode, each line comprising two sections in series respectively coupled with one of the two sections of the other line and all sections having the same lengths, the common mode line being connected in series with a capacitor, to lower the central frequency of the transformer passband, the λ/4 lengths of the sections being chosen to correspond to a central frequency greater than the central frequency desired for the transformer. | 12-30-2010 |
| 20100327995 | Guided Acoustic Wave Resonant Device and Method for Producing the Device - A guided acoustic wave resonant device is provided. The device comprises at least two filters (F | 12-30-2010 |
| 20100325525 | SOFT OUTPUT VITERBI DECODER ARCHITECTURE - A soft output Viterbi algorithm (SOVA) decoder arranged to decode symbols received over a transmission channel, the symbols indicating a state transition between two states of a plurality of states that determines a decoded data value, the SOVA decoder comprising a reliability memory unit including at least four stages of logic units, each logic unit including a single buffer and at least four stages including a plurality of full stages comprising a separate logic unit corresponding to each of the plurality of states; and a plurality of compact stages including half or less than half the number of logic units than the number of the plurality of states, each logic unit corresponding to two of the plurality of states. | 12-23-2010 |
| 20100325320 | VERIFICATION OF DATA READ IN MEMORY - A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element. | 12-23-2010 |
| 20100325183 | CHECKING OF THE SKEW CONSTANCY OF A BIT FLOW - A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element. | 12-23-2010 |
| 20100323477 | INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT - A method to fabricate an integrated electronic circuit includes superimposing insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of the first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of the second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. In one insulating layer, at least one of the levels comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other. | 12-23-2010 |
| 20100308411 | METHOD FOR FORMING AN INTEGRATED CIRCUIT LEVEL BY SEQUENTIAL TRIDIMENSIONAL INTEGRATION - A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator. | 12-09-2010 |
| 20100301987 | MILLIMETER WAVE TRANSFORMER WITH A HIGH TRANSFORMATION FACTOR AND A LOW INSERTION LOSS - A millimeter wave transformer including, at its primary, a turn formed of a conductive track made in at least one first metallization level, and, at its secondary, a winding in front of the primary turn, including at least one turn formed of a conductive track made in at least one second metallization level isolated from the at least one first level, the track width of the primary turn being at least equal to the total width of the secondary winding. | 12-02-2010 |
| 20100295631 | BULK ACOUSTIC WAVE RESONATOR AND METHOD FOR MANUFACTURING SAID RESONATOR - A resonant device including a stack of a first metal layer, a piezoelectric material layer, and a second metal layer formed on a silicon substrate, a cavity being formed in depth in the substrate, the thickness of the silicon above the cavity having at least a first value in a first region located opposite to the center of the stack, having a second value in a second region located under the periphery of the stack and having at least a third value in a third region surrounding the second region, the second value being greater than the first and the third values. | 11-25-2010 |
| 20100295520 | REGULATION DEVICE FOR A CHARGE PUMP GENERATOR AND CORRESPONDING REGULATION METHOD - A regulation device may be configured for regulating an output voltage of a charge pump voltage generator. The regulation device may include a first regulation loop capable of generating and delivering, to a first input of the voltage generator, an input voltage depending on the difference between the output voltage and a first reference voltage. The regulating device may also include a charger capable of generating and delivering, to a second input of the voltage generator, a substantially constant charge voltage. An electronic device may include the regulation device. | 11-25-2010 |
| 20100295416 | MICRORESONATOR - A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening. | 11-25-2010 |
| 20100293212 | BARREL SHIFTER - A barrel shifter receiving N symbols, arranged n | 11-18-2010 |
| 20100289779 | CURRENT DRIVE DISPLAY SYSTEM - This invention relates to systems, methods and apparatus for driving organic light emitting diodes (OLED) displays, in particular those using multi-line addressing (MLA) techniques. Embodiments of the invention are particularly suitable for use with so-called passive matrix OLED displays. A current drive system for an electroluminescent display, the system comprising: a plurality of current mirrors having a plurality of outputs for driving a plurality of drive electrodes of said display, each said current mirror having a reference signal input; and an automatic selector coupled to said current mirror outputs to automatically select a said output for providing reference signal inputs to said current mirrors. | 11-18-2010 |
| 20100289583 | VARIABLE GAIN RF AMPLIFIER - A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor. | 11-18-2010 |
| 20100289107 | PHOTODIODE WITH INTERFACIAL CHARGE CONTROL BY IMPLANTATION AND ASSOCIATED PROCESS - A photodiode includes a first doped layer and a second doped layer adjacent to the first doped layer and sharing a common face. A deep isolation trench is provided adjacent the photodiode having a face contiguous with the first doped layer and the second doped layer. A free face of the second doped layer is in contact with a conducting layer. A protective layer capable of generating a layer of negative charge is provided at the interface between, on one side, the first doped layer and the second doped layer and, on the other side, the deep isolation trench. | 11-18-2010 |
| 20100289106 | PHOTODIODE WITH INTERFACIAL CHARGE CONTROL AND ASSOCIATED PROCESS - A photodiode includes a first doped layer and a second doped layer that share a common face. A deep isolation trench has a face contiguous with the first and second doped layers. A conducting layer is in contact with a free face of the second doped layer. A protective layer is provided at an interface with the first doped layer and second doped layer. This protective layer is capable of generating a layer of negative charge at the interface. The protective layer may further be positioned within the second doped layer to form an intermediate protective structure. | 11-18-2010 |
| 20100289101 | IMAGE SENSOR - An image sensor including an array of pixels, wherein each pixel includes, in a vertical stack: a central photosensitive area; a stack of interconnects on top of the periphery of the photosensitive area, extending upwards up to a first height; a filtering layer on top of the photosensitive area, extending upwards from a height lower than the first height; and a microlens overlying the filtering layer in vertical projection, the optical axis of this microlens being such that the light rays received by the pixel reach the photosensitive area, substantially at its center. | 11-18-2010 |
| 20100289096 | VIBRATING NANO-SCALE OR MICRO-SCALE ELECTROMECHANICAL COMPONENT WITH ENHANCED DETECTION LEVEL - A vibrating nano-scale or micro-scale electromechanical component including a vibrating mechanical element that cooperates with at least one detection electrode. The detection electrode is flexible and is configured to vibrate in phase opposition relative to the vibrating mechanical element. Such a component may find, for example, application to resonators or motion sensors. | 11-18-2010 |
| 20100269020 | LDPC DECODER - A low density parity check decoder for performing LDPC decoding based on a layered algorithm applied to a parity check matrix, the decoder including a channel memory, a metrics memory, first and second operand supply paths each arranged to provide operands based on channel values and metrics values; a processor block including a plurality processing units in parallel and arranged to receive operands from the first supply path and to determine updated metric values, a buffer arranged to store at least one of the operands from the first supply path; and an adder coupled to an output of the processor block and arranged to generate updated channel values by adding the updated metrics values to operands from a selected one of the buffer and the second supply path. | 10-21-2010 |
| 20100265758 | Method for implementing an SRAM memory information storage device - A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column. | 10-21-2010 |
| 20100245329 | PLASMA DISPLAY PANEL CONTROL CIRCUIT - A method and circuit to control a circuit for addressing at least one line electrode of a plasma display panel having, for each line, a line selection stage formed of two switches in series between two input terminals of the selection stage, the method including alternating use of the two switches of the selection stage of each line to flow a current from or to an inductive element of the addressing circuit without connecting the input terminals together. | 09-30-2010 |
| 20100216054 | FUEL CELL WITH LARGE EXCHANGE SURFACE AREA - A support wafer made of silicon wafer comprising, on a first surface a porous silicon layer having protrusions, porous silicon pillars extending from the porous silicon layer to the second surface of the wafer, in front of each protrusion. Layers constituting a fuel cell can be formed on the support wafer. | 08-26-2010 |
| 20100208883 | PROTECTION OF A MODULAR EXPONENTIATION CALCULATION PERFORMED BY AN INTEGRATED CIRCUIT - The invention concerns a method and a circuit for protecting a numerical quantity (d) contained in an integrated circuit ( | 08-19-2010 |
| 20100200964 | METHOD OF PRODUCING A POROUS DIELECTRIC ELEMENT AND CORRESPONDING DIELECTRIC ELEMENT - A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improve the overall dielectric constant of the resulting dielectric element. | 08-12-2010 |
| 20100200943 | Photosensitive cell with light guide - An integrated circuit having a photosensitive cell with an entry face, a photosensitive element and at least two elements forming a light guide and placed between the entry face and the photosensitive element. The second element is located between the first element and the entry face such that the two elements guide the light coming from the entry face onto the photosensitive element and each element forms a light guide. The inner volume has a first surface located on the same side as the photosensitive element, a second surface located on the same side as the entry face, and a lateral surface joining said first surface to said second surface and separating the inner volume from the outer volume. The first surface of the inner volume of the second element has a smaller area than that of the second surface of the inner volume of the first element. | 08-12-2010 |
| 20100199051 | CACHE COHERENCY IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM - A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories. | 08-05-2010 |
| 20100182660 | CORRECTION OF WHITE BALANCE DEVIATION IN A CAPTURED IMAGE - A method is provided for correcting an image. At least some pixels in a captured image are scanned and there is selected each scanned pixel having at least one associated light intensity value greater than an intensity threshold value based on a comparison between the light intensity values for color indicators associated with the scanned pixel. Three correction information items are obtained by summing the light intensity values associated with the pixels selected by color indicator, and a correction of the white balance deviation affecting the captured image is determined based on the correction information items. A pixel is selected if both the difference between a mean light intensity value and a lowest light intensity value associated with the scanned pixel and the difference between a highest light intensity value and the mean light intensity value associated with the scanned pixel are less than a difference threshold value. | 07-22-2010 |
| 20100182474 | IMAGE CAPTURE DEVICE COMPRISING PIXEL COMBINATION MEANS - An image capture device includes n image sensors arranged to capture images respectively of a same scene according to at least three different colors, each of the sensors comprising a pixel array, each pixel being associated with a MOS transfer transistor, the transfer transistors of n neighboring pixels being associated with a same output; and a read circuit associated with control circuitry for reading separately, the output of each transfer transistor, or cumulatively, the outputs of from two to n neighboring transfer transistors. | 07-22-2010 |
| 20100180117 | RANDOM SIGNAL GENERATOR - A random signal generator uses a folded MOS transistor, whose drain-source current includes a random component, as an electronic noise source. The random signal generator generates a random binary signal from the random component. The invention may be applied, in particular, to smart cards. | 07-15-2010 |
| 20100171548 | ANALOG FIR FILTER - An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter. | 07-08-2010 |
| 20100167488 | INTEGRATED CIRCUIT COMPRISING A GRADUALLY DOPED BIPOLAR TRANSISTOR AND CORRESPONDING FABRICATION PROCESS - An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone | 07-01-2010 |
| 20100165709 | ROBUST SRAM MEMORY CELL CAPACITOR PLATE VOLTAGE GENERATOR - An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies. | 07-01-2010 |
| 20100165204 | System and process for image rescaling using adaptive interpolation kernel with sharpness and overshoot control - Provided are a digital video rescaling system, a method of rescaling video images, and a chip comprising a computer executable medium embedded therein computer executable instructions for rescaling video images. | 07-01-2010 |
| 20100165156 | IMAGE CAPTURE DEVICE COMPRISING FOCUSING ADJUSTMENT MEANS - An image capture device includes first and second image sensors arranged to capture first and second images respectively of a same scene, each of the first and second images including pixel values; an objective lens associated with each of the image sensors, one objective lens being axially offset with respect to the other and having the same focal length as the other; a unit for analyzing the sharpness of each image; and a unit for selecting the image of desired sharpness. | 07-01-2010 |
| 20100159666 | INTEGRATION OF CAPACITIVE ELEMENTS IN THE FORM OF PEROVSKITE CERAMIC - The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate. | 06-24-2010 |
| 20100158158 | WIDE-BAND SIGNAL PROCESSOR - A signal processor for processing a digital input signal including samples sampled at a sampling frequency, the signal processor comprising a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency; first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency; decimation circuitry arranged to decimate the first signal and the shifted second signal; and processing circuitry arranged to process the decimated first and second signals. | 06-24-2010 |
| 20100155950 | IMPLEMENTATION OF A METAL BARRIER IN AN INTEGRATED ELECTRONIC CIRCUIT - A metal barrier is realized on top of a metal portion of a semiconductor product, by forming a metal layer on the surface of the metal portion, with this metal layer comprising a cobalt-based metal material. Then, after an optional deoxidation step, a silicidation step and a nitridation step of the cobalt-based metal material of the metal layer are performed. The antidiffusion properties of copper atoms (for example) and the antioxidation properties of the metal barrier are improved. | 06-24-2010 |
| 20100144403 | ISOLATED MONOLITHIC ELECTRIC POWER - An isolated monolithic electrical converter including a substrate made of a resistive material, the underside of which has two input electrodes spaced apart from each other, constituting the primary, an insulating layer on the top side of the substrate, and, on the insulating layer, at least two elements made of respectively p-doped and n-doped semiconductor thermoelectric materials electrically connected in series, the ends of the series connection constituting the secondary of the converter. | 06-10-2010 |
| 20100144388 | MONOLITHIC PHOTODETECTOR - A photodetector including a photodiode formed in a semiconductor substrate and a waveguide element formed of a block of a high-index material extending above the photodiode in a thick layer of a dielectric superposed to the substrate, the thick layer being at least as a majority formed of silicon oxide and the block being formed of a polymer of the general formula R | 06-10-2010 |
| 20100140774 | METHOD OF PRODUCING EXTERNAL PADS ON A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - External electrical connection pads are provided on a semiconductor device. A well is formed in an outer surface for the semiconductor device to at least partially expose an internal electrical connection pad. An electrical connection tab is formed which has an internal branch extending over the internal pad, an external branch extending over a top of the outer surface and extending from one side edge of the well, and a linking branch extending over a sidewall of the wells between the external branch and the internal branch. | 06-10-2010 |
| 20100138617 | METHOD FOR INITIALIZING A MEMORY - A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event. | 06-03-2010 |
| 20100135427 | COFDM DEMODULATOR WITH AN OPTIMAL FFT ANALYSIS WINDOW POSITIONING - The invention relates to a method for the COFDM demodulation of a signal received from a transmission channel. The inventive method includes performing the fast Fourier transform of the signal received in a window corresponding to a symbol, each symbol being associated with a guard time reproducing one part of the symbol; supplying a set of estimated values for the module impulse response; determining coefficients, each coefficient being obtained from the product of the aforementioned set and a filtering function (FE) for a determined relative position of the filtering function in relation to the set; determining the maximum coefficient and the corresponding relative position; and positioning the window as a function of the relative position, the filtering function including a central part (LMAX) which has a constant amplitude and a duration equal to the duration of the guard time and which is surrounded by non-zero decreasing edges. | 06-03-2010 |
| 20100135317 | PCM TYPE INTERFACE - An interface device having a first and second data terminal configured for the communication of data in duplex mode, with one of the first and second data terminals always assigned to each direction of the communication, the first and second data terminals configurable during operation such that, in a first mode of operation, the first data terminal is configured to send but not to receive data and the second data terminal is configured to receive but not send data, while in a second mode of operation the first data terminal is configured to receive but not to send data and the second data terminal is configured to send but not to receive data. | 06-03-2010 |
| 20100135087 | READING OF THE STATE OF A NON-VOLATILE STORAGE ELEMENT - A method for reading of the state of a non-volatile memory element including conditioning the frequency of a first oscillator to the state of this element, and comparing the frequency of the first oscillator with the predetermined frequency of a second oscillator, selected between two possible frequency values for the first oscillator, according to the state of the storage element. | 06-03-2010 |
| 20100133634 | PRODUCTION OF A SELF-ALIGNED CUSIN BARRIER - A semiconductor product includes a portion made of copper, a portion made of a dielectric and a self-aligned barrier between the copper portion and the dielectric portion. The self-aligned barrier includes a first copper silicide layer comprising predominantly first copper silicide molecules, and a second copper silicide layer comprising predominantly second copper silicide molecules. The proportion of the number of silicon atoms is higher in the second silicide molecules than in the first silicide molecules. The second copper silicide layer is positioned between the copper portion and the first copper silicide layer. A nitride layer may overlie at least part of the first copper silicide layer. | 06-03-2010 |
| 20100109770 | RECONFIGURABLE POWER AMPLIFIER AND USE OF SUCH AMPLIFIER FOR MAKING A MULTI-STANDARD AMPLIFICATION STAGE FOR MOBILE PHONE COMMUNICATIONS - A reconfigurable power amplifier includes at least one amplification circuit (E | 05-06-2010 |
| 20100108867 | INTEGRATED ELECTROOPTIC SYSTEM - An integrated circuit includes at least one photosensitive element capable of delivering an electrical signal when light of at least one wavelength of the visible spectrum reaches it, and an electrooptic system functioning as an electrochemical shutter. The electrooptic system is located in the path of at least one light ray capable of reaching the photosensitive element and possesses at least one optical property, dependent on electrochemical reaction, that can be modified by an electrical control signal. The optical property is preferably transmission. | 05-06-2010 |
| 20100102206 | NEAR INFRARED/COLOR IMAGE SENSOR - A near infrared/color photodetector made in a monolithic form in a lightly-doped substrate of a first conductivity type covering a holder and comprising a face on the side opposed to the holder. The photodetector includes at least first and second photodiodes for the storage of electric charges photogenerated in the substrate, the second photodiode being adjacent to said face; and a first region extending at least between the second photodiode and the holder, preventing the passage of said charges between a first substrate portion being located between said region and the holder and a second substrate portion extending between said face and the first region, the first photodiode being adapted to store at least charges photogenerated in the first substrate portion and the second photodiode being adapted to store charges photogenerated in the second substrate portion. | 04-29-2010 |
| 20100097843 | EXTRACTION OF A BINARY CODE BASED ON PHYSICAL PARAMETERS OF AN INTEGRATED CIRCUIT - An integrated cell and method for extracting a binary value based on a value difference between two resistors values, including connection circuitry for a binary reading of the sign of the difference between the resistors, and connection circuitry for a modification of the value of one of the resistors to make the sign of the difference invariable. | 04-22-2010 |
| 20100097093 | INPUT/OUTPUT CIRCUITRY WITH COMPENSATION BLOCK - Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein the plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at the first node of the external resistor. | 04-22-2010 |
| 20100078673 | ACTIVE SEMICONDUCTOR COMPONENT WITH A REDUCED SURFACE AREA - A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established. | 04-01-2010 |
| 20100069031 | MIXER-AMPLIFIER FOR AN RF RECEIVE CHAIN - A mixer-amplifier of an RF signal including at least an amplifier circuit and a mixing circuit controlled at a local oscillator frequency, for amplifying a signal applied on at least one input terminal and converting a first frequency of this signal into a second, lower, frequency, and including a reverse feedback loop switched at the local oscillator frequency. | 03-18-2010 |
| 20100066472 | OPTIMISED SOLENOID WINDING - The inductive micro-device comprises a rectilinear solenoid winding comprising a plurality of disjointed rectangular turns each having predetermined dimensions. At least one of the dimensions of the turns is variable and is determined individually for each turn according to the position of the turn along the winding and to predetermined magnetic characteristics of the winding, in particular a homogeneous magnetic field and/or an optimum quality factor. Said variable dimension of the turns is chosen from the width, length, thickness, height of turn and the value of the gap between two adjacent turns. | 03-18-2010 |
| 20100054038 | PROGRAMMING OF A CHARGE RETENTION CIRCUIT FOR A TIME MEASUREMENT - A method of controlling an electronic charge retention circuit for time measurement, including at least a first capacitive element, the dielectric of which has a leakage, and at least a second capacitive element, the dielectric of which has a higher capacitance than the first, the two elements having a common electrode defining a floating node that can be connected to an element for measuring its residual charge, in which a charge retention period is programmed or initialized by injecting or extracting charges via the first element. | 03-04-2010 |
| 20100054024 | CIRCUIT FOR READING A CHARGE RETENTION ELEMENT FOR A TIME MEASUREMENT - A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual charges, the reading circuit including; two parallel branches between two supply terminals, each branch including at least one transistor of a first type and one transistor of a second type, the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal, the respective drains of the transistors of the first type being connected to the respective inputs of a comparator whose output provides an indication of the residual voltage in the charge retention element. | 03-04-2010 |
| 20100048145 | ANALOG FIR FILTER - An analog finite impulse response filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter. | 02-25-2010 |
| 20100045390 | CIRCUIT AND METHOD FOR MEASURING THE PERFORMANCE PARAMETERS OF TRANSISTORS - An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device. | 02-25-2010 |
| 20100045342 | LEVEL TRANSLATOR CIRCUIT - A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit. | 02-25-2010 |
| 20100044886 | SEMICONDUCTOR DEVICE HAVING PAIRS OF PADS - An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These zones extend perpendicularly to the pitch direction. The electrical connection pads are grouped in adjacent pairs. An insulation space is located between the pads of each pair of electrical connection pads. In a direction perpendicular to the pitch direction, the pads in the pair are spaced apart. The pads of each pair of electrical connection pads extend over a pair of adjacent zones and are associated with two adjacent vias. | 02-25-2010 |
| 20100041189 | SELECTIVE REMOVAL OF A SILICON OXIDE LAYER - A method of fabricating a device, including the steps of forming a first silicon oxide layer within a first region of the device and a second silicon oxide layer within a second region of the device, implanting doping ions of a first type into the first region, implanting doping ions of a second type into the second region, and etching the first and second regions for a determined duration such that the first silicon oxide layer is removed and at least a part of the second silicon oxide layer remains. | 02-18-2010 |
| 20100039337 | ELECTROMAGNETIC FIELD GENERATION ANTENNA FOR A TRANSPONDER - An antenna generating an electromagnetic field for an electromagnetic transponder and a terminal provided with such an antenna. The antenna comprises a first inductive element designed to be connected to two terminals employing an energizing voltage, and a parallel resonant circuit coupled with the first inductive element. | 02-18-2010 |
| 20100039306 | ANALOG-TO-DIGITAL CONVERTER - A method of analog-to-digital conversion over n bits of an analog signal, including the steps of: comparing the amplitude of the analog signal with a threshold representing the amplitude of the full-scale analog signal divided by 2 | 02-18-2010 |
| 20100038797 | CONTROLLING LATERAL DISTRIBUTION OF AIR GAPS IN INTERCONNECTS - Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant. | 02-18-2010 |
| 20100032734 | MINIATURE IMAGE SENSOR - An image sensor including at least one photodiode and at least one transistor formed in and on a silicon substrate, the assembly of the photodiode and of the transistor being surrounded with a heavily-doped insulating wall, wherein the silicon substrate has a crystal orientation (110). | 02-11-2010 |
| 20100027174 | CIRCUIT FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES IN CMOS TECHNOLOGY - The integrated circuit may include at least one electronic protection circuit for protecting against at least one electrostatic discharge and being able to discharge the overvoltage current generated by the electrostatic discharge. The electronic protection circuit includes a controlled short-circuiting switch embodied in CMOS technology including a CMOS technology TRIAC or a CMOS technology thyristor arranged in anti-parallel with a CMOS technology diode, and a triggering circuit for controlling the short-circuiting switch. | 02-04-2010 |
| 20100025773 | PROCESS FOR PRODUCING A CONTACT PAD ON A REGION OF AN INTEGRATED CIRCUIT, IN PARTICULAR ON THE ELECTRODES OF A TRANSISTOR - A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad. | 02-04-2010 |
| 20100022214 | METHOD AND DEVICE FOR PROCESSING THE DC OFFSET OF A RADIOFREQUENCY RECEPTION SUBSYSTEM - A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations. | 01-28-2010 |
| 20100020903 | METHOD AND DEVICE FOR PROCESSING THE DC OFFSET OF A RADIOFREQUENCY RECEPTION SUBSYSTEM - A method may compensate for direct current (DC) offset in a radio frequency reception device. The method may include partitioning an analog portion of the reception device into a plurality of zones, for each zone, calibrating initial DC offset compensation to be applied within an operating range of a respective zone, the operating range of the other zones being limited to a threshold operating range, and determining DC offset compensation to be applied to the reception device throughout the operating range based on the basic DC offset compensations. | 01-28-2010 |
| 20100020648 | CHARGE RETENTION CIRCUIT FOR A TIME MEASUREMENT - An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node. | 01-28-2010 |
| 20100019869 | BULK MODE RESONATOR - A resonator including a resonant element having a bulk and columns of a material having a Young's modulus with a temperature coefficient having a sign opposite to that of the bulk. | 01-28-2010 |
| 20100011171 | CACHE CONSISTENCY IN A MULTIPROCESSOR SYSTEM WITH SHARED MEMORY - A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state. | 01-14-2010 |
| 20100003806 | DETERMINISTIC GENERATION OF AN INTEGRATED CIRCUIT IDENTIFICATION NUMBER - The generation of an identification number of a chip supporting at least one integrated circuit, including the step of causing a cutting of at least one conductive section by cutting of the chip among several first conductive sections parallel to one another and perpendicular to at least one edge of the chip, the first sections being individually connected, by at least one of their ends, to the chip, and exhibiting different lengths, the position of the cutting line with respect to the chip edge conditioning the identification number. | 01-07-2010 |
| 20100003573 | METHOD FOR PROCESSING PORTIONS OF WALLS OF AN OPENING FORMED IN A SILICON SUBSTRATE - A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening. | 01-07-2010 |
| 20090327672 | SECURED PROCESSING UNIT - A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the information is detected, triggering the execution of a hidden subprogram by the processing unit. The method may be applied to the securization of an integrated circuit. | 12-31-2009 |
| 20090323381 | ADAPTABLE POWER SUPPLY CIRCUIT - A power supply circuit and a transponder having a circuit for rectifying an A.C. voltage and two power storage elements, the rectifying circuit providing a rectified voltage to at least one of the storage elements and an output voltage being provided by at least one of the storage elements, and at least one switching element for switching the circuit operation between a state of provision of a relatively high voltage and a state of provision of a relatively low voltage, the second state configuring the rectifying circuit in halfwave operation. | 12-31-2009 |
| 20090322580 | ANALOG FILTER WITH PASSIVE COMPONENTS FOR DISCRETE TIME SIGNALS - A filter intended to receive a discrete time signal at a sampling dock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive dock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one dock cycle from one filtering unit to the next one. | 12-31-2009 |
| 20090314008 | SELF-COOLED VERTICAL ELECTRONIC COMPONENT - A self-cooled electronic component comprising a vertical monolithic circuit, in which the vertical monolithic circuit is electrically connected in series with a Peltier cooler so that the D.C. current flowing through the circuit supplies the cooler and in which the circuit and the cooler are placed against each other so that the cold surface of the cooler is in thermal contact with the circuit. | 12-24-2009 |
| 20090311572 | INTEGRATED FUEL CELL AND MANUFACTURING METHOD - A fuel cell having its active stack resting on a thin conductive layer, bearing on a wafer provided with through gas inlet channels, the thin conductive layer protruding in the active stack in front of each channel and being transparent to the gas. | 12-17-2009 |
| 20090310319 | DEVICE FOR ELECTRICAL CONNECTION OF AN INTEGRATED CIRCUIT CHIP - A device is provided for electrically connecting an integrated circuit chip. The device includes a main board, an intermediate board, and electrical connection balls in a space separating the boards. In the space, a peripheral zone comprises a peripheral matrix of balls, a central zone comprises a central matrix of balls, a first secondary zone comprises a matrix of electrical connection vias linked to the balls of the two adjacent rows of balls of the peripheral matrix, and a second secondary zone comprises a matrix of electrical connection vias linked to balls of the central matrix. The first secondary zone and the second secondary zone are separated by an intermediate zone that includes at least a first part having at least one complementary row of electrical connection balls, and a second part having complementary electrical connection vias linked to the balls of this complementary row. | 12-17-2009 |
| 20090302959 | SYNCHRONOUS DISTRIBUTED OSCILLATOR - A distributed oscillator includes an odd number of serially connected amplifying elements. An output of a last amplifying element is looped back to an input of a first amplifying element via a first transmission line. The oscillator oscillates at a first frequency f | 12-10-2009 |
| 20090289314 | MICRO-ELECTROMECHANICAL RESONANCE DEVICE WITH PERIODIC STRUCTURE - A Micro Electro Mechanical Systems resonance device includes a substrate, and an input electrode, connected to an alternating current source having an input frequency. The device also includes an output electrode, and at least one anchoring structure, connected to the substrate. The device further includes a vibratile structure connected to an anchoring structure by at least one junction, having a natural acoustic resonant frequency. The vibration under the effect of the input electrode, when it is powered, generates, on the output electrode, an alternating current wherein the output frequency is equal to the natural frequency. The vibratile structure and/or the anchoring structure includes a periodic structure. The periodic structure includes at least first and second zones different from each other, and corresponding respectively to first and second acoustic propagation properties. | 11-26-2009 |
| 20090288805 | SEMICONDUCTOR PACKAGE WITH A CHIP ON A SUPPORT PLATE - A semiconductor package includes a support plate made of an electrically non-conducting material. Electrical connection vias are formed outside a chip fixing region provided on the front face of the support plate. Electrical connection wires connect pads on a front of the chip to pads on the front of the support plate associated with the electrical connection vias. The front face of the support plate is further provided with at least one intermediate front layer made of a thermally conducting material extending at least partly below the chip. The rear face of the support plate is provided with at least one rear layer made of a thermally conducting material extending at least partly opposite the front layer. The front and rear layers are connected by vias made of a thermally conducting material that fills through-holes made through the plate. | 11-26-2009 |
| 20090284331 | COPLANAR WAVEGUIDE - An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes. | 11-19-2009 |
| 20090267046 | MEMORY STRUCTURE WITH A PROGRAMMABLE RESISTIVE ELEMENT AND ITS MANUFACTURING PROCESS - A memory structure has an access transistor connected in series with a programmable resistive element, wherein the programmable resistive element comprises on a semiconductor substrate; an insulated layer with a cavity comprising: a first layer lining the lateral surfaces and the bottom of the said cavity and impermeable to the diffusion of metal; a second layer made of porous material on the said first layer; a third layer of metallic material allowing to realize a contact electrode susceptible to spread within the said formed porous material of the second layer. Diffusion of metallic ions within the said second layer is controlled by the joint action of an electric field and temperature. A manufacturing process is also described. | 10-29-2009 |
| 20090262247 | SYSTEM AND PROCESS FOR IMAGE RESCALING WITH EDGE ADAPTIVE PHASE CONTROL IN INTERPOLATION PROCESS - A video image processing system is described that generates the interpolated video images with sharp and jaggedness-free edges. A method of video image processing is also described that interpolates video images to generate the video images with sharp and jaggedness-free edges. The video image processing system receives and makes input image data available for further processing; analyzes the local features of the input image data; filters the input image data before performing interpolation process; modifies the phase value adaptive to the local edge distance; rescales the input image data in horizontal interpolation using the modified phase value; and rescales the horizontally interpolated image data in vertical interpolation using modified phase value. | 10-22-2009 |
| 20090261903 | VARIABLE GAIN RF AMPLIFIER - A variable gain amplifier having an input node, a variable current source including a control input coupled to the input node, first and second branches coupled in parallel between a first supply terminal and the variable current source, the first and second branches defining a differential pair arranged to be controlled by first and second differential gain signals and having first and second output terminals, one of the output terminals including an output node of the variable gain amplifier; and a potential divider having a middle node coupled to the first and second output terminals, wherein the middle node is also coupled to the input node by a capacitor. | 10-22-2009 |
| 20090256650 | FILTERING CIRCUIT WITH COUPLED ACOUSTIC RESONATORS - A filter with coupled resonator having a substrate; an acoustic mirror intended to support acoustic resonators, and to isolate these resonators from the substrate; a first structure with an upper resonator and a lower resonator coupled to one another through at least one layer of acoustic coupling; a second structure with an upper resonator and a lower resonator coupled to one another through at least one layer of acoustic coupling; the lower resonators of the first and second structure having the same electrodes. The first and second structures are connected via a fifth resonator for which electrodes and the piezoelectric layer of the lower resonators are of the first and second structure. | 10-15-2009 |
| 20090256224 | INTEGRATED CIRCUIT COMPRISING MIRRORS BURIED AT DIFFERENT DEPTHS - A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer. | 10-15-2009 |
| 20090254782 | METHOD AND DEVICE FOR DETECTING AN ERRONEOUS JUMP DURING PROGRAM EXECUTION - The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to a jump address instruction for jumping a program memory read address, an instruction for storing the presence of the jump address instruction; and activating an error signal if an address jump has been detected and if the presence of a jump address instruction has not been stored. The present disclosure also relates to securing integrated circuits. | 10-08-2009 |
| 20090251942 | METHOD OF PROGRAMMING A MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE AND INTEGRATED CIRCUIT INCORPORATING SUCH A MEMORY - A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device. | 10-08-2009 |
| 20090251235 | BULK ACOUSTIC WAVE RESONATOR FILTER BEING DIGITALLY RECONFIGURABLE, WITH PROCESS - A filtering circuit with BAW type acoustic resonators having at least a first quadripole and a second quadripole connected in cascade, each quadripole having a branch series with a first acoustic resonator of type BAW and a branch parallel with each branch having an acoustic resonator of type BAW, the first acoustic resonator having a frequency of resonance series approximately equal to the frequency of parallel resonance of the second acoustic resonator, the branch parallel of the first quadripole having a first capacitance connected in series with the second resonator and, in parallel with the capacitance, a first switching transistor to short circuit the capacitance. | 10-08-2009 |
| 20090250737 | SECURE MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE - The integrated circuit includes a memory device of the irreversibly electrically programmable type. This device includes several memory cells, each memory cell having a dielectric zone positioned between a first electrode and a second electrode. Each memory cell is further associated with an access transistor. At least one first electrically conductive link electrically couples to the first electrodes of at least two memory cells, these first two electrodes being coupled to one and the same bias voltage. The first electrically conductive link is positioned in substantially a same plane as the first electrodes of the two memory cells. | 10-08-2009 |
| 20090245342 | EQUALIZER ADAPTING CIRCUIT - A channel equalizer having a filter arranged to filter an input signal, the filter including a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving the coefficients and an output for outputting a filtered signal; and coefficient generating circuitry including a graduation unit arranged to receive the input signal and an error signal indicating an error in the filtered signal, to accumulate gradient values relating to each of the coefficients based on a plurality of error values of the error signal, each of the gradient values indicating a required change in one of the coefficients, and to sequentially output the gradient values; and coefficient update unit arranged to sequentially update each of the filter coefficients in turn, based on the gradient values. | 10-01-2009 |
| 20090245341 | CHANNEL EQUALIZER - A channel equalizer arranged to receive a data signal encoded by a plurality of amplitude levels, the circuitry including a filter having a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving an error signal for adapting the coefficients, and an output for outputting a filtered signal; and blind error generation circuitry arranged to generate the error signal, the blind error generation circuitry including: error estimating circuitry arranged to estimate the error of the filtered signal based on maximum likelihood; and adding circuitry coupled to the error estimating circuitry and to the output of the filter and arranged to add at least part of the filtered signal to the error estimated by the error estimating circuitry to generate the error signal. | 10-01-2009 |
| 20090244347 | IMAGE SENSOR WITH AN IMPROVED SENSITIVITY - An image sensor having a surface intended to be illuminated and pixels, each pixel including a photosensitive area formed in an active area of the substrate, at least one first pixel including a first microlens located on the surface, the sensor including at least one second pixel including a transparent portion forming a pedestal located at least partly on the surface and a second microlens at least partially covering the pedestal. | 10-01-2009 |
| 20090212330 | METHOD OF FABRICATING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT - A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device. | 08-27-2009 |
| 20090200454 | PIXEL CIRCUIT FOR GLOBAL ELECTRONIC SHUTTER - An image sensor formed of an array of pixels, each pixel including a photodiode coupled between a first reference voltage and a first switch, the first switch being operable to connect the photodiode to a first node; a capacitor arranged to store a charge accumulated by the photodiode, the capacitor being coupled between a second reference voltage and a second node; a second switch coupled between the first and second nodes, the second switch being operable to connect the capacitor to the first node; and read circuitry coupled for reading the voltage at the second node. | 08-13-2009 |
| 20090196085 | SRAM MEMORY CELL PROTECTED AGAINST CURRENT OR VOLTAGE SPIKES - A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell. | 08-06-2009 |
| 20090192939 | METHOD OF TRANSFERRING DATA AND CORRESPONDING DEVICE - The method of transferring data between a first and a second set of elements via a switch that includes a set of paths each associated with a weighting coefficient representing a data stream for each path. The method includes a credit flow control between the first set of elements and the switch and a credit flow control between the switch and the second set of elements. An available credit coefficient is computed for each element of the first set on the basis of a credit allocated by each element of the second set and of the weighting coefficient of each path. | 07-30-2009 |
| 20090184702 | VOLTAGE REGULATOR WITH SELF-ADAPTIVE LOOP - A voltage regulator includes an amplifier and a regulation loop. The regulator includes a first PMOS transistor connected to a terminal supplying an input voltage, a second PMOS transistor connected in series with the first PMOS transistor. A node between those two transistors defines an output terminal. A first source of a first polarization current of fixed value is connected to the gate of the first transistor, and a second source of a second polarization current of fixed value connects the second transistor to ground. A third NMOS transistor is connected between the two current sources. A circuit is provided to modify automatically at least one of the polarization currents in relation to the load current. | 07-23-2009 |
| 20090184385 | OPTICAL SEMICONDUCTOR PACKAGE WITH COMPRESSIBLE ADJUSTMENT MEANS - An optical semiconductor package includes a support with a passage to receive a ring holding a lens situated facing an optical sensor. The support has, in the passage, at least one local release recess and the ring is equipped peripherally with a locally projecting, elastically deformable element. The local release recess and the elastically deformable element are such that, when the ring occupies an angular mounting position, the locally projecting elastically deformable element is engaged in the local recess of the support and, when the ring is pivoted from the aforementioned angular mounting position, the locally projecting elastically deformable element is moved out of the recess of the support and is compressed against the wall of the passage in order to secure the ring relative to the support. | 07-23-2009 |
| 20090174503 | INTEGRABLE TUNABLE FILTER CIRCUIT COMPRISING A SET OF BAW RESONATORS - A tunable filter circuit having inputs IN | 07-09-2009 |
| 20090167261 | CURRENT MEASURING DEVICE - An embodiment of a current measuring device, defined by a gain, including an amplification module including an input for receiving a control signal, an input connected to an output node, brought to an output potential and traversed by an output current, a feedback node traversed by a mirror current associated with the output current by a proportionality coefficient equal to the gain, and an output traversed by the mirror current, and capable of bringing the feedback node to the output potential in response to the control signal. The measuring device also includes a gain modification module, mounted between the first potential and the feedback node, including at least one input for receiving an activation signal, and capable of modifying the value of the gain in response to an activation signal. | 07-02-2009 |
| 20090166880 | ELECTRICAL BONDING PAD - An electrical bonding pad for an integrated circuit, comprising an encapsulation layer for receiving electrical signals and for covering a portion of a stack of conductive layers. The pad further comprises a conductive area in the stack, with the conductive area being at least partially covered by the encapsulation layer. The conductive area is intended for the passage of electrical signals received by the encapsulation layer and traveling towards a circuit core, and is electrically insulated from the encapsulation layer in a manner that at least partially decouples the electrical signals received from the encapsulation layer. | 07-02-2009 |
| 20090164858 | PROTECTING AN INTEGRATED CIRCUIT TEST MODE - An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit. | 06-25-2009 |
| 20090154273 | MEMORY INCLUDING A PERFORMANCE TEST CIRCUIT - A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells. | 06-18-2009 |
| 20090153715 | PIXEL READ CIRCUITRY - A method of reading voltages from an image sensor having an array of pixels, each pixel Having at least one photodiode connectable to a storage node, the method including: controlling each pixel in a row of pixels to store and output a first voltage value at a first instance, a second voltage value at a second instance, and a third voltage value at a third instance, the first, second and third voltage values being representative of charge accumulated by the photodiodes during an integration phase; comparing the first voltage value from each pixel with a reference threshold; sampling for each pixel, based on the comparison, one of the second and third voltage values: and generating an output pixel value based on the sampled one of the second and third voltage values | 06-18-2009 |
| 20090153119 | METHOD AND DEVICE FOR MEASURING CURRENT FOR A DC-DC CONVERTER - An embodiment of a current sensing device for a DC-DC converter comprising an output node through which passes an output current and taken to an output potential equal respectively to first and second values. The current sensing device comprises an amplifying module comprising a retroaction node through which passes a mirror current that is proportional to the output current and taken to the potential present on a first input of the amplifying module. The device also comprises a first intermediate module mounted between the first potential and the output node, comprising an intermediate node connected to the first input and taken to an intermediate potential equal to third and fourth values respectively correlated to the first and second values, wherein the difference between the third and fourth values is smaller than the difference between the first and second values. | 06-18-2009 |
| 20090152998 | MICRORESONATOR - A microresonator comprising a single-crystal silicon resonant element and at least one activation electrode placed close to the resonant element, in which the resonant element is placed in an opening of a semiconductor layer covering a substrate, the activation electrode being formed in the semiconductor layer and being level at the opening. | 06-18-2009 |
| 20090146819 | Antenna for an Electronic Tag - The invention concerns an inductive element for forming an electromagnetic transponder antenna, comprising a first group of mutually parallel conductors coplanar in a first plane, a second group of mutually parallel conductors coplanar in a second plane parallel to the first plane, and an insulating material separating the two groups of conductors, one end of each conductor of the first group being connected to one end of a conductor of the second group whereof the other end is connected to one end of another conductor of the first group, the connections between the conductors being conductive via holes in the thickness of the insulating material. | 06-11-2009 |
| 20090146720 | PULSE GENERATOR - A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent. | 06-11-2009 |
| 20090141978 | IMAGE NOISE CORRECTION - An image noise correction method is provided. For at least one target pixel having a determined pixel value, for each pixel in a window of pixels surrounding the target pixel, a weighting factor for the pixel is estimated based on the value of the target pixel and at least one pixel value in the window. An average of pixel values for the pixels in the window is calculated, with each pixel value being weighted by the weighting factor corresponding to the pixel. A new value is assigned to the target pixel based on the average of pixel values that is calculated. Also provided is an image noise correction device. | 06-04-2009 |
| 20090141014 | CONTROLLING AN ENERGY RECOVERY STAGE OF A PLASMA SCREEN - A method and a circuit for controlling a power recovery stage of a plasma display panel including a resonant circuit of at least one inductive element and one capacitive element, wherein the capacitive element is precharged to half a supply voltage of the display panel. | 06-04-2009 |
| 20090140384 | PROCESS FOR OBTAINING A THIN, INSULATING, SOFT MAGNETIC FILM OF HIGH MAGNETIZATION, CORRESPONDING FILM AND CORRESPONDING INTEGRATED CIRCUIT - A thin soft magnetic film combines a high magnetization with an insulating character. The film is formed by nitriding Fe-rich ferromagnetic nanograins immersed in an amorphous substrate. A selective oxidation of the amorphous substrate is then performed. The result is a thin, insulating, soft magnetic film of high magnetization. Many types of integrated circuits can be made which include a component using a membrane incorporating the above-mentioned thin film. | 06-04-2009 |
| 20090140363 | Optical semiconductor device having photosensitive diodes and process for fabricating such a device - An optical semiconductor device includes, in a zone ( | 06-04-2009 |
