| STMicroelectronics (Rousset) SAS Patent applications |
| Patent application number | Title | Published |
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| 20120131533 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT PROTECTED AGAINST REVERSE ENGINEERING - The disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit comprising at least first and second standard cells implementing a same basic function; designing for the standard cell at least first and second cell layouts presenting random differences; designing an integrated circuit layout corresponding to the integrated circuit architecture; fabricating the integrated circuit according to the integrated circuit layout; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout. The method can be used for protection of an integrated circuit against reverse engineering. | 05-24-2012 |
| 20120124258 | CONVERSION OF A SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method of transmission-reception over a serial bus placed, when idle, in a first state at a first voltage, including: a transmit circuit capable of coding a transmission according to a first protocol in which the respective states of the bits are conditioned by time periods of fixed levels, indifferently in the first state or in a second state at a second voltage smaller than the first one; a receive circuit capable of interpreting a communication according to the first protocol; and a protocol converter, interposed between the bus and the transmit and receive circuits, to convert the signals to be transmitted to a second protocol in which the respective states of the bits are conditioned by respective time periods of fixed levels in the first state, and to convert the received signals from the second protocol to the first protocol. | 05-17-2012 |
| 20120119822 | Method for Modulating the Impedance of an Antenna Circuit - An electromagnetic transponder includes an antenna circuit capable of providing signals to a charge pump. The pump includes a first transistor connected to a first capacitor. The transponder also includes means for applying a voltage alternating between first and second values between the gate and the conduction terminal on the side of the first capacitor of the first transistor. | 05-17-2012 |
| 20120108169 | METHOD AND DEVICE FOR MANAGING INFORMATION EXCHANGE BETWEEN FOR EXAMPLE A NFC CONTROLLER AND A SET OF AT LEAST TWO SECURE ELEMENTS - The device may include a contactless element and a set of least two auxiliary elements. Each auxiliary element may include a slave SWP interface connected to a same master SWP interface of the contactless element through a SWP link, and a management module configured for activating at once only one slave SWP interface on the SWP link. | 05-03-2012 |
| 20120106732 | CRYPTOGRAPHIC COUNTERMEASURE METHOD BY DERIVING A SECRET DATA - A method of protecting a circuit from attacks aiming to discover secret data used during the execution of a cryptographic calculation by the circuit, by, executing a transformation calculation implementing a bijective transformation function, receiving as input a secret data, and supplying a transformed data, executing a cryptographic calculation receiving as input a data to process and the transformed data, and executing an inverse transformation calculation receiving as input the result of the cryptographic calculation, and supplying a result that the cryptographic calculation would have supplied if it had been applied to the data to process and directly to the secret data, the data to process belong to a stream of a multiplicity of data, the transformed data being supplied as input to the cryptographic calculation for all the data of the stream. | 05-03-2012 |
| 20120105012 | POWER RECOVERY BY AN ELECTROMAGNETIC TRANSPONDER - A method of power recovery by an electromagnetic transponder in the field of a terminal, wherein: a ratio of the current coupling factor of the transponder with the terminal to an optimum coupling position with a resistive load value is evaluated; and a detuning of the oscillating circuit is caused if the ratio is greater than a first threshold greater than or equal to one. | 05-03-2012 |
| 20120104632 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AN ANALOG BLOCK AND A DIGITAL BLOCK, AND CORRESPONDING INTEGRATED CIRCUIT - The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA | 05-03-2012 |
| 20120102248 | MASTER-SLAVE COMMUNICATION OVER A SINGLE-WIRE BUS BETWEEN A MASTER CIRCUIT AND AT LEAST TWO SLAVE CIRCUITS - A method of transmission over a serial bus, between a master circuit and two slave circuits, wherein each slave circuit makes the transmission of a first one of two binary states depend on the absence of a transmission of the second binary state by the other slave circuit. | 04-26-2012 |
| 20120097838 | IMAGING DEVICE IN PARTICULAR OF THE CMOS TIME DELAY AND INTEGRATION TYPE - An imaging device may be formed in a semiconductor substrate including a matrix array of photosites extending in a first direction and a second direction. The imaging device may include a transfer module configured to transfer charge in the first direction and an extraction module configured to extract charge in the second direction. | 04-26-2012 |
| 20120092901 | POWER MANAGEMENT IN AN ELECTROMAGNETIC TRANSPONDER - A method for managing the power in an electromagnetic transponder in the field of a terminal, including the steps of: evaluating the power consumption of the transponder circuits; and if this power consumption is below a threshold, evaluating the current coupling factor between the transponder and the terminal and, according to the current coupling: causing an increase of the transponder power consumption or causing a detuning of an oscillating circuit of the transponder. | 04-19-2012 |
| 20120091553 | Method for Detecting the Repackaging of an Integrated Circuit after it has been Originally Packaged, and Corresponding Integrated Circuit - An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged. | 04-19-2012 |
| 20120087228 | DATA MEDIUM OF THE COMPACT DISC TYPE, IN PARTICULAR FITTED WITH PROTECTION AGAINST COPYING, AND CORRESPONDING METHOD - A data medium of the compact disc type may include medium areas of different types configured to define digital content, and a controllable element having two different states corresponding respectively to the two different types of areas. The controllable element may be configured to take selectively one of its states in response to a command, so as to modify in a controllable manner the content of the data medium. | 04-12-2012 |
| 20120081092 | LOW ELECTROMAGNETIC EMISSION DRIVER - The disclosure concerns circuitry for controlling a power transistor of a drive circuit arranged to drive an electrical component, the circuitry comprising: a variable current source adapted to set the level of a current for charging a control terminal of said power transistor; and a control circuit adapted to control said variable current source in a continuous manner based on a feedback voltage. | 04-05-2012 |
| 20120080620 | METHOD AND DEVICE FOR DETECTING METALS IN A FLUID - A method detects metallic atoms in a fluid. The method includes: placing, in a zone sheltered from light, a photodiode comprising a photosensitive surface in contact with a fluid to analyze; heating the photosensitive surface of the photodiode to a temperature sufficient to allow metallic atoms deposited on the photosensitive surface to migrate through this surface; acquiring a signal relative to the lighting of the photodiode; and determining, from the acquired signal, a measurement representative of a contamination status by metallic atoms of the photodiode. | 04-05-2012 |
| 20120079151 | IDENTIFICATION, BY A MASTER CIRCUIT, OF TWO SLAVE CIRCUITS CONNECTED TO A SAME BUS - A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits. | 03-29-2012 |
| 20120068689 | EEPROM CELL WITH CHARGE LOSS - An EEPROM memory cell that includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer, wherein the insulation layer includes a first portion and a second portion having lower insulation properties than the first one, the second portion being located at least partially above a channel area of the transistor. | 03-22-2012 |
| 20120066571 | KEY EXTRACTION IN AN INTEGRATED CIRCUIT - A method of extraction of a key from a physical unclonable function exploiting the states of cells of a volatile memory after a powering on, wherein: cells are read according to addresses stored in a non-volatile memory; an error-correction code corrects the read states; and, in case an error has been corrected, the address of the cell providing an erroneous state is replaced in the non-volatile memory with that of another cell providing the non-erroneous state. | 03-15-2012 |
| 20120035883 | METHOD OF DETECTING AN OBJECT WITH A PROXIMITY SENSOR - The disclosure relates to a method of detecting an object using a detection signal supplied by a proximity sensor. The method comprises the steps of generating a reference signal by filtering the value of the detection signal, defining a first detection threshold, and going from an object non-detecting state to an object detecting state when the value of the detection signal becomes greater than the first detection threshold. When the value of the detection signal becomes greater than the first detection threshold, the value of the reference signal is readjusted in a manner such that the value of the detection signal again becomes less than or respectively greater than, the first detection threshold. | 02-09-2012 |
| 20120030753 | MULTIPROTOCOL COMMUNICATION AUTHENTICATION - A method for authenticating a transmission between a first and a second circuit transiting through at least one third circuit, wherein: data are transmitted from the first to the third circuit, and from the third to the second circuit; a first signature of the data is calculated by the first circuit; at least a second signature of the data is calculated by the third circuit; at least one first portion of the first signature is transmitted by the first circuit to the third one; and the second signature is transmitted by the third circuit to the second one, a portion of this signature being distorted in case of a failure of authentication of the first portion of the first signature by the third circuit. | 02-02-2012 |
| 20120030443 | PROTECTION OF SECRET KEYS - A method for protecting at least first data of a non-volatile memory from which the extraction of this first data is triggered by the reading or the writing, by a processor from or into the memory, of second data independent from the first data, said first data being provided to a circuit which the processor cannot access. | 02-02-2012 |
| 20120030388 | CONVERSION OF A TWO-WIRE BUS INTO A SINGLE-WIRE BUS - A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit. | 02-02-2012 |
| 20120027104 | SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration. | 02-02-2012 |
| 20120023580 | METHOD FOR DETECTING AN ATTACK BY FAULT INJECTION INTO A MEMORY DEVICE, AND CORRESPONDING DETECTION SYSTEM - The method for detecting an attack by fault injection into memory positions includes a generation of an initial value of a reference indication including an application of a reversible mathematical operator to the values of the information stored in the memory positions. An updating of the value of this reference indication is performed on each write in at least one memory position by using the operator, the reverse operator and the values of the stored information before and after each write in the at least one memory position. And, in the presence of a request, a check is performed as to whether a criterion involving the values of the information stored in the memory positions at the time of the request and the operator or its reverse is or is not satisfied by the value of the reference indication at the time of the request. | 01-26-2012 |
| 20120014024 | Method of Testing a Structure Protected from Overvoltages and the Corresponding Structure - An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the protection circuit in the presence of a test voltage across terminals of the component. | 01-19-2012 |
| 20120009774 | DEVICE FOR DETECTING AN ATTACK AGAINST AN INTEGRATED CIRCUIT - An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion. | 01-12-2012 |
| 20110309521 | CHIP STACK WITH CONDUCTIVE COLUMN THROUGH ELECTRICALLY INSULATED SEMICONDUCTOR REGION - A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas. | 12-22-2011 |
| 20110302539 | METHOD FOR DESIGNING MASKS USED TO FORM ELECTRONIC COMPONENTS - A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive. | 12-08-2011 |
| 20110300800 | EVALUATION OF THE COUPLING FACTOR OF AN ELECTROMAGNETIC TRANSPONDER BY CAPACITIVE DETUNING - A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, and a transponder implementing this method, wherein a ratio between data representative of a voltage across an oscillating circuit of the transponder and obtained for two capacitance values of the oscillating circuit is compared with one or several thresholds. | 12-08-2011 |
| 20110267094 | CIRCUIT AND METHOD FOR DETECTING A FAULT ATTACK - A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold. | 11-03-2011 |
| 20110265178 | Method and Device for Authenticating a User With the Aid of Biometric Data - Authentication system comprising an input device comprising a plurality of input elements configured for inputting respectively characters in response to an input of a sequence of at least one character carried out by a user, the input device comprising at least one determination means coupled to at least one input element in order to determine a force exerted on the said at least one input element, the system comprising a recording means for recording a series of at least one force exerted on the said at least one input element, a memory configured for storing a series of at least one reference force, and comparison means configured for comparing the series of at least one exerted force with the series of at least one reference force. | 10-27-2011 |
| 20110255560 | TRANSMISSION OVER AN 12C BUS - A method and a system of multichannel transmission over a twin-wire bus including a data signal and a synchronization signal, data of a first channel being transmitted by a state coding of the data signal for a time period containing a first state of the synchronization signal, data of a second channel being transmitted by pulse coding outside of said period. | 10-20-2011 |
| 20110255064 | PHOTOLITHOGRAPHY METHOD AND DEVICE - A photolithography method includes projecting a light beam through a mask onto a photosensitive layer to form on the photosensitive layer an image of a mask pattern formed by the mask, and controlling a layer of active elements of the mask so that the light beam after having traversed the layer of active elements, reproduces the mask pattern onto the photosensitive layer. The active elements are distributed throughout the layer of active elements in conformance with a matrical organization of lines and columns, each active element being individually controllable to take a state transparent to the light of the light beam, or else a state opaque to or reflecting of the light of the light beam, as a function of a command signal supplied to the active element. | 10-20-2011 |
| 20110253174 | METHOD FOR DECONTAMINATING SEMICONDUCTOR WAFERS - A method for decontaminating at least one object contained in a chamber, the method including a succession of alternated steps of lowering and increasing the pressure in the chamber. | 10-20-2011 |
| 20110248720 | TESTING SYSTEM FOR INTEGRATED CIRCUITS - A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit. | 10-13-2011 |
| 20110234307 | COUNTERMEASURE METHOD AND DEVICE AGAINST AN ATTACK BY FAULT INJECTION IN AN ELECTRONIC MICROCIRCUIT - The disclosure relates to a method for detecting an attack in an electronic microcircuit, comprising: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage. | 09-29-2011 |
| 20110225432 | METHOD AND CIRCUITRY FOR DETECTING A FAULT ATTACK - A method of detecting a fault attack during a cryptographic operation using at least one look-up table including a plurality of sub-tables each having a same number of values of a fixed bit length, a fixed relation existing between values at same locations in each sub-table, the method including: performing a load operation to retrieve from the look-up table data values from a same location in each sub-table; verifying that the fixed relation exists between at least two of the data values; and generating an output signal based on the verification. | 09-15-2011 |
| 20110222684 | PROTECTION OF REGISTERS AGAINST UNILATERAL DISTURBANCES - A method for protecting a key intended to be used by an electronic circuit in an encryption or decryption algorithm, including the steps of: submitting the key to a first function taking a selection value into account; storing all or part of the result of this function in at least two registers; when the key is called by the algorithm, reading the contents of said registers and submitting them to a second function taking into account all or part of the bits of the registers; and providing the result of the combination as an input for the algorithm, the second function being such that the provided result corresponds to the key. | 09-15-2011 |
| 20110215862 | INTERNAL SUPPLY VOLTAGE CIRCUIT OF AN INTEGRATED CIRCUIT - The disclosure relates to a method for generating a setpoint voltage in an integrated circuit, comprising generating a substantially constant reference voltage, and generating from the reference voltage, a setpoint voltage comprising a component equal to the highest threshold voltage of all the CMOS transistors of a circuit of the integrated circuit and a component which may be equal to zero. The disclosure applies in particular to the provision of a power supply voltage of a circuit based on CMOS transistors. | 09-08-2011 |
| 20110202948 | METHOD FOR DETECTING POTENTIALLY SUSPICIOUS OPERATION OF AN ELECTRONIC DEVICE AND CORRESPONDING ELECTRONIC DEVICE - A method may be for detecting potentially suspicious operation of an electronic device configured to operate in the course of activity sessions. The method may include within the device, a metering, from an initial instant of the number of activity sessions having a duration below a first threshold, and a comparison of this number with a second threshold. | 08-18-2011 |
| 20110194219 | INTEGRATED CIRCUIT PROVIDED WITH A PROTECTION AGAINST ELECTROSATATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, having output pads coupled to amplification stages, each stage including, between first and second power supply rails, a P-channel MOS power transistor in series with an N-channel MOS power transistor, this integrated circuit further including protection circuitry for simultaneously turning on the two transistors when a positive overvoltage occurs between the first and second power supply rails. | 08-11-2011 |
| 20110181991 | STRUCTURE OF PROTECTION OF AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGES - An integrated circuit protected against electrostatic discharges, including input/output pads and first and second power supply rails, and: a thyristor forward-connected between each input/output pad and the second rail, each thyristor including, between its anode gate and its anode, a resistor; between each thyristor and the first rail, a diode having its anode connected to the anode gate of the thyristor and having its cathode connected to the first rail via a resistor for adjusting the triggering; and a triggering device capable of conducting a current between the first and second rails when a positive overvoltage occurs between these rails. | 07-28-2011 |
| 20110176674 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - The present disclosure relates to a countermeasure method in an integrated circuit comprising at least one first logic circuit and at least one first input register supplying the first logic circuit with a datum, the method comprising steps of introducing a random datum into each first input register of the first logic circuit and of the first logic circuit reading the random datum in each first input register, then of introducing a datum to be processed into each first input register, and of the first logic circuit processing the datum in each first input register. | 07-21-2011 |
| 20110170691 | PROTECTION OF A CIPHERING KEY AGAINST UNIDIRECTIONAL ATTACKS - A method for protecting a key implemented, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of: selecting in non-deterministic fashion a pair of different masks from a set of at least four different masks, the masks having the property of representing different bit combinations, at least by pairs of bits; executing the algorithm twice by applying, to the key or to the message, one of the masks of the selected pair at each execution; checking the consistency between the two executions. | 07-14-2011 |
| 20110156756 | COUNTERMEASURE METHOD AND DEVICE FOR PROTECTING DATA CIRCULATING IN AN ELECTRONIC COMPONENT - A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. | 06-30-2011 |
| 20110150065 | MULTIPLE-CHANNEL TRANSMISSION OVER A SINGLE-WIRE BUS - A method for transmitting at least a synchronization and a data signal on a single-wire bus between a master device and at least one slave device, wherein a first transmission channel from the master device to the slave device modulates the periodic pulse width between a first level and second level of a same sign voltage relative to a reference potential, and a second transmission channel amplitude modulates at least one of the voltage levels between the level and at least one third level different from the two others and from the reference potential. | 06-23-2011 |
| 20110140852 | POWER MANAGEMENT IN AN ELECTROMAGNETIC TRANSPONDER - A method of evaluation, by an electromagnetic transponder in the field of a terminal generating a magnetic field, of power that can be extracted from this field, including the steps of: evaluating the current coupling between the transponder and the terminal; and deducing therefrom information relative to the power available in this coupling position. | 06-16-2011 |
| 20110128070 | CHARGE PUMP STAGE, METHOD FOR CONTROLLING A CHARGE PUMP STAGE AND MEMORY HAVING A CHARGE PUMP STAGE - A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block. | 06-02-2011 |
| 20110128030 | MONITORING OF THE ACTIVITY OF AN ELECTRONIC CIRCUIT - A method and a device for monitoring a digital signal, wherein a first P-channel MOS transistor is placed in degradation conditions of negative bias temperature instability type during periods when the signal to be monitored is in a first state; a first quantity representative of the saturation current of the first transistor is measured when the signal to be monitored switches to a second state; and a detection signal is switched when this first quantity exceeds a threshold. | 06-02-2011 |
| 20110126085 | METHOD OF SIGNATURE VERIFICATION - A method of detecting a fault including generating at least one blinded data value based on at least one input value and at least one blinding parameter selected from a plurality of blinding parameters generating a first signature based on said at least one blinded data value; selecting, from a memory storing a plurality of reference signatures, one or more reference signatures and comparing said first signature with said one or more reference signatures in order to detect a fault. | 05-26-2011 |
| 20110119762 | METHOD AND APPARATUS FOR DETECTION OF A FAULT ATTACK - The invention concerns a method of detecting a fault attack including providing a plurality of blinding values; generating a first set of data elements including a first group of data elements and at least one additional data element generated by performing the exclusive OR between at least one data element in the first group and at least one of the blinding values; generating a second set of data elements corresponding to the exclusive OR between each data element of the first set and a selected one of the plurality of blinding values; generating a first signature by performing a commutative operation between each of the data elements of the first set; generating a second signature by performing the commutative operation between each of the data elements of the second set; and comparing the first and second signatures to detect a fault attack. | 05-19-2011 |
| 20110119532 | METHOD OF DETECTING A FAULT ATTACK - A method of detecting a fault attack including generating a first signature of a first group of data values by performing a single commutative non-Boolean arithmetic operation between all the data values of the first group; generating a second set of data values by performing a permutation of the first set of data values; generating a second signature of the second group of data values by performing said single commutative non-Boolean arithmetic operation between all the data values of the second group; and comparing the first and second signatures to detect a fault attack. | 05-19-2011 |
| 20110113256 | Secure Method for Processing a Content Stored Within a Component, and Corresponding Component - The component comprises a first memory (MM) comprising a first portion (P | 05-12-2011 |
| 20110108902 | MEMORY WITH A READ-ONLY EEPROM-TYPE STRUCTURE - A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell. | 05-12-2011 |
| 20110103584 | PROTECTION OF A CIPHERING KEY - A method for protecting a key used, by an electronic circuit, in a symmetrical algorithm for ciphering or deciphering a message, including the steps of complementing to one the key and the message; executing the algorithm twice, respectively with the key and the message and with the key and the message complemented to one, the selection between that of the executions which processes the key and the message and that which processes the key and the message complemented to one being random; and checking the consistency between the two executions. | 05-05-2011 |
| 20110103146 | MEMORY DEVICE OF THE ELECTRICALLY ERASABLE AND PROGRAMMABLE TYPE, HAVING TWO CELLS PER BIT - The memory device includes a memory cell unit of the electrically erasable and programmable non-volatile type including two memory cells respectively connected to two bit lines via two bit line select transistors. The common terminal between the bit line select transistor and the floating-gate transistor of each memory cell of the memory cell unit is connected to the control gate of the floating-gate transistor of the other memory cell of the memory cell unit. | 05-05-2011 |
| 20110092000 | METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT - A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections. | 04-21-2011 |
| 20110091034 | Secure Method for Cryptographic Computation and Corresponding Electronic Component - The secure method for cryptographic computation comprises processing of an input datum (D) by a cryptographic computation tool involving at least one encryption key (K) and at least one generated item of secret information, so as to provide an output datum (DC). The generation of the said at least one item of secret information (ST) comprises processing of the said input datum by at least one operator (OPS) having at least one secret characteristic. | 04-21-2011 |
| 20110090748 | DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT - The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor. | 04-21-2011 |
| 20110090747 | INTEGRATED CIRCUIT COMPRISING A NON-DEDICATED TERMINAL FOR RECEIVING AN ERASE PROGRAM HIGH VOLTAGE - The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals. | 04-21-2011 |
| 20110090745 | SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS - The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories. | 04-21-2011 |
| 20110087856 | Memory Device with Serial Protocol and Corresponding Method of Addressing - The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP | 04-14-2011 |
| 20110080933 | DEVICE FOR DETECTING TEMPERATURE VARIATIONS IN A CHIP - A device for detecting temperature variations of the substrate of an integrated circuit chip, including, in the substrate, implanted resistors connected as a Wheatstone bridge, wherein each of two first opposite resistors of the bridge is covered with an array of metal lines parallel to a first direction, the first direction being such that a variation in the substrate stress along this direction causes a variation of the unbalance value of the bridge. | 04-07-2011 |
| 20110080190 | METHOD FOR PROTECTING AN INTEGRATED CIRCUIT CHIP AGAINST LASER ATTACKS - A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 μm from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate. | 04-07-2011 |
| 20110079881 | INTEGRATED CIRCUIT CHIP PROTECTED AGAINST LASER ATTACKS - An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 μm from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 10 | 04-07-2011 |
| 20110072300 | TEARING-PROOF METHOD FOR WRITING DATA IN A NONVOLATILE MEMORY - A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone. | 03-24-2011 |
| 20110072221 | METHOD FOR WRITING AND READING DATA IN A NONVOLATILE MEMORY, BY MEANS OF METADATA - A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A | 03-24-2011 |
| 20110072202 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 03-24-2011 |
| 20110072028 | METHOD FOR READING A NONVOLATILE MEMORY BY MEANS OF METADATA AND OF A LOOK-UP TABLE - An example method for writing and reading data in electrically erasable and programmable nonvolatile memory (EEPROM) cells may include writing, in erased blocks of a first memory zone, data each having a logical address defined in relation to a virtual memory; writing, in a second memory zone, metadata structures associated with the data present in the first memory zone, configuring, in a volatile memory zone, for each logical address of a data stored in the first memory zone, addresses of metadata structures comprising the logical address, reading the look-up table and then reading metadata structures that the look-up table designates, to find, from the logical address of a data, an address in the first memory zone of a block containing a valid data having the logical address. | 03-24-2011 |
| 20110057333 | METHOD FOR THE REAL-TIME MONITORING OF INTEGRATED CIRCUIT MANUFACTURE THROUGH LOCALIZED MONITORING STRUCTURES IN OPC MODEL SPACE - The present disclosure relates to a method of controlling the manufacturing of integrated circuits, comprising steps of determining parameters that are characteristic of a curve of radiation intensity applied to a semiconductor wafer through a mask, in critical zones of structures to be formed on the wafer, for each of the critical zones, placing a measuring point in a multidimensional space each dimension of which corresponds to one of the characteristic parameters, placing control points in the multidimensional space that are spread around an area delimited by the measuring points, so as to delimit an envelope surrounding the area, for each control point, defining control structures each corresponding to a control point, generating a mask containing the control structures, applying a process involving the generated mask to a semiconductor wafer, and analyzing the control structures transferred to the wafer to detect any defects therein. | 03-10-2011 |
| 20110045625 | METHOD OF MANUFACTURING A SEMICONDUCTOR WAFER COMPRISING AN INTEGRATED OPTICAL FILTER - A method manufactures semiconductor chips each comprising a component implanted in the semiconductor. The method includes collectively implanting components onto a front face of a semiconductor wafer and fixing a plate of a transparent material onto the front face of the wafer. Fixing the plate of transparent material is preceded by a step of depositing, on the front face of the wafer, at least one layer of polymer material forming an optical filter. Application is particularly to the manufacturing of imagers. | 02-24-2011 |
| 20110033045 | COUNTERMEASURE METHOD FOR PROTECTING STORED DATA - A method of read or write access by an electronic component of data, including generating a first secret key for a first data of an ordered list of data to access, and for each data of the list, following the first data, generating a distinct secret key by means of a deterministic function applied to a secret key generated for a previous data of the list, and the application of a cryptographic operation to each data to be read or to be written of the list, carried out by using the secret key generated for the data. | 02-10-2011 |
| 20110029828 | FAULT INJECTION DETECTOR IN AN INTEGRATED CIRCUIT - A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a functional phase and a detection phase of the logic block, the isolation block applying, during the functional phase, the signal to be processed to at least one input of the logic block, and during the detection phase, a constant value to the input of the logic block; and a detection block adapted to monitor, during the detection phase, the state of the output signal of the logic block, and to generate an alert signal in case of any change in the state of the output signal. | 02-03-2011 |
| 20110026346 | SELF-TIMED LOW POWER SENSE AMPLIFIER - A sense amplifier is disclosed comprising a first sense input, a second sense input, a latch, a first p-channel control transistor arranged to electrically power a first section of the latch and having a gate terminal linked to the first sense input, and a second p-channel control transistor arranged to electrically power a second section of the latch and having a gate terminal linked to the second sense input. Application may be in particular to low power embedded memories. | 02-03-2011 |
| 20110001558 | INTEGRATED CIRCUIT COMPRISING A BROADBAND HIGH VOLTAGE BUFFER - The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port. | 01-06-2011 |
| 20100331045 | EEPROM MEMORY ARCHITECTURE OPTIMIZED FOR EMBEDDED MEMORIES - The present disclosure relates to an electrically erasable and programmable memory comprising rows of memory cells to store words of N bits each, bit lines and word lines, wherein a row of memory cells comprises a first group of memory cells to store collectively erasable words, and at least one second group of memory cells to store one individually erasable word. | 12-30-2010 |
| 20100328046 | AUTHENTICATION OF A TERMINAL BY AN ELECTROMAGNETIC TRANSPONDER - A method of authentication of a terminal generating a magnetic field by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein at least one quantity depending on the coupling between the transponder and the terminal is compared with at least one reference value. | 12-30-2010 |
| 20100328027 | AUTHENTICATION OF AN ELECTROMAGNETIC TERMINAL-TRANSPONDER COUPLE BY THE TERMINAL - A method of authentication, by a terminal generating a magnetic field, of a transponder located in this field, wherein: first data, relative to the current in an oscillating circuit of the terminal, measured by the terminal for a first value of the resistive load of the transponder, are transmitted to the transponder; second corresponding data are evaluated by the transponder for a second value of the resistive load and are transmitted to the terminal; and said second data are compared with third corresponding data, measured by the terminal for the second value of the resistive load. | 12-30-2010 |
| 20100328026 | AUTHENTICATION OF AN ELECTROMAGNETIC TERMINAL-TRANSPONDER COUPLE BY THE TRANSPONDER - A method of authentication of a terminal generating a magnetic field, by a transponder including an oscillating circuit from which a D.C. voltage is generated, wherein the transponder: receives first data relative to the current in an oscillating circuit of the terminal, measured by the terminal for a first value of the resistive load of the transponder; and exploits these first data and second data relative to the level of said D.C. voltage, respectively measured for the first resistive load value and for a second resistive load value. | 12-30-2010 |
| 20100323629 | RESISTIVE EVALUATION OF THE COUPLING FACTOR OF AN ELECTROMAGNETIC TRANSPONDER - A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, wherein a ratio between data, representative of a voltage across an oscillating circuit of the transponder and obtained for two values of the resistive load, is compared with one or several thresholds. | 12-23-2010 |
| 20100321164 | INDUCTIVE EVALUATION OF THE COUPLING FACTOR OF AN ELECTROMAGNETIC TRANSPONDER - A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, wherein a ratio between data representative of a voltage across an oscillating circuit of the transponder and obtained for two pairs of inductive and capacitive values of this oscillating circuit is compared with one or several thresholds, the two pairs of values preserving a tuning of the oscillating circuit to a same frequency. | 12-23-2010 |
| 20100321049 | INTEGRATED CIRCUIT CHIP IDENTIFICATION ELEMENT - A element for identifying an integrated circuit chip having identical diffused resistors connected as a Wheatstone bridge. | 12-23-2010 |
| 20100318885 | METHOD OF DETECTING AN ATTACK BY FAULT INJECTION ON A MEMORY DEVICE, AND CORRESPONDING MEMORY DEVICE - A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit. | 12-16-2010 |
| 20100315108 | DEVICE FOR DETECTING THE THINNING DOWN OF THE SUBSTRATE OF AN INTEGRATED CIRCUIT CHIP - A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge. | 12-16-2010 |
| 20100308898 | METHOD OF GENERATING ELECTRICAL ENERGY IN AN INTEGRATED CIRCUIT DURING THE OPERATION OF THE LATTER, CORRESPONDING INTEGRATED CIRCUIT AND METHOD OF FABRICATION - An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material. | 12-09-2010 |
| 20100308602 | METHOD OF GENERATING ELECTRICAL ENERGY IN AN INTEGRATED CIRCUIT, CORRESPONDING INTEGRATED CIRCUIT AND METHOD OF FABRICATION - A method of generating electrical energy in an integrated circuit that may include setting into motion a (3D) three-dimensional enclosed space in the integrated circuit. The 3D enclosed space may include a piezoelectric element and a free moving object therein. The method may also include producing the electrical energy from impact between the free moving object and the piezoelectric element during the motion. | 12-09-2010 |
| 20100306295 | PROTECTION OF A PRIME NUMBER GENERATION FOR AN RSA ALGORITHM - A method for protecting a generation, by an electronic circuit, of at least one prime number by testing the prime character of successive candidate numbers, including: for each candidate number: the calculation of a reference number involving at least one first random number, and at least one primality test based on modular exponentiation calculations; and for a candidate number having successfully passed the primality test: a test of consistency between the candidate number and its reference number. | 12-02-2010 |
| 20100245148 | ANALOG-DIGITAL CONVERTER AND CORRESPONDING SYSTEM AND METHOD - An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers. | 09-30-2010 |
| 20100210300 | COMMUNICATION DEVICE COMPRISING A BATTERY AND A NEAR-FIELD COMMUNICATION MODULE - A mobile telecommunication device including at least one telecommunication circuit; at least one subscriber identification module; at least one assembly including at least one supply battery; and a switch of selection between a power supply of the subscriber identification module by the assembly and by the telecommunication circuit according to the presence or not of a near-field communication module in the assembly. | 08-19-2010 |
| 20100194645 | TEAR-PROOF CIRCUIT - A circuit including a flexible substrate and at least one electric element attached to the substrate, the substrate including at least one cavity arranged near the electric element and helping to break or distort the electric element in response to a flexion or stretching of the substrate. Application in particular is to the manufacture of tear-proof electronic micromodules. | 08-05-2010 |
| 20100161854 | METHOD FOR ENABLING SEVERAL VIRTUAL PROCESSING UNITS TO DIRECTLY AND CONCURRENTLY ACCESS A PERIPHERAL UNIT - The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set. | 06-24-2010 |
| 20100158072 | DEVICE FOR MONITORING THE TEMPERATURE OF AN ELEMENT - A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold. | 06-24-2010 |
| 20100153732 | CACHE-BASED METHOD OF HASH-TREE MANAGEMENT FOR PROTECTING DATA INTEGRITY - The present disclosure relates to accessing data stored in a secure manner in an unsecure memory, based on signatures forming an integrity check tree comprising a root signature stored in a secure storage space, and lower-level signatures stored in the unsecure memory. One embodiment calculates a first-level signature from the data in a group comprising a changed datum, and temporarily stores the signature calculated in a secure memory. The embodiment calculates a signature to check the integrity of a lower-level signature by using the signature to be checked and a second signature belonging to a same group as the signature to be checked, read as a priority in the secure memory and in the unsecure memory if it has different values in the secure and unsecure memories. | 06-17-2010 |
| 20100151595 | MAGNETIC RAM - A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions. | 06-17-2010 |
| 20100133645 | METHOD FOR STACKING AND INTERCONNECTING INTEGRATED CIRCUITS - A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas. | 06-03-2010 |
| 20100124100 | DEVICE FOR CONTROLLING THE ACTIVITY OF MODULES OF AN ARRAY OF MEMORY MODULES - A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function. | 05-20-2010 |
| 20100110791 | EEPROM MEMORY PROTECTED AGAINST THE EFFECTS OF BREAKDOWN OF MOS TRANSISTORS - The disclosure relates to an electrically erasable and programmable memory, comprising memory cells arranged in bit lines and word lines transverse to bit lines, wherein each memory cell may be in a programmed or erased state, the memory comprising memory cell selection circuits configured to memorize and read data bits in two memory cells belonging to different bit lines and different word lines, and to avoid a memory cell from being written or read by mistake in another state than a default state after a gate oxide breakdown of a transistor of the memory, and a read circuit to determine a data bit to be read in the memory according to the states of the two memory cells memorizing the data bit. | 05-06-2010 |
| 20100070779 | INTEGRITY OF CIPHERED DATA - A method for protecting the integrity of data ciphered by a ciphering algorithm providing at least an intermediary state meant to be identical in ciphering and in deciphering, this intermediary state being sampled during the ciphering to generate a signature. | 03-18-2010 |
| 20100059766 | STORAGE OF AN IMAGE IN AN INTEGRATED CIRCUIT - An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion. | 03-11-2010 |
| 20100054460 | PROTECTION OF A CIPHERING ALGORITHM - A method for protecting the execution of a ciphering or deciphering algorithm against the introduction of a disturbance in a step implementing one or several first values obtained from second values supposed to be invariant and stored in a non-volatile memory in which, during an execution of the algorithm: a current signature of the first values is calculated; this current signature is combined with a reference signature previously stored in a non-volatile memory; and the result of this combination is taken into account at least in the step of the algorithm implementing said first values. | 03-04-2010 |
| 20100052128 | DEVICE FOR DETECTING AN ATTACK AGAINST AN INTEGRATED CIRCUIT - An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion. | 03-04-2010 |
| 20100049892 | METHOD OF ROUTING AN INTERRUPT SIGNAL DIRECTLY TO A VIRTUAL PROCESSING UNIT IN A SYSTEM WITH ONE OR MORE PHYSICAL PROCESSING UNITS - The present disclosure relates to a method of processing an interrupt comprising a peripheral unit sending an interrupt, the interrupt being intended for a virtual unit executed by a processing unit, transmitting the interrupt to an interrupt control unit coupled to a processing unit, and the interrupt control unit storing the interrupt in an interrupt register. According to an embodiment of the present disclosure, the interrupt is transmitted to the interrupt control unit in association with an identifier of the virtual unit receiving the interrupt, the interrupt register in which the interrupt belonging to a set of registers is stored comprising one interrupt register per virtual unit likely to be executed by the processing unit, the interrupt being transmitted to the processing unit if the virtual unit receiving the interrupt is being executed by the processing unit. | 02-25-2010 |
| 20100044874 | INTEGRATED CIRCUIT OF DECREASED SIZE - An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface. | 02-25-2010 |
| 20100040045 | DATA PROCESSING SYSTEM HAVING DISTRIBUTED PROCESSING MEANS FOR USING INTRINSIC LATENCIES OF THE SYSTEM - The present disclosure relates to a method for routing data between a sending unit and a receiving unit linked by a network in a processing system comprising several units, the method comprising steps of routing data in the network between the sending unit and the receiving unit, and of applying a process to the routed data, the process comprising several steps which are applied to the data by different units in the network receiving the data, to use latency times in data routing. | 02-18-2010 |
| 20100034000 | ELECTRONIC CIRCUIT HAVING A DIODE-CONNECTED MOS TRANSISTOR WITH AN IMPROVED EFFICIENCY - An integrated circuit including a semiconductor layer; and a MOS transistor including first and second power terminals and a bulk insulated from the semiconductor layer, the first power terminal being intended to receive an oscillating signal, the transistor gate and the bulk being connected to the first power terminal. | 02-11-2010 |
| 20100026358 | PROTECTION AGAINST FAULT INJECTIONS OF AN ELECTRONIC CIRCUIT WITH FLIP-FLOPS - A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance. | 02-04-2010 |
| 20100019885 | DETECTION OF THE PRESENCE OF A CONTACTLESS COMMUNICATION ELEMENT WITHIN THE RANGE OF A TERMINAL - A method of detection of the presence of a contactless communication element by a terminal emitting an electromagnetic field, in which an oscillating circuit of the terminal is excited at a frequency which is made variable between two values surrounding a nominal tuning frequency of the oscillating circuit; a signal representative of the load of the oscillating circuit being interpreted to detect that a reference voltage has not been exceeded, which indicates the presence of an element in the field. A presence-detection circuit and a corresponding terminal. | 01-28-2010 |
| 20100017553 | INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS - A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period. | 01-21-2010 |
| 20090315603 | DETECTION OF A DISTURBANCE IN THE STATE OF AN ELECTRONIC CIRCUIT FLIP-FLOP - A method and a circuit for detecting a disturbance of a state of at least one first flip-flop from a group of several first flip-flops of an electronic circuit, wherein: the respective outputs of the first flip-flops in the group are, independently from their functional purpose, combined to provide a signal and its inverse, triggering two second flip-flops having data inputs forced to a same state, the respective outputs of the second flip-flops being combined to provide the result of the detection; and a pulse signal comprising a pulse at least for each triggering edge of one of the first flip-flops in the group initializes the second flip-flops. | 12-24-2009 |
| 20090285398 | VERIFICATION OF THE INTEGRITY OF A CIPHERING KEY - A method for verifying the integrity of a key implemented in a symmetrical ciphering or deciphering algorithm, including the steps of complementing to one at least the key; and verifying the coherence between two executions of the algorithm, respectively with the key and with the key complemented to one. | 11-19-2009 |
| 20090273452 | RECHARGE OF AN ACTIVE TRANSPONDER - A method for configuring a terminal capable of emitting a radio-frequency field for a transponder including, in the presence of a transponder within the range of the terminal, at least one step of adaptation of the series resistance of an oscillating circuit of the terminal, according to an off-load value, which depends on an operation of the terminal while no transponder is in its field. | 11-05-2009 |
| 20090267172 | METHOD OF MANUFACTURING AN IMAGE SENSING MICROMODULE - A method of manufacturing a micromodule including the steps of: producing an integrated circuit on an active face of a chip made of a semi-conductive material, making a via passing through the chip, electrically linked to the integrated circuit, and inserting the chip into a box comprising a cavity and an electrically conductive element, the active face of the chip being disposed towards the bottom of the cavity, forming on at least one part of a lateral face of the chip a conductive lateral layer made of an electrically conductive material, electrically linked to a conductive element of the rear face of the chip, and producing a connection between the conductive lateral layer and the conductive element by depositing an electrically conductive material in the cavity. | 10-29-2009 |
| 20090252068 | DETECTION OF DATA RECEIVED BY A MASTER DEVICE IN A SINGLE-WIRE COMMUNICATION PROTOCOL - A method of determining, by a first device capable of transmitting a two-state signal over a single-wire connection to a second device, the binary state of data transmitted by the second device over said connection, the state being determined according to the slope of a rising edge of the two-state signal. | 10-08-2009 |
| 20090251544 | VIDEO SURVEILLANCE METHOD AND SYSTEM - The present disclosure relates to a video surveillance method comprising steps of a video camera periodically capturing an image of a zone to be monitored, analyzing the image to detect a presence therein, and of the video camera transmitting the image only if a presence has been detected in the image. | 10-08-2009 |
| 20090251168 | DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST A LASER ATTACK - An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device. | 10-08-2009 |
| 20090247079 | TERMINAL OF RADIO-FREQUENCY TRANSMISSION/RECEPTION BY INDUCTIVE COUPLING - A method and a device of transmission/reception by inductive coupling including circuitry for generating an AQ.C. signal intended to drive an oscillating circuit and circuitry intended to modulate the impedance of the oscillating circuit when data is to be transmitted, the oscillating circuit including an inductive element forming an antenna in parallel with a first capacitive element; and at least one second capacitive element in series with a switch, all in parallel with the first capacitive element and the antenna, the modulating circuitry being connected between the terminals of the antenna and the circuitry for generating the AQ.C. signal being connected to the junction point of the second capacitive element and of the switch. | 10-01-2009 |
| 20090186460 | METHOD FOR MANUFACTURING AN EEPROM CELL - A method for manufacturing an EEPROM cell including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with a stack of first and second layers, forming at least one first opening in the second layer, forming, in the first layer, a second opening continuing the first opening, enlarging the first opening by isotropic etching, forming a first doped region in the substrate by implantation through the first enlarged opening, the first doped region taking part in the forming of the transistor drain or source, forming, in the third opening, a thinned-down insulating portion thinner than the first layer, and forming the gates of the MOS transistor at least partially extending over the thinned-down insulating portion. | 07-23-2009 |
| 20090146214 | METHOD FOR MANUFACTURING AN EEPROM CELL - A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a second surface opposite to the first surface; and incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface. | 06-11-2009 |
| 20090096520 | DETECTOR OF A RADIO-FREQUENCY SIGNAL - A method and a circuit for detecting a radio-frequency signal, including at least one first MOS transistor with a channel of a first type, having its gate coupled to an input terminal capable of receiving said signal; a circuit for biasing the first transistor, capable of biasing it to a level lower than its threshold voltage; and a circuit for determining the average value of the current in the first transistor. | 04-16-2009 |
| 20090022211 | METHOD AND DEVICE FOR CORRELATING A SIGNAL, IN PARTICULAR AN ULTRA WIDEBAND SIGNAL - The waveform of the signal varies according to the distance at which the signal was emitted, and several correlation signals are defined and correspond respectively to at least part of several sampled waveforms of the signal respectively emitted at several distances of different values so that the sum of the maxima of intercorrelations performed respectively between the various correlation signals and the various sampled waveforms is substantially constant over an interval including all the values of the distances. The correlation processing includes several elementary correlation processings respectively performed with the correlation signals and each delivering initial correlation values, as well as a summation of the homologous initial correlation values respectively delivered by the elementary correlation processings so as to obtain the correlation values. | 01-22-2009 |
| 20090010321 | METHOD AND DEVICE FOR PROCESSING A PULSE TRAIN OF A MODULATED SIGNAL, IN PARTICULAR AN ULTRA WIDEBAND SIGNAL MODULATED BY A DIGITAL PULSE INTERVAL MODULATION - The pulse train of a signal is modulated by a DPIM modulation involving a discrete random time parameter. A first processing is performed on the signal to deliver a sampled signal. A second processing is performed on the sampled signal, comprising a correlation processing including at least one elementary correlation processing with a correlation mask corresponding to the shape of at least part of a sampled pulse, and delivering second information items. A third processing is performed for detecting the pulses following a first pulse by taking account of the position of the first pulse, on packets of second information items, which are separated by a duration related to the discrete random parameter. | 01-08-2009 |
| 20080290383 | CMOS IMAGING DEVICE COMPRISING A MICROLENS ARRAY EXHIBITING A HIGH FILLING RATE - A CMOS imager includes a photosite array and a microlens array. The microlens array comprises microlenses of a first type and microlenses of a second type, the microlenses of first type being manufactured according to a first circular template having a first radius, the microlenses of second type being manufactured according to a second circular template having a second radius inferior to the first radius, and the first and second templates having overlap areas. One advantage is that the CMOS imager has a high fill rate. | 11-27-2008 |
| 20080273763 | Method and device for locating a human iris in an eye image - The present disclosure relates to a method for locating the iris in an image of an eye, comprising steps of locating the pupil in the image, of detecting positions of intensity steps of pixels located on a line passing through the pupil and transition zones between the iris and the cornea, on either side of the pupil, and of determining the center and the radius of a circle passing through the detected positions of the transitions. | 11-06-2008 |
| 20080239786 | LOGIC CODING IN AN INTEGRATED CIRCUIT - The programming of a read-only memory formed of MOS transistors, the programming being set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. An interconnection structure and a read-only memory. | 10-02-2008 |
