STMICROELECTRONICS (GRENOBLE 2) SAS Patent applications |
Patent application number | Title | Published |
20160112700 | CIRCUIT AND METHOD FOR ON-CHIP TESTING OF A PIXEL ARRAY - Testing of control wires of a pixel array of an image sensor is performed by applying a signal transition to a control wire and detecting, based on a voltage signal detected on the control wire, the duration of at least part of the signal transition on the control wire. An electrical fault in the control wire is indicated based on a comparison of the detected duration to a threshold. | 04-21-2016 |
20160049341 | INTEGRATED CIRCUIT CHIP WITH CORRECTED TEMPERATURE DRIFT - An integrated circuit chip includes trenches at least partially surrounding a critical portion of a circuit that is sensitive to temperature variations. The trenches are locally interrupted in order to permit circuit connections to pass between the critical portion and an outer portion containing a remainder of the circuit. The critical portion includes heating resistors and a temperature sensor. | 02-18-2016 |
20150364455 | STACK OF INTEGRATED-CIRCUIT CHIPS AND ELECTRONIC DEVICE - A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer. | 12-17-2015 |
20150357484 | ELECTRONIC DEVICE COMPRISING AN OPTICAL SENSOR CHIP - An electronic device includes a substrate plate with a traversing passage. An electronic component, mounted to the substrate plate, includes an integrated circuit chip with an optical sensor and an opaque protective plate mounted above the sensor. The electronic component is mounted with the chip facing the substrate plate such that the protective plate is engaged with the traversing passage. Electrical connection elements extend between the chip and the substrate plate. An internal block of encapsulation material extends into the traversing passage of the substrate plate between the chip and the substrate plate so as to embed the electrical connection elements. | 12-10-2015 |
20150349010 | IMAGE SENSOR - An image sensor is formed by a pixel array including a plurality of pixels. Certain ones of the pixels include, above their active areas, a first optical grating formed of periodically spaced apart parallel strips separated from the active area by a first insulator. Those pixels further include, in another metal level, a second optical grating formed of periodically spaced apart parallel strips separated from the first grating by a second insulator. The second optical grating is laterally shifted with respect to the first grating in a direction orthogonal to a longitudinal direction of the parallel strips. | 12-03-2015 |
20150295003 | METHOD OF SIMULTANEOUSLY MANUFACTURING PARTIALLY SHIELDED PIXELS - A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a process wherein a first insulator is deposited on an active area. A first metal level is deposited and defined, with a first mask, to form a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield. A second insulator is deposited, and via openings therein are defined, with a second mask. An overlying second metal level is deposited and defined, with a third mask, to form two connection areas covering the via openings on each side of the first and second pixels. The second and third masks are identical for the first and second pixels. | 10-15-2015 |
20150268094 | AMBIENT LUMINOSITY LEVEL DETECTION - The following steps are performed in connection with a photodiode circuit: a) resetting the photodiode circuit; b) determining when a photodiode voltage changes in response to illumination to reach a threshold; and c) updating a counter in response to the determination in step b). The steps a) to c) are repeated until an end of a measurement period is reached. The value of the counter at the end of the measurement period is then output to indicate an intensity of the illumination. | 09-24-2015 |
20150262941 | PERFORATED ELECTRONIC PACKAGE AND METHOD OF FABRICATION - An electronic package includes an integrated circuit chip mounted to a support plate and encapsulated by an encapsulating body. The package includes at least one weakening deep perforation. The perforation is formed in either the support plate or the encapsulating body, and functions to reduce a resistance of the package to bending stresses perpendicular to the support plate. | 09-17-2015 |
20150215559 | PIXEL CIRCUIT WITH FAST READ OUT - An image sensor includes a first photodiode with associated first sense node and a second photodiode with associated second sense node. A first transistor has its control node coupled to the first sense node and a second transistor has its control node coupled to the second sense node. The conduction paths (for example, source-drain paths) of the first and second transistors are coupled in series between first and second column lines associated with a column of the image sensor array. Switches control connection of the first and second column lines in two modes: one mode where a voltage is applied to the first column line and data from one of the photodiodes is read out by the second column line; and another mode where a voltage is applied to the second column line and data from the other of the photodiodes is read out by the first column line. | 07-30-2015 |
20150155324 | ELECTRONIC DEVICE COMPRISING A CHIP OF INTEGRATED CIRCUITS STACKED WITH AN OPTICAL PLATE - An electronic device is formed by a stack of an integrated circuit chip and an optical plate. The integrated circuit chip includes integrated circuits (such as optical circuits) formed on or in a semiconductor substrate plate. The optical integrated circuits may form an optical sensor. An electrical connection network is provided on the top side of the semiconductor substrate plate. Electrical connection lugs, which are connected to the electrical connection network through electrical connection vias, are mounted on the back side of the semiconductor substrate plate. The vias are through silicon vias situated at a distance from the periphery of the semiconductor substrate plate. The optical plate is configured to allow light radiation to pass to the optical integrated circuits. | 06-04-2015 |
20150115424 | ELECTRONIC SYSTEM COMPRISING STACKED ELECTRONIC DEVICES PROVIDED WITH INTEGRATED-CIRCUIT CHIPS - An electronic system includes a first electronic device (with a first integrated-circuit chip) and a second electronic device (with a second integrated-circuit chip). The second electronic device is stacked above the first electronic device on a same side as the first integrated-circuit chip. Electrical connection elements located around the first integrated-circuit chip electrically connected to the second electronic device to the first electronic device. A metal plate configured for heat capture and transfer extends between the first and second electronic devices. The metal plate includes through-passages aligned to permit the electrical connection elements to pass at a distance. | 04-30-2015 |
20150103489 | INTEGRATED CIRCUIT CHIP COMPRISING ELECTRONIC DEVICE AND ELECTRONIC SYSTEM - An electronic device includes a substrate wafer made of an insulating material and having an electrical connection network. An integrated circuit chip is mounted to a top side of the substrate wafer. The substrate wafer contains an internal duct. The duct is formed by a covered trench located in the top side of the substrate wafer. The trench contains a thermally conductive material, for example being a fluid. Openings in the top side of the substrate wafer that are offset from the trench permit the making of an electrical connection between the integrated circuit and the electrical connection network. | 04-16-2015 |
20150102500 | ELECTRONIC SYSTEM COMPRISING STACKED ELECTRONIC DEVICES COMPRISING INTEGRATED-CIRCUIT CHIPS - An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer. | 04-16-2015 |
20150102499 | INTEGRATED CIRCUIT CHIP COMPRISING ELECTRONIC DEVICE AND ELECTRONIC SYSTEM - An electronic device includes a substrate wafer made of many layers of an insulating material and including an electrical connection network. An integrated circuit chip is mounted to a top side of the substrate wafer. The substrate wafer further includes a metal plate that is integrated into the substrate wafer and thermally coupled to the integrated circuit chip. The metal plate may have a thickness in excess of several layers of the substrate wafer. The metal plate may include a duct through which a thermally conductive fluid flows. | 04-16-2015 |
20150083900 | PROXIMITY SENSOR INCLUDING REFERENCE DETECTOR FOR STRAY RADIATION DETECTION - A proximity sensor includes a radiation source configured to emit a primary radiation beam and a primary detector configured to pick up a reflected primary radiation beam. The radiation source is further configured to emit stray radiation. The sensor further includes a reference detector arranged to receive the stray radiation. The stray radiation may, for example, be emitted from either a side of the radiation source or a bottom of the radiation source. | 03-26-2015 |
20150041865 | PIXEL CIRCUIT - A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage. | 02-12-2015 |
20150036309 | ELECTRONIC DEVICE COMPRISING A SUBSTRATE BOARD EQUIPPED WITH A LOCAL REINFORCING OR BALANCING LAYER - A substrate board includes an electrical connection network on a face thereof. An integrated-circuit chip is mounted to the face of the substrate board in electrical contact with the electrical connection network. A local reinforcing or balancing layer made of a non-metallic material is mounted to the face of the substrate board in at least one local zone free of the face which is free of metal portions of the electrical connection network. | 02-05-2015 |
20150022987 | ELECTRONIC DEVICE COMPRISING AN INTEGRATED CIRCUIT CHIP PROVIDED WITH PROJECTING ELECTRICAL CONNECTION PADS - An electronic device includes an integrated circuit chip with an insulating passivation layer. An opening in the passivation layer uncovers a first region of an electrical contact. An electrical connection pad is formed to fill the opening by covering the first region and extend in projection in such a way as to cover a second region situated on the passivation layer surrounding the opening. The periphery of at least one of the first and second regions has an elongate or oblong shape. Centers of the opening and the pad are aligned with each other. | 01-22-2015 |
20140333834 | MULTIPLE-SENSOR IMAGE ACQUISITION SYSTEM - Each of a first and second image acquisition device includes: a circuit for providing a primary clock signal and a frequency synthesizing circuit capable of generating at least one secondary clock signal from said primary clock signal. The frequency synthesizing circuit in each image acquisition device has a fractional phase-locked loop configuration. A synchronization comparison circuit in each image acquisition device functions to compare sync between an external sync signal and an internal sync signal. An adjustment of the fraction phase lock loop operation is made in response to the sync comparison. | 11-13-2014 |
20140319322 | MULTIPLE CONVERSION GAIN IMAGE SENSOR - An image sensor including an array of pixels, each having: a storage node coupled to a capacitive sense node by a transfer transistor; and a connection transistor coupling the pixel sense node to an intermediate node of the pixel, wherein each pixel has its intermediate node coupled to a node of application of a reset voltage by a reset transistor, and different pixels have their respective intermediate nodes interconnected by a conductive connection track. | 10-30-2014 |
20140289807 | RESOURCE MANAGEMENT IN A PROCESSOR - A processor system is arranged to execute user selected applications. A manager module is configured to detect a user selection of an application and configured to initiate a launch process. A supervisor module is configured to intercept the launch process initiated by the manager module and detect whether the application is a trusted application or an untrusted application. Trusted applications have a privilege to access resources without authorization, and untrusted applications do not have the privilege. The supervisor module has the privilege to access the resources. When the application is untrusted, the application is launched in a container, and at least one of the resources is delivered to the untrusted application in the container. | 09-25-2014 |
20140289748 | LAUNCHING MULTIPLE APPLICATIONS IN A PROCESSOR - A supervisor module manages multiple user selected applications. A first one of the multiple applications is launched in a first container. Allocation of a first process identifier by the first one of the multiple applications in the first container is detected. The first process identifier is unique within the first container. A first unique identifier is allocated to the first one of the multiple applications. The launch of a second one of the multiple applications is delayed but subsequently launched if the first unique identifier has been allocated to the first one of the multiple applications. A second unique identifier is allocated to the second one of the multiple applications. The first and second unique identifiers uniquely identify the respective first and second ones of the multiple applications within the supervisor module. | 09-25-2014 |
20140289736 | MANAGING MULTIPLE SYSTEMS IN A COMPUTER DEVICE - Resources of multiple systems are managed in a computer device. A first processing system having a set of dedicated resources also has a resource manager to manage at least one of the resources. The first processing system is prevented from directly accessing the resources without authorization. A second processing system, connected to the set of dedicated resources, has a supervisor application to grant control to individual resources to the resource manager of the first processing system. A computer program is executed in the first processing system. The supervisor application grants control of at least one resource to the resource manager of the first processing system in a way that is transparently to the computer program executing in the first processing system. | 09-25-2014 |
20140289439 | METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT - A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another. | 09-25-2014 |
20140287705 | Method for Processing a Frequency-Modulated Analog Signal and Corresponding Device - A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results. | 09-25-2014 |
20140267822 | TONE MAPPING METHOD - Generating by a digital processing device, of a first digital image from a second digital image, by: for each pixel of the second image, determining a pixel luminance; dividing the interval ranging from the lowest to the highest luminance into a plurality of sub-intervals; and determining the value of at least one pixel of the first image by multiplying the value of a pixel of the second image by a gain determined by interpolation by taking into account the distance of the pixel luminance of the second image to the limits of the sub-interval containing this luminance. | 09-18-2014 |
20140247979 | METHOD AND DEVICE FOR GENERATING HIGH DYNAMIC RANGE IMAGES - A method of generation, by a digital processing device, of a first high dynamic range digital image from second and third digital images of a same scene, including, for at least one point of the first image: determining a brightness index; comparing this index with at least one of first, second, third, and fourth decreasing thresholds stored in a memory; and determining the value of the point by taking into account the value of the index. | 09-04-2014 |
20140231633 | PROXIMITY SENSOR - A device including a photon emitter, a photon receiver, and a screen opaque to photons following a direct path from the outside of the device to the photon receiver. | 08-21-2014 |
20140206154 | SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND PROCESS FOR FABRICATION - A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block. | 07-24-2014 |
20140191387 | METHOD OF FABRICATING LAND GRID ARRAY SEMICONDUCTOR PACKAGE - A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board. | 07-10-2014 |
20140166859 | CIRCUIT AND METHOD FOR MEASURING AN AMBIENT LIGHT LEVEL - A device includes an image sensor and a circuit for controlling the sensor. The control circuit is configured control the device in a first operating mode and second operating mode. In the first operating mode images acquired by the sensor are output. In the second operating mode, no images are provided, but a selected subassembly of pixels of the image sensor are read and image data therefrom is processed to provide an ambient luminosity value. | 06-19-2014 |
20140117214 | AMBIENT LUMINOSITY LEVEL DETECTION - A method wherein the updating of a counter is triggered when a photodiode reaches a discharge threshold. | 05-01-2014 |
20140112149 | CLOSED LOOP END-TO-END QOS ON-CHIP ARCHITECTURE - An apparatus includes an output configured to output data to a communication path of an interconnect for routing to a target and a rate controller configured to control a rate of the output data. The rate controller is configured to control the rate in response to feedback information from the target. | 04-24-2014 |
20140103197 | PIXEL READ METHOD - A method for reading a pixel, including at least two integration periods, at least one of said periods including at least one integration sub-period, wherein an output value of the pixel is determined by taking into account the amounts of photogenerated charges contained in the pixel at the end of each of said periods and the amount of photogenerated charges stored in a photodiode of the pixel beyond a threshold during said at least one sub-period. | 04-17-2014 |
20140095932 | DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD - A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network. | 04-03-2014 |
20140057394 | METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE - A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer. | 02-27-2014 |
20140050221 | INTERCONNECT ARRANGEMENT - An interconnect arrangement includes a plurality of tag allocators. Each tag allocator is configured to receive at least one stream of a plurality of packet units and further configured to tag each packet unit. Each packet unit is tagged with one of a set of n tags where n is greater than two. At least one stream is tagged with a sequence of tags that is different from a sequence of tags used for at least one other of said streams. The interconnect arrangement also includes a router configured to receive a plurality of streams of tagged packet units and to arbitrate between the streams such that packet units having a same tag are output in a group. | 02-20-2014 |
20140038539 | IMBALANCE CORRECTION IN A DEMODULATOR WITH FULL BAND SAMPLING - A method for demodulating phase quadrature modulated signals in a band of channels includes transposing the band around zero, and selecting a channel in the transposed band. A first pair of phase quadrature signals forming a first complex signal is extracted from the selected channel. A second pair of phase quadrature signals forming a second complex signal is extracted from a symmetrical channel of the selected channel. The method further includes establishing a correlation product based on the first and second complex signals, and correcting the two complex signals to make the correlation product tend towards zero. | 02-06-2014 |
20140023167 | METHOD AND DEVICE FOR ESTIMATING GAIN AND PHASE CORRECTION PARAMETERS WHEN RECEIVING AN OFDM MODULATED SIGNAL - Gain and phase correction parameters are estimated by calculating the error between the value of at least one received bin and a probable value of the transmitted bin, and by correlating this error with the conjugate value of the rotationally compensated symmetrized bin. | 01-23-2014 |
20130342763 | SYSTEM AND METHOD FOR PROCESSING DIGITAL DATA - This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer. | 12-26-2013 |
20130304787 | DIGITAL SERIAL MULTIPLIER - A multiplier of a binary number A by a binary number B may be configured to add each term A | 11-14-2013 |
20130293402 | TEST OF AN EMBEDDED ANALOG-TO-DIGITAL CONVERTER - A method for testing an analog-to-digital converter (ADC) includes applying ramps to the input of the converter, and classifying the digital codes produced by the converter according to a histogram. The converter is declared operational as soon as all the classes of the histogram have reached a minimum count. The minimum count may be equal to 1 in practice. The converter is declared defective if any class does not reach the minimum count before expiry of a time interval. | 11-07-2013 |
20130287254 | Method and Device for Detecting an Object in an Image - A method for detecting at least one object in an image including a pixel array, by means of an image processing device, including searching out the silhouette of the object in the image only if pixels of the image are at the minimum or maximum level. | 10-31-2013 |
20130268990 | ARRANGEMENT AND METHOD - A method includes providing at least one target bandwidth for bandwidth usage on an interconnect, the target bandwidth being for traffic associated with a traffic initiator. The method also includes measuring a served bandwidth and resetting the measuring of served bandwidth in response to an occurrence of an event. | 10-10-2013 |
20130266177 | Method and Device for Detecting an Object in an Image - A method for detecting an object in an image by means of an image processing device, includes several steps of object search in the image at different search scales. During at least one of the search steps, portions of the image are excluded from the search. The size of the portions decreases as the search scale increases. | 10-10-2013 |
20130248887 | OPTICAL ELECTRONIC PACKAGE - An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip. | 09-26-2013 |
20130243333 | Fidelity Measurement of Digital Images - There is provided a method of measuring the similarity of parts of digital image files (IF | 09-19-2013 |
20130235156 | 3D VIDEO TRANSMISSION ON A LEGACY TRANSPORT INFRASTRUCTURE - The present disclosure relates to a method for transmitting two consecutive pairs of images. The method may include decimating each image with a ratio of 2, assembling the two decimated images of each pair in a composite image, transmitting the composite images, and reconstructing complete images from the composite images. In decimation, the information removed from the images of the first pair may be kept in the images of the second pair, from the spatial point of view, and the complete images may be reconstructed by de-interlacing processing from the composite images. | 09-12-2013 |
20130221927 | DEVICE FOR MEASURING THE NO-LOAD VOLTAGE OF A BATTERY - A method for measuring the voltage of a battery of an electronic device by means of a measurement device integrated to the electronic device, wherein, after the connection of the battery to the electronic device, the measurement device prevents battery charge and discharge operations during the measurement. | 08-29-2013 |
20130214976 | METHOD FOR LOCALIZING AN OBJECT - A method for localizing an object, including the acts of: transmission of a first signal by a first transmitter assigned to the object and of a second signal by at least one second transmitter; reception of the first and of the second signal by at least three receivers; in each receiver and for the first and the second signal: a) generation of a first and of a second reference signal; b) correlation between the first signal and the first reference signal and between the second signal and the second reference signal; c) interpolation of samples resulting from the correlation; d) deduction of the propagation time of the first and of the second signal; e) calculation of the difference between the propagation times of the first and of the second signal; and, by triangulation, deduction of the position of the object. | 08-22-2013 |
20130214425 | DUAL SIDE PACKAGE ON PACKAGE - An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material. | 08-22-2013 |
20130195235 | METHOD AND APPARATUS FOR SWITCHING CLOCK FREQUENCY IN A SYSTEM-IN-PACKAGE DEVICE - An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made. | 08-01-2013 |
20130175435 | DEVICE FOR DETECTING AN OBJECT USING SPAD PHOTODIODES - The disclosure relates to a method for detecting the presence of an object near a detection device, comprising: emitting pulses of an incident photon beam, detecting photodiodes which trigger avalanche after the reception by the photodiode of at least one photon of a reflected photon beam produced by a reflection of the incident beam on an object near the detection device, determining a distance between the photodiodes and an object in a detection area, as a function of the time between a transmit time of the incident beam and avalanche triggering times of the photodiodes, and correcting the distance determined as a function of a calibration measurement obtained in the absence of object in the detection area, to compensate for photon reflections on a transparent plate arranged between the photodiodes and the detection area. | 07-11-2013 |
20130169798 | CHECKING DEVICE AND METHOD BASED ON IMAGE PROCESSING - A device for detecting objects includes a vessel intended to contain the objects. A sensor is configured to capture at least one image of the vessel. A processing device is configured to process at least one captured image by detecting objects of the at least one captured image, extracting characteristics of each detected object, and generating a list of the characteristics of each detected object. A memory stores the generated list, the memory also configured to store a first reference list of object characteristics. The processing device further generates a second list of characteristics from a captured image. The characteristics of each object of the second list are compared with, respectively, the characteristics of each object of the reference list. | 07-04-2013 |
20130168840 | SEMICONDUCTOR INTEGRATED DEVICE WITH MECHANICALLY DECOUPLED ACTIVE AREA AND RELATED MANUFACTURING PROCESS - A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package. | 07-04-2013 |
20130155620 | Package - An electronic component package includes a support and heat conductor. The heat conductor has a protuberance and the support has a socket arranged to be able to receive the protuberance so that the movement of heat conductor relative to the support during the assembly process is reduced. | 06-20-2013 |
20130155239 | IMAGE SENSOR WITH IMPROVED DYNAMIC RANGE - An image sensor having improved dynamic range includes a signal that is read out for a selection of pixels which act as a calibration to govern the choice of exposure levels to be applied to the rest of the array. In this way, the sensor is operable to adapt to variations in scene intensity. The pixels in the array are vertically and horizontally addressed so as to enable accounted for small areas of intensity variation across an imaged scene. | 06-20-2013 |
20130154044 | Single-Photon Avalanche Diode Assembly - A single-photon avalanche diode assembly, the diode including a central terminal and a peripheral terminal, the peripheral terminal being connected to an input of a comparator and to a first power supply terminal by a first resistor, the central terminal being connected by a conductive track to a second power supply terminal, a second resistor being arranged in series on said conductive track. | 06-20-2013 |
20130153754 | DEVICE HAVING SPAD PHOTODIODES FOR DETECTING AN OBJECT - The disclosure relates to a method for detecting the presence of an object near a detection device, comprising: reverse biasing single photon avalanche photodiodes, at a bias voltage greater than a breakdown voltage of a PN junction of each photodiode, emitting pulses of an incident photon beam, detecting photodiodes which avalanche trigger after the reception by the photodiode of at least one photon of a reflected photon beam produced by a reflection of the incident beam on an object near the detection device, determining the object presence as a function of the existence of at least one avalanche triggering in one of the photodiodes, and selecting a number of photodiodes to be reverse biased in relation to the detection device, as a function of a load of a circuit for generating the bias voltage. | 06-20-2013 |
20130142227 | COMMUNICATIONS ARRANGEMENT FOR A SYSTEM IN PACKAGE - A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications. | 06-06-2013 |
20130136129 | ZERO-CYCLE ROUTER FOR NETWORKS ON-CHIP - A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel. | 05-30-2013 |
20130127536 | FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER WITH COMMON-MODE FEEDBACK CIRCUIT - A fully differential operational amplifier includes a differential input stage, at least one output stage and a common-mode feedback circuit connected with the input stage. The differential input stage includes a differential pair of transistors and a bias circuit for the differential pair of transistors. A start-up circuit operates to detect an operating condition of the differential pair of transistors of the input stage and in response thereto turn on the bias circuit. | 05-23-2013 |
20130106632 | CALIBRATION OF INTERLEAVED ADC | 05-02-2013 |
20130106631 | INTERLEAVED ADC CALIBRATION | 05-02-2013 |
20130094652 | METHOD AND DEVICE FOR CONTROLLING THE BROADCASTING OF AUDIO CONTENTS BY TWO LOUDSPEAKERS - The broadcasting of audio contents by two loudspeakers is controlled by delivering a first audio content to the two loudspeakers and a further processing in which an auxiliary audio content is received. A second audio content is formed by temporally delaying the auxiliary audio content with a delay dependent on the spacing between the loudspeakers and on a distance between a first loudspeaker and a spot located in front of this first loudspeaker. The second audio content is delivered to the first loudspeaker. A third audio content is formed by inverting the auxiliary audio content. The third audio content is then delivered to the second loudspeaker. | 04-18-2013 |
20130088298 | HIGH PERFORMANCE CLASS AB OPERATIONAL AMPLIFIER - A class AB operational amplifier includes an input stage, an output stage and a level shifter stage to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, and a control circuit of the level shifter stage. The control circuit includes a transistor differential pair having a differential input terminals and the differential voltage at the differential terminals of the differential pair controls the level shifter stage. | 04-11-2013 |
20130079068 | OPTICAL ELECTRONIC PACKAGE - A package includes a substrate with an attached emitting IC chip and receiving IC chip. The emitting IC chip includes an optical emitter, and the receiving IC chip includes a main optical sensor and a secondary optical sensor. A case is provided with a bottom portion and a peripheral wall portion to cover the IC chips, wherein the edge of the peripheral wall portion is mounted to the substrate. The bottom portion of the case includes a main opening above the main optical sensor and a secondary opening above the optical emitter. An opaque material is interposed between the case and the receiving IC chip to isolate the main optical sensor from the secondary optical sensor and delimiting a chamber containing the secondary optical sensor and the optical emitter. The chamber is optically isolated from the main optical sensor and main opening, and may be filled with a transparent material. | 03-28-2013 |
20130077082 | Device and Method for Determining the Distance to an Object - A method and apparatus for defining, from a first periodic signal, a second signal of same period, including the steps of: generating a third signal exhibiting detectable events; and synchronizing the second signal for each event. | 03-28-2013 |
20130071026 | IMAGE PROCESSING CIRCUITRY - A method for performing a modification of the color saturation of at least one pixel of an image involving: determining, based on pixel values of a first pixel, at least one of a color saturation value, luminance value and hue value corresponding to said first pixel; determining, based on said at least one value, a saturation factor; and modifying the color saturation level of said first pixel based on said saturation factor. | 03-21-2013 |
20130069972 | CIRCUITRY FOR IMAGE PROCESSING - A method of increasing the color saturation of the RGB values of at least one pixel of an image, the method involving: calculating a luminance value based on RGB values of a first pixel; calculating a first maximum increase of said color saturation based on the highest of said RGB values and on said luminance value; calculating a second maximum increase of said color saturation based on the lowest of said RGB values and on said luminance value; and increasing the color saturation of said first pixel based on said first and second maximum increases. | 03-21-2013 |
20130069624 | LOW-VOLTAGE DIFFERENTIAL SIGNAL ACTIVITY DETECTOR - An activity detector for a differential signal formed by two components may include a current source connected to a power supply line, and a first transistor has a drain being powered by the current source, and has a source that forms a first input terminal receiving a first component of the differential signal. A second transistor has a drain being powered by the current source, and has a source forms a second input terminal receiving the second component of the differential signal. A bias circuit applies a potential to the gates of the first and second transistors, establishing a balance condition where all the current from the current source is distributed between the two transistors when the first and second input terminal potential is equal to a threshold value. An activity indication terminal is taken from the drains of the first and second transistors. | 03-21-2013 |
20130064448 | IMAGE CHROMA NOISE REDUCTION - An embodiment of a method for reducing chroma noise in digital image data and of a corresponding image processor. Chrominance components are subjected to low-pass filtering. The strength of the low-pass filtering is modulated in accordance with the dynamic range of the luminance signal and the dynamic range of each of the two chrominance signals in order to avoid color bleeding at image-object edges. Moreover, the low-pass filtering is selectively applied to pixels with similar luminance and chrominance values only. A combination of down-sampling and up-sampling units is employed so that comparatively small filter kernels may be used for removing chroma noise with low spatial frequency. | 03-14-2013 |
20130043938 | LOW VOLTAGE ANALOG SWITCH - A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal. | 02-21-2013 |
20130033615 | METHOD OF IMAGE PREVIEW IN A DIGITAL IMAGE PICKUP APPARATUS - The present disclosure relates to a method of image preview in an image pickup apparatus. One embodiment is directed to a method that includes acquiring from an image sensor an image of a scene observed by an image sensor of the apparatus, generating a preview image obtained by applying to the acquired image a resolution reduction process to adapt it to the resolution of a display screen of a viewfinder of the image pickup apparatus, displaying the preview image on the display screen, generating an image of an area of the scene by extracting an area from the acquired image, and displaying the area image superimposed on the preview image or alternately with the preview image, the area image displayed having a resolution higher than that of the preview image and inferior or equal to that of the acquired image. | 02-07-2013 |
20130027563 | METHOD OF REAL-TIME CHECKING OF A MATRIX IMAGING DEVICE, AND ASSOCIATED DEVICE - A method is for monitoring the electrical integrity of lines of photosites of an imaging device with matrix array of photosites. The control lines of photosites may include for each line of photosites an emission of elementary electrical control signals for the photosites of the line. The method may include diagnosis of the elementary electrical control signals emitted. | 01-31-2013 |
20130022286 | IMAGE PROCESSING METHOD - The present disclosure relates to a method for improving the perception of an image. The method may include subjecting an original image to a series of independent processes, each producing a pixel calculated using a respective reference kernel. The reference kernels each may comprise pixels from the original image. | 01-24-2013 |
20130022269 | DIFFERENTIATED PROCESSING METHOD OF IMAGE ZONES - A method for improving the perception of an image may include performing a main separation of the pixels of the image into two categories, one corresponding to pixels of a flat zone, and the other corresponding to pixels of a textured zone. The method may also include processing the pixels of each category according to a method optimized according to the type of zone. Before the main separation step, a preliminary separation of the pixels may be performed into one category of normal pixels intended for the main separation step, and one category of singular pixels, with the criterion for selecting the singular pixels being adapted to identify pixels that would be wrongly identified as pixels of a textured zone. The singular pixels may then be processed according to a method adapted to their nature. | 01-24-2013 |
20130016478 | ELECTRONIC PACKAGE WITH THERMAL VIAS, AND FABRICATION PROCESSAANM Gagnieux; JeanAACI MontaudAACO FRAAGP Gagnieux; Jean Montaud FRAANM Pailhes; MaximeAACI La BuisseAACO FRAAGP Pailhes; Maxime La Buisse FR - An electronic package includes at least one heat-transfer element interposed between a front side of an integrated-circuit chip and a back side of a heat-transfer plate. An encapsulation block has a portion lying between the front side of the integrated-circuit chip and the back side of the heat-transfer plate. The portion embeds the heat-transfer element. Another heat transfer element is interposed between a front side of a electrical-connection support plate and a rim portion of the heat-transfer plate. | 01-17-2013 |
20130015910 | DEVICE FOR TRANSFERRING PHOTOGENERATED CHARGES AT HIGH FREQUENCY AND APPLICATIONSAANM Tubert; CedricAACI SassenageAACO FRAAGP Tubert; Cedric Sassenage FRAANM Roy; FrancoisAACI SeyssinsAACO FRAAGP Roy; Francois Seyssins FRAANM Mellot; PascalAACI Lans en VercorsAACO FRAAGP Mellot; Pascal Lans en Vercors FR - A device for transferring charges photogenerated in a portion of a semiconductor layer delimited by at least two parallel trenches, each trench including, lengthwise, at least a first and a second conductive regions insulated from each other and from the semiconductor layer, including the repeating of a first step of biasing of the first conductive regions to a first voltage to form a volume accumulation of holes in the area of this portion located between the first regions, while the second conductive regions are biased to a second voltage greater than the first voltage, and of a second step of biasing of the first regions to the second voltage and of the second regions to the first voltage. | 01-17-2013 |
20130015892 | DOUBLE-POINT MODULATOR WITH ACCURATE AND FAST GAIN CALIBRATIONAANM Badets; FranckAACI VoironAACO FRAAGP Badets; Franck Voiron FRAANM Ramet; SergeAACI JarrieAACO FRAAGP Ramet; Serge Jarrie FRAANM Ayraud; MichelAACI VoreppeAACO FRAAGP Ayraud; Michel Voreppe FR - A phase-locked loop double-point modulator may include a frequency divider having a ratio which can be changed by a first modulation signal, and an oscillator, a frequency of which can be changed by a second modulation signal correlated to the first modulation signal. A calibration circuit may be configured, in a calibration mode, to match the gains of the first and second modulation signals based on frequency measurements of the oscillator for two different calibration values of the second modulation signal. The phase-locked double-point modulator may also include an attenuator having a constant ratio greater than 1 and placed in the path of the second modulation signal, and a selector switch configured to be controlled by the calibration circuit to reduce the ratio of the attenuator in the calibration mode. | 01-17-2013 |
20130012276 | OPTICAL ELECTRONIC PACKAGE - An electronic package includes a substrate wafer having front and rear faces. An emitting integrated circuit chip is mounted to the front face of the substrate wafer and includes a light radiation optical emitter. A receiving integrated circuit chip is also mounted to the front face of the substrate wafer and includes at least one light radiation optical sensor. A transparent encapsulant extends above the optical sensor and the optical emitter. An opaque encapsulant encapsulates the transparent encapsulant. The opaque encapsulant has a front window situated above the optical emitter and which is offset laterally relative to the optical sensor. The transparent encapsulant accordingly has an uncovered front face situated above the optical emitter and offset laterally relative to the optical sensor. The opaque encapsulant may include an additional front window. The receiving integrated circuit chip further includes a second optical sensor situated opposite the additional front window. | 01-10-2013 |
20130009173 | OPTICAL ELECTRONIC PACKAGE - An electronic package includes a substrate wafer having front and rear faces and a through passage having a front window and a blind cavity communicating laterally with the front window. A receiving integrated circuit chip is mounted on the rear face and includes an optical sensor situated opposite the blind cavity. A transparent encapsulant extends above the optical sensor and at least partially fills the through passage. An emitting integrated circuit chip, embedded in the transparent encapsulant, includes an optical emitter of luminous radiation. The emitting integrated circuit chip may be mounted to the front face or within the through passage to the receiving integrated circuit chip. The substrate wafer may further include a second through passage. The receiving integrated circuit chip further includes a second optical sensor situated opposite the second through passage. A cover plate is mounted to the front face at the second through passage. | 01-10-2013 |
20130001777 | COPPER WIRE RECEIVING PAD - On embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad. | 01-03-2013 |
20120328186 | METHOD FOR IMPROVING THE VISUAL PERCEPTION OF A DIGITAL IMAGE - The method for improving the visual perception of a digital image may comprise dividing the digital image into repetitive areas, and modifying the tone curve and/or the histogram of each area to improve the visual perception of the corresponding area. Lastly, the joins between adjacent areas may be smoothed. | 12-27-2012 |
20120327977 | FAST BLIND CHANNEL SEARCH - A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike. | 12-27-2012 |
20120326332 | SEMICONDUCTOR DEVICE WITH ENCAPSULATED ELECTRICAL CONNECTION ELEMENTS AND FABRICATION PROCESS THEREOF - An integrated-circuit chip and external electrical connection elements are arranged on a first side of a substrate to form an assembly that is placed within a mold. The mold includes first and second opposed planar faces with a molding film made of a deformable material on the first planar face. The molding film is pressed against end faces of the external electrical connection elements. Encapsulating material then fills the mold cavity producing a semiconductor device that, when removed from the mold, includes electrical connection elements that are peripherally coated by the encapsulating material and have exposed end faces. An additional semiconductor device may be mounted over and in electrical connection with the electrical connection elements through the exposed end faces. | 12-27-2012 |
20120313874 | METHOD OF MANUFACTURING A VIBRATORY ACTUATOR FOR A TOUCH PANEL WITH HAPTIC FEEDBACK - The disclosure relates to a method of manufacturing vibratory elements, comprising forming on a substrate a multilayer structure by an integrated circuit manufacturing method, the multilayer structure comprising an element susceptible of vibrating when it is subjected to an electrical signal, and electrodes for transmitting an electrical signal to the vibratory element, the vibratory element comprising a mechanical coupling face that is able to transmit to control element vibrations perceptible by a user. | 12-13-2012 |
20120313766 | METHOD OF CONTROLLING A HANDHELD OBJECT USING HAPTIC FEEDBACK - The disclosure relates to a method for controlling an object configured to be handheld and including vibratory actuators. The method including mechanically coupling a first group of at least one vibratory actuator to a first part of the object, mechanically coupling a second group of at least one vibratory actuator to a second part of the object, the first and the second parts being configured to be able to vibrate independently of each other, and to come into contact with different areas of the hand of the user holding the object, and transmitting to each group of actuators, an electrical signal having a frequency adapted to the resonance frequency of the part to which it is mechanically coupled. | 12-13-2012 |
20120281713 | COMMUNICATION SYSTEM AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD - A communication system transmits data from a first circuit over a communication channel to a second circuit, the data having a first priority and a second priority. The communication system includes a separation circuit, a first-in first-out (FIFO) memory, and a control circuit. | 11-08-2012 |
20120261820 | ASSEMBLY OF STACKED DEVICES WITH SEMICONDUCTOR COMPONENTS - A method for forming an assembly including, stacked on each other, first and second devices with semiconductor components including opposite conductive balls, this method including the steps of: a) forming, on the first device, at least one resin pattern, close to at least some of the conductive balls by a distance smaller than or equal to half the ball diameter, and of a height greater than the ball height; and b) bonding the second device to the first device, by using said at least one pattern to guide the balls of the second device towards the corresponding balls of the first device. | 10-18-2012 |
20120248625 | SEMICONDUCTOR PACKAGE COMPRISING AN OPTICAL SEMICONDUCTOR DEVICE - A semiconductor package includes a transmissive support plate and includes at least one elongate hole. An integrated circuit semiconductor device is mounted on a rear face of the support plate. The semiconductor device includes first and second optical elements oriented towards the rear face of the support plate, where the first and second optical elements are placed on either side of the elongate hole. An encapsulation material made of an opaque material encapsulates the semiconductor device and fills the elongate hole so as to form an optical insulation partition between the first and second optical elements. A cavity is left, however, between each optical element and a rear face of the support plate. | 10-04-2012 |
20120176533 | IMAGING DEVICE WITH AMBIENT LIGHT SENSING MEANS - An imaging device includes a fixed focused lens, an image sensor having a image matrix of a plurality of pixels arranged on a semiconductor substrate and supplying image data, and electronic means for reading the image matrix. The image sensor also comprises at least two ambient light sensors arranged on the semiconductor substrate on opposite sides of the image matrix, and configured to capture an ambient light intensity through the fixed lens, and the electronic means is also configured to read the two ambient light sensors and to supply ambient light data and the image data. | 07-12-2012 |
20120162410 | 3D IMAGE SENSOR - An integrated image sensor capable of determining the distance to objects contained in a scene including at least a set of first pixels and a set of second pixels, the first and second pixels being alternately distributed in an array, the first pixels having a different angular aperture than the second pixels. | 06-28-2012 |
20120162391 | THREE-DIMENSIONAL IMAGE SENSOR - An integrated image sensor capable of determining the distance to objects contained in a scene, including a pixel array, each pixel in the array being associated with a microlens and being formed of an assembly of sub-pixels, each including a photosensitive area. | 06-28-2012 |
20120161802 | DIGITAL CIRCUIT TESTABLE THROUGH TWO PINS - A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin. | 06-28-2012 |
20120159095 | INTERFACE SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD - An interface system for interfacing an asynchronous circuit with a synchronous circuit, wherein the synchronous circuit samples, in response to a clock signal, a first data signal when a first control signal indicates that the first data signal contains valid data, and wherein the asynchronous circuit generates a second data signal according to an asynchronous communication protocol. The system includes a FIFO memory, a control circuit for asynchronously writing the second data signal in the memory when the second data signal indicates the start of a communication, and synchronously reading the second data signal from the memory in response to a clock signal, and a conversion circuit for decoding, according to a asynchronous communication protocol, the second data signal read from the memory in a decoded data signal, wherein the decoded data signal corresponds to the first data signal. | 06-21-2012 |
20120159017 | METHOD AND APPARATUS FOR ROUTING TRANSACTIONS THROUGH PARTITIONS OF A SYSTEM-ON-CHIP - A node having a node input is configured to receive a plurality of transactions intended for a plurality of different targets. The node has multiple node outputs. At least one target is provided, that target including an input configured to receive a respective output of the node. The node is configured to direct transactions to the at least one target or an output (for passing to a different partition) depending on whether the transactions are intended for the target or a different target. This determination is made in response to a conversion operation which converts a target address of the transaction to an identification associated with the target or the output. | 06-21-2012 |
20120155489 | COMMUNICATION SYSTEM, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD - A communication system includes interfacing between a first synchronous circuit and a second synchronous circuit. The system includes a first interface system and a second interface system. The first interface system receives data from the first synchronous circuit, and encodes the data according to an asynchronous communication protocol. The encoded data are transmitted over a communication channel to the second interface system. The second interface system decodes the data and transmits the decoded data to the second synchronous circuit. The first interface system includes a first FIFO memory for storing temporarily the data received from the first synchronous circuit and the second interface system includes a second FIFO memory for storing temporarily the data transmitted over the communication channel. | 06-21-2012 |
20120153422 | Imaging Device with Filtering of the Infrared Radiation - An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation. | 06-21-2012 |
20120153394 | METHOD FOR MANUFACTURING A STRAINED CHANNEL MOS TRANSISTOR - A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate. | 06-21-2012 |
20120148186 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES - A process for fabricating semiconductor devices provides a wafer of integrated circuits, permanently attaches an optical wafer to the wafer of integrated circuits, and temporarily attached a supporting wafer to the optical wafer. The supporting wafer provides structural support during further fabrication processes where a back side of the wafer of integrated circuits is thinned and through silicon vias are formed. The supporting wafer is then removed and the wafer of integrated circuits with the optical wafer is singulated into individual integrated-circuit chips. | 06-14-2012 |
20120146170 | MANUFACTURING OF A CAMERA MODULE - A camera module includes a sensor die, a glass plate, peripheral spacer, an optical element, an outer surface having a shoulder extending in a direction substantially parallel to the sensor die, and a metal layer at least partially covering the outer surface. A method of manufacturing a camera module includes providing an assembly including a sensor dice wafer, a spacer wafer in front of the sensor dice wafer, and an optical element wafer in front of the spacer wafer. The method includes sawing a top cut, using a first saw blade of a first thickness, proceeding in a direction from the optical element wafer toward the sensor dice wafer, stopping before the sensor dice wafer is reached, and sawing a bottom cut, using a second saw blade of a second thickness, proceeding in a direction from the sensor dice wafer toward the optical element wafer. | 06-14-2012 |
20120137115 | METHOD AND DEVICE FOR SIMULATING A RESET SIGNAL IN A SIMULATED SYSTEM ON CHIP - A method and system for simulating a reset signal in a modeled system comprises a reset control module and a module to be reset. Operations of the system include emitting by a control thread of the control module a reset signal, receiving by the module to be reset the reset signal, waking up a thread of the module to be reset, and waiting for a reset signal. If the thread is woken up by the reset signal further operations include activating a reset exception by the thread, and if a reset exception is raised, making the thread wait for a reboot signal, transmitting the reboot signal by the control thread to the module to be reset, and after receiving the reboot signal, activating the thread which executes and waits for a reset signal. | 05-31-2012 |
20120133039 | SEMICONDUCTOR PACKAGE WITH THERMAL VIA AND METHOD OF FABRICATION - A semiconductor package includes a block for encapsulating a microchip and its electrical connection wires. The encapsulating block has at least one front recess disposed on top of the microchip. A thermally conducting filling material fills the front recess so as to form a thermal via. A radiating structure is attached over the encapsulating block and in thermal communication with the thermal via. | 05-31-2012 |
20120126892 | REFERENCE VOLTAGE GENERATOR FOR BIASING AN AMPLIFIER - A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage. | 05-24-2012 |
20120126094 | ANALOG TO DIGITAL RAMP CONVERTER - A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal. | 05-24-2012 |
20120112873 | VIALESS INTEGRATION FOR DUAL THIN FILMS - THIN FILM RESISTOR AND HEATER - A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films. | 05-10-2012 |
20120104454 | OPTICAL DEVICE, PROCESS FOR FABRICATING IT AND AN ELECTRONIC PACKAGE COMPRISING THIS OPTICAL DEVICE - An optical device includes at least one optical die ( | 05-03-2012 |
20120098684 | Device and Method for Processing an Analogue Signal - Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset. | 04-26-2012 |
20120092459 | METHOD AND DEVICE FOR RECONSTRUCTION OF A THREE-DIMENSIONAL IMAGE FROM TWO-DIMENSIONAL IMAGES - The disclosure relates to a method for reconstruction of a three-dimensional image of an object. A first image is acquired of the object lit by a luminous flux having, in a region including the object, a luminous intensity dependant on the distance, with a light source emitting the luminous flux. A second image is acquired of the object lit by a luminous flux having, in a region including the object, a constant luminous intensity. For each pixel of a three-dimensional image, a relative distance of a point of the object is determined as a function of the intensity of a pixel corresponding to the point of the object in each of the acquired images. | 04-19-2012 |
20120092358 | Noise-robust edge enhancement system and method for improved image sharpness - A system for edge enhancement includes an input unit to receive an input signal Yin, a vertical enhancement unit to perform a vertical enhancement of an edge of the input signal Yin to generate an output YEV, and a horizontal enhancement unit to perform a horizontal enhancement of the edge of the input signal Yin to generate an output YEH. The system also includes a local gradient analysis unit to generate a local gradient direction GradDir and a local gradient magnitude GradMag based at least partly upon the input signal Yin, and a mixer to generate an output Yout by mixing the output YEV with the output YEH using the local gradient direction GradDir. The system further includes an output unit to output the output Yout. | 04-19-2012 |
20120092071 | CLASS-AB OUTPUT STAGE - An output stage of a class-AB amplifier, including: a first transistor of a first channel type between a first terminal of application of a first voltage and an output terminal of the stage, having its gate connected to a first input terminal of the stage; a first transistor of a second channel type between this output terminal and a second terminal of application of the first voltage, having its gate connected to a second input terminal of the stage; and second and third transistors of the second channel type between the output terminal and the first transistor of the second channel type, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor of the second channel type, and the gate of the third transistor being biased to a fixed voltage. | 04-19-2012 |
20120081137 | TESTING METHOD FOR SEMICONDUCTOR INTEGRATED ELECTRONIC DEVICES AND CORRESPONDING TEST ARCHITECTURE - A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method. | 04-05-2012 |
20120079154 | TRANSACTION REORDERING ARRANGEMENT - An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued. | 03-29-2012 |
20120079148 | REORDERING ARRANGEMENT - An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are configured to provide respective responses to respective requests. The network-on-chip further includes an interconnect for routing said requests and respective responses to said requests to and from the plurality of sources and at least one transaction reordering arrangement. The transaction reordering arrangement is configured to reorder said responses such that said responses are provided to a respective source in an order which corresponds to an order in which the requests are issued by said respective source. A respective transaction reordering arrangement is associated with a respective source. | 03-29-2012 |
20120061849 | SEMICONDUCTOR COMPONENT AND DEVICE PROVIDED WITH HEAT DISSIPATION MEANS - A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components. | 03-15-2012 |
20120033806 | METHOD OF ENCRYPTING A DATA STREAM - The disclosure relates to a method of encrypting or of decrypting a binary data stream by generating a binary encryption stream and combining by a reversible logic operation each bit of the binary data stream with a bit of the binary encryption stream, the generation of the binary encryption stream including generating an input block by applying a cryptographic function using a secret key to a data block, and generating the binary encryption stream from the input block by combining the bits of the input block with each other by logic operations in a manner so as to prevent the input block from being determined from the binary encryption stream. | 02-09-2012 |
20120021606 | PROCESS FOR PRODUCING TWO INTERLEAVED PATTERNS ON A SUBSTRATE - A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern. | 01-26-2012 |
20120012736 | Image Sensor - Image sensor, comprising a matrix of active pixels having several columns for delivering at least one information signal of an active pixel, the sensor comprising means for processing the information signals delivered by the said active pixels which comprise at least one amplification stage biased by a current source, the processing means comprising a device for voltage-limiting the signal delivered on an output terminal of the said at least one amplification stage comprising an input terminal connected to the output terminal, a first transistor connected between the input terminal and a reference terminal connected to a reference power supply source, a gain device comprising an input connected to the input terminal, an output connected to the gate of the first transistor and configured so as to decrease the voltage span necessary to cause the first transistor to toggle from its off state to a state in which it absorbs the current provided by the said current source. | 01-19-2012 |
20120007663 | INTEGRATED CIRCUIT WITH DEVICE FOR ADJUSTMENT OF THE OPERATING PARAMETER VALUE OF AN ELECTRONIC CIRCUIT AND WITH THE SAME ELECTRONIC CIRCUIT - An integrated circuit includes an electronic circuit and a device for adjustment of the operating parameter value of the electronic circuit. The electronic circuit comprises a resistive stage. The device comprises a first circuit portion adapted to adjust said operating parameter when the device is active and the electronic circuit is inactive, and adapted to be inactive when the electronic circuit is active, and a second circuit portion adapted to determine the active or inactive state of the device in response to the value of an external control signal. The integrated circuit comprises a first external terminal for the connection to ground, a second external terminal for inputting said control signal, a further external terminal for inputting a further external signal and a deactivation circuit driven by said further external signal to deactivate the electronic circuit when the device is active. | 01-12-2012 |
20120001904 | METHOD OF PROCESSING 3D IMAGES, AND CORRESPONDING SYSTEM - The method is for processing a multiplex image, the multiplex including at least one first view intended to be viewed by a first eye of an observer and at least one second view intended to be viewed by a second eye of the observer. The two views are spatially sub-sampled according to complementary grids and mutually spatially shifted. The method includes a demultiplexing of the multiplex image so as to extract the first and the second views. And, for at least one missing pixel of the first view, there is a determination of a first window of the first view containing the location of the missing pixel and representing a first detail in the first view, a determination of a second window of the second view representing the same first detail in the second view, and a formulation of the missing pixel by using the pixels of the second window. | 01-05-2012 |
20120001668 | DIE AND A PACKAGE COMPRISING A PLURALITY OF DIES - A first die includes a controller configured to select at least one task to be performed by the first die and signal circuitry configured in response to the selection of the at least one task to provide a signal to be sent to a second die for initiating performance of at least one task on the second die which corresponds to (and is to be performed in a time coordinated manner with) the at least one task on the first die. The first die has task circuitry configured to perform the task in response to generation of the signal, and the second die has task circuitry configured to perform the corresponding task in response to receipt of the signal. | 01-05-2012 |
20110320669 | COMMUNICATION SYSTEM AND METHOD - A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted. | 12-29-2011 |
20110305390 | METHOD AND DEVICE FOR PROCESSING A DIGITAL IMAGE - A digital image including a plurality of pixels is processed. Each pixel has at least one colorimetric component. The processing of the image includes processing for each pixel of a group of pixels of the image and for each colorimetric component of the pixel. In this processing, a modification is made to the value of the colorimetric component so as to obtain a modified value situated inside or outside a colorimetric range. A comparison is made of the modified value to the upper and lower limits of the associated colorimetric range. If the corrected value is outside the associated colorimetric range, a corrected value equal to an additional value is assigned to the corresponding colorimetric component of the pixel. The additional value is chosen to be unique and included in the associated colorimetric range and different from the values of the limits of the associated colorimetric range. | 12-15-2011 |
20110302471 | CIRCUITRY FOR BUILT-IN SELF-TEST - A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested. | 12-08-2011 |
20110299783 | Object Detection in an Image - The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions ( | 12-08-2011 |
20110299581 | BUILT-IN SELF-TEST CIRCUITRY - A method of generating at least one test sequence for testing a data connection, the method involving selectively combining by a logic function ( | 12-08-2011 |
20110289253 | INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP - Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue. | 11-24-2011 |
20110286383 | Demodulator for High Bit Rate Transmission and Corresponding Demodulation Method - Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames. | 11-24-2011 |
20110278733 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE COMPRISING A CHIP WITH THROUGH-VIAS - A semiconductor device includes a first wafer having at least one first integrated-circuit chip and a first support layer surrounding the first integrated circuit chip. A first electrical-connection layer is placed on a frontside of the first wafer and includes a first electrical-connection network. A second wafer is placed on a frontside of the first electrical-connection layer. The second wafer includes at least one second integrated-circuit chip and a second support layer surrounding the second integrate circuit chip. The second integrated circuit chip has an active side facing the first electrical-connection layer, and one or more through-holes filled with a conductor forming electrical-connection vias. A second electrical-connection layer is placed on the backside of the second wafer and includes a second electrical-connection network. | 11-17-2011 |
20110225400 | Device for Testing a Multitasking Computation Architecture and Corresponding Test Method - A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation architecture. The execution of the instruction sequences is controlled so that the sequences are alternately executed within the computation architecture. | 09-15-2011 |
20110213944 | SYNCHRONIZATION SYSTEM AND RELATED INTEGRATED CIRCUIT - A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency. | 09-01-2011 |
20110199149 | METHOD AND DEVICE FOR DRIVING THE FREQUENCY OF A CLOCK SIGNAL OF AN INTEGRATED CIRCUIT - An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases. | 08-18-2011 |
20110167316 | METHOD AND DEVICE FOR ROW AND COLUMN INTERLEAVING OF BLOCKS OF VARIABLE SIZE - The present disclosure relates to a method for interleaving a stream of input data blocks, the method comprising steps of: subdividing a block into sub-blocks of fixed size in number of data rows and data columns, the sub-blocks being distributed in the block in rows of sub-blocks and in columns of sub-blocks, transferring the data contained in the block into a first memory, while respecting the order of the data in the input stream, transferring the data contained in the block by row of sub-blocks, into a second memory in which the data of each sub-block is accessible from the address of the sub-block, transferring the data of each sub-block by column of sub-blocks, from the second memory into a third memory, by putting back the data of each sub-block in data rows and columns, and transferring the data by data column from the third memory into an output stream. | 07-07-2011 |
20110164831 | METHOD FOR DETECTING ORIENTATION OF CONTOURS - A method for detecting orientation of the contours in an image, performs an initial transformation of the image using a non-decimated multi-resolution transform, segments the image into a plurality of blocks, determines the optimal resolution for each block, and detects the predominant direction of contour for each of the blocks. | 07-07-2011 |
20110160912 | METHOD AND SYSTEM FOR CONTROLLING ELECTRICAL MACHINES - An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities. The calculation of the square root includes: calculating an approximated value of the square root, having a first precision, and then calculating a corrective value and combining said approximated value with said corrective value to obtain a square root value having a second precision greater than the first precision. | 06-30-2011 |
20110148533 | CRYSTAL OSCILLATOR WITH FAST START-UP AND LOW CURRENT CONSUMPTION - An oscillator comprises an inverter, with a resonator connected between an input and an output of the inverter. A transistor external to the inverter is connected in a current mirror mode with a transistor of the inverter so that the inverter's transistor copies the current of the external transistor. The external transistor has its drain terminal connected to the gate terminals of the inverter's transistor and of the external transistor. A current source is connected to the gate terminal of the inverter's transistor, and a switch is connected between the drain and gate terminals of the external transistor. Circuitry controls the switch so as to open the connection between the drain and gate terminals of the external transistor at the beginning of a start-up phase of the oscillator. | 06-23-2011 |
20110141805 | METHOD OF PROGRAMMING AN ELECTRICALLY PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY POINT, AND CORRESPONDING MEMORY DEVICE - An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line. | 06-16-2011 |
20110141078 | AMBIENT LIGHT DETECTION - Ambient light is detected by a photodiode circuit by measuring the time taken for a digital output of the photodiode circuit to change state in response to exposure of a photodiode of the photodiode circuit to that ambient light. A nominal time for state change is calculated based on photodiode circuit characteristics. Furthermore, an effective time for the photodiode circuit digital output to change state is determined in a calibration mode where the photodiode has been disconnected and a reference current is applied to the circuit. An illumination value of the detected ambient light is then calculated as a function of: the measured time, the effective time and the nominal time. | 06-16-2011 |
20110125437 | METHOD AND DEVICE FOR ANALYZING THE BEHAVIOR OF A POWER SUPPLY IN A CIRCUIT - A method for testing an integrated circuit, comprising performing a series of at least three tests, each comprising: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken. | 05-26-2011 |
20110116773 | METHOD AND DEVICE FOR CONTROLLING PLAYING SPEED OF A COMPRESSED DIGITAL VIDEO SEQUENCE (TRICKMODE) - A method of playing a compressed digital video sequence, comprising steps comprising attributing to each frame a display duration determined as a function of a playing speed set point, and at each period of a frame synchronization signal: if a display duration cumulative value is equal to or greater than a threshold value corresponding to the period of the synchronization signal, playing a previously acquired decoded frame and decreasing the cumulative value of the threshold value; and if the present cumulative value is less than the threshold value, acquiring a new decoded frame and adding the display duration attributed to the newly acquired frame to the cumulative value, until the cumulative value is equal to or greater than the threshold value, playing a last decoded frame acquired and decreasing the cumulative value of the threshold value. | 05-19-2011 |
20110096876 | METHOD AND DEVICE FOR DETECTING A PHASE ERROR OF A SIGNAL - A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component. | 04-28-2011 |
20110018135 | METHOD OF ELECTRICALLY CONNECTING A WIRE TO A PAD OF AN INTEGRATED CIRCUIT CHIP AND ELECTRONIC DEVICE - A wire is electrically connected to an electrical bonding pad of an integrated circuit chip and electronic device through an intermediate electrical interconnect block that is interposed between the electrical bonding pad and one end of the electrical lead wire. | 01-27-2011 |
20100325318 | DATA STREAM FLOW CONTROLLER AND COMPUTING SYSTEM ARCHITECTURE COMPRISING SUCH A FLOW CONTROLLER - A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters. | 12-23-2010 |
20100321082 | METHOD AND DEVICE FOR CONTROLLING A COMMON-MODE VOLTAGE OF A SWITCHED-CAPACITOR SYSTEM, IN PARTICULAR AN ANALOG-TO-DIGITAL CONVERTER - The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path. | 12-23-2010 |
20100308904 | DEVICE FOR GENERATING A REFERENCE VOLTAGE DESIGNED FOR A SYSTEM OF THE SWITCHED-CAPACITOR TYPE - The device generates a reference voltage, in particular designed for a system of the switched-capacitor type, based on a setpoint voltage. It includes a regulation loop having a first input to receive the setpoint voltage, and an output stage arranged as a voltage follower and looped to a second input of the loop. An additional stage is configured to deliver the reference voltage to the switched-capacitor system, this additional stage, coupled to the output stage, also being arranged as a voltage follower and paired with the output stage. | 12-09-2010 |
20100289472 | LOW DROPOUT VOLTAGE REGULATOR WITH LOW QUIESCENT CURRENT - The disclosure relates to a low dropout voltage regulator comprising a regulation transistor to supply an output voltage from an input voltage, a gate control stage to supply a gate voltage to the regulation transistor, and an error amplifier to supply a control voltage to a control terminal of a control transistor. The low dropout voltage regulator also comprises a quiescent current control circuit to limit a quiescent current flowing through the gate control stage when the input voltage approaches the output voltage and causes the regulation transistor to enter into an ohmic conduction mode. The quiescent current control circuit comprises a current source providing a reference current and is configured to control the quiescent current by current-mirror effect based upon the reference current. | 11-18-2010 |
20100272292 | METHOD AND DEVICE FOR CONTROLLING THE BROADCASTING OF AUDIO CONTENTS BY TWO LOUDSPEAKERS - The broadcasting of audio contents by two loudspeakers is controlled by delivering a first audio content to the two loudspeakers and a further processing in which an auxiliary audio content is received. A second audio content is formed by temporally delaying the auxiliary audio content with a delay dependent on the spacing between the loudspeakers and on a distance between a first loudspeaker and a spot located in front of this first loudspeaker. The second audio content is delivered to the first loudspeaker. A third audio content is formed by inverting the auxiliary audio content. The third audio content is then delivered to the second loudspeaker. | 10-28-2010 |
20100253429 | METHOD FOR MEASURING THE SATURATION RATE OF AN AUDIO AMPLIFIER - A method and corresponding circuit that adjusts the gain of an audio output stage having a class D amplifier, this method including the steps of setting the gain to a nominal value, analyzing an output signal during successive clock periods, counting the number of clock periods during which the signal is in a state corresponding to a saturation, decreasing the gain if the number reaches, before the end of a first time interval, a value corresponding to a first percentage, maintaining the gain constant if, at the end of a second time interval, different from the first interval, the number corresponds to a second percentage being comprised between the first percentage and a third percentage, and increasing the gain if, at the end of the second time interval, the number corresponds to a fourth percentage, lower than the third percentage. | 10-07-2010 |
20100244229 | SEMICONDUCTOR PACKAGE FABRICATION PROCESS AND SEMICONDUCTOR PACKAGE - A substrate is provided with electrical connection pads on a front face and on a rear face, the front pads and rear pads being selectively connected via a network passing through the substrate. A peripheral edge of the substrate is mounted on a rigid annular frame and the rearm face secured to a suction table. A layer of a dielectric sealant containing electrically conductive particles is deposited on the front face and front pads of the substrate. Integrated-circuit chips are positioned on the front face to flatten the layer of dielectric sealant, the included electrically conductive particles making electrical connection between pads of the integrated-circuit and the front pads of the substrate. The resulting assembly in then encapsulated in a block of encapsulating material positioned on top of the front face of the substrate. The block is then diced in order to obtain a plurality of semiconductor packages. | 09-30-2010 |
20100225509 | ANALOG-DIGITAL CONVERTER WITH PIPELINE ARCHITECTURE ASSOCIATED WITH A PROGRAMMABLE GAIN AMPLIFIER - A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold. | 09-09-2010 |
20100176845 | METHOD FOR DETECTING THE LOCKING OF A PHASE-LOCKED LOOP AND ASSOCIATED DEVICE - A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected. | 07-15-2010 |
20100157035 | ANALOG-TO-DIGITAL CONVERSION IN IMAGE SENSORS - An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear. | 06-24-2010 |