| STMICROELECTRONICS (GRENOBLE 2) SAS Patent applications |
| Patent application number | Title | Published |
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| 20120137115 | METHOD AND DEVICE FOR SIMULATING A RESET SIGNAL IN A SIMULATED SYSTEM ON CHIP - A method and system for simulating a reset signal in a modeled system comprises a reset control module and a module to be reset. Operations of the system include emitting by a control thread of the control module a reset signal, receiving by the module to be reset the reset signal, waking up a thread of the module to be reset, and waiting for a reset signal. If the thread is woken up by the reset signal further operations include activating a reset exception by the thread, and if a reset exception is raised, making the thread wait for a reboot signal, transmitting the reboot signal by the control thread to the module to be reset, and after receiving the reboot signal, activating the thread which executes and waits for a reset signal. | 05-31-2012 |
| 20120133039 | SEMICONDUCTOR PACKAGE WITH THERMAL VIA AND METHOD OF FABRICATION - A semiconductor package includes a block for encapsulating a microchip and its electrical connection wires. The encapsulating block has at least one front recess disposed on top of the microchip. A thermally conducting filling material fills the front recess so as to form a thermal via. A radiating structure is attached over the encapsulating block and in thermal communication with the thermal via. | 05-31-2012 |
| 20120126892 | REFERENCE VOLTAGE GENERATOR FOR BIASING AN AMPLIFIER - A method generates a reference voltage by steps including: generating a reference signal from a voltage source; generating a comparison signal of the reference signal with a voltage reference; sampling the comparison signal; adjusting a numerical value as a function of the result of the comparison and of the numerical value; and converting the current numerical value into a voltage corresponding to the reference voltage. | 05-24-2012 |
| 20120126094 | ANALOG TO DIGITAL RAMP CONVERTER - A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal. | 05-24-2012 |
| 20120112873 | VIALESS INTEGRATION FOR DUAL THIN FILMS - THIN FILM RESISTOR AND HEATER - A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films. | 05-10-2012 |
| 20120104454 | OPTICAL DEVICE, PROCESS FOR FABRICATING IT AND AN ELECTRONIC PACKAGE COMPRISING THIS OPTICAL DEVICE - An optical device includes at least one optical die ( | 05-03-2012 |
| 20120098684 | Device and Method for Processing an Analogue Signal - Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset. | 04-26-2012 |
| 20120092459 | METHOD AND DEVICE FOR RECONSTRUCTION OF A THREE-DIMENSIONAL IMAGE FROM TWO-DIMENSIONAL IMAGES - The disclosure relates to a method for reconstruction of a three-dimensional image of an object. A first image is acquired of the object lit by a luminous flux having, in a region including the object, a luminous intensity dependant on the distance, with a light source emitting the luminous flux. A second image is acquired of the object lit by a luminous flux having, in a region including the object, a constant luminous intensity. For each pixel of a three-dimensional image, a relative distance of a point of the object is determined as a function of the intensity of a pixel corresponding to the point of the object in each of the acquired images. | 04-19-2012 |
| 20120092358 | Noise-robust edge enhancement system and method for improved image sharpness - A system for edge enhancement includes an input unit to receive an input signal Yin, a vertical enhancement unit to perform a vertical enhancement of an edge of the input signal Yin to generate an output YEV, and a horizontal enhancement unit to perform a horizontal enhancement of the edge of the input signal Yin to generate an output YEH. The system also includes a local gradient analysis unit to generate a local gradient direction GradDir and a local gradient magnitude GradMag based at least partly upon the input signal Yin, and a mixer to generate an output Yout by mixing the output YEV with the output YEH using the local gradient direction GradDir. The system further includes an output unit to output the output Yout. | 04-19-2012 |
| 20120092071 | CLASS-AB OUTPUT STAGE - An output stage of a class-AB amplifier, including: a first transistor of a first channel type between a first terminal of application of a first voltage and an output terminal of the stage, having its gate connected to a first input terminal of the stage; a first transistor of a second channel type between this output terminal and a second terminal of application of the first voltage, having its gate connected to a second input terminal of the stage; and second and third transistors of the second channel type between the output terminal and the first transistor of the second channel type, the gate of the second transistor being connected to the midpoint of a resistive dividing bridge between said output terminal and the gate of the third transistor of the second channel type, and the gate of the third transistor being biased to a fixed voltage. | 04-19-2012 |
| 20120081137 | TESTING METHOD FOR SEMICONDUCTOR INTEGRATED ELECTRONIC DEVICES AND CORRESPONDING TEST ARCHITECTURE - A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method. | 04-05-2012 |
| 20120079154 | TRANSACTION REORDERING ARRANGEMENT - An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued. | 03-29-2012 |
| 20120079148 | REORDERING ARRANGEMENT - An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are configured to provide respective responses to respective requests. The network-on-chip further includes an interconnect for routing said requests and respective responses to said requests to and from the plurality of sources and at least one transaction reordering arrangement. The transaction reordering arrangement is configured to reorder said responses such that said responses are provided to a respective source in an order which corresponds to an order in which the requests are issued by said respective source. A respective transaction reordering arrangement is associated with a respective source. | 03-29-2012 |
| 20120061849 | SEMICONDUCTOR COMPONENT AND DEVICE PROVIDED WITH HEAT DISSIPATION MEANS - A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components. | 03-15-2012 |
| 20120033806 | METHOD OF ENCRYPTING A DATA STREAM - The disclosure relates to a method of encrypting or of decrypting a binary data stream by generating a binary encryption stream and combining by a reversible logic operation each bit of the binary data stream with a bit of the binary encryption stream, the generation of the binary encryption stream including generating an input block by applying a cryptographic function using a secret key to a data block, and generating the binary encryption stream from the input block by combining the bits of the input block with each other by logic operations in a manner so as to prevent the input block from being determined from the binary encryption stream. | 02-09-2012 |
| 20120021606 | PROCESS FOR PRODUCING TWO INTERLEAVED PATTERNS ON A SUBSTRATE - A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern. | 01-26-2012 |
| 20120012736 | Image Sensor - Image sensor, comprising a matrix of active pixels having several columns for delivering at least one information signal of an active pixel, the sensor comprising means for processing the information signals delivered by the said active pixels which comprise at least one amplification stage biased by a current source, the processing means comprising a device for voltage-limiting the signal delivered on an output terminal of the said at least one amplification stage comprising an input terminal connected to the output terminal, a first transistor connected between the input terminal and a reference terminal connected to a reference power supply source, a gain device comprising an input connected to the input terminal, an output connected to the gate of the first transistor and configured so as to decrease the voltage span necessary to cause the first transistor to toggle from its off state to a state in which it absorbs the current provided by the said current source. | 01-19-2012 |
| 20120007663 | INTEGRATED CIRCUIT WITH DEVICE FOR ADJUSTMENT OF THE OPERATING PARAMETER VALUE OF AN ELECTRONIC CIRCUIT AND WITH THE SAME ELECTRONIC CIRCUIT - An integrated circuit includes an electronic circuit and a device for adjustment of the operating parameter value of the electronic circuit. The electronic circuit comprises a resistive stage. The device comprises a first circuit portion adapted to adjust said operating parameter when the device is active and the electronic circuit is inactive, and adapted to be inactive when the electronic circuit is active, and a second circuit portion adapted to determine the active or inactive state of the device in response to the value of an external control signal. The integrated circuit comprises a first external terminal for the connection to ground, a second external terminal for inputting said control signal, a further external terminal for inputting a further external signal and a deactivation circuit driven by said further external signal to deactivate the electronic circuit when the device is active. | 01-12-2012 |
| 20120001904 | METHOD OF PROCESSING 3D IMAGES, AND CORRESPONDING SYSTEM - The method is for processing a multiplex image, the multiplex including at least one first view intended to be viewed by a first eye of an observer and at least one second view intended to be viewed by a second eye of the observer. The two views are spatially sub-sampled according to complementary grids and mutually spatially shifted. The method includes a demultiplexing of the multiplex image so as to extract the first and the second views. And, for at least one missing pixel of the first view, there is a determination of a first window of the first view containing the location of the missing pixel and representing a first detail in the first view, a determination of a second window of the second view representing the same first detail in the second view, and a formulation of the missing pixel by using the pixels of the second window. | 01-05-2012 |
| 20120001668 | DIE AND A PACKAGE COMPRISING A PLURALITY OF DIES - A first die includes a controller configured to select at least one task to be performed by the first die and signal circuitry configured in response to the selection of the at least one task to provide a signal to be sent to a second die for initiating performance of at least one task on the second die which corresponds to (and is to be performed in a time coordinated manner with) the at least one task on the first die. The first die has task circuitry configured to perform the task in response to generation of the signal, and the second die has task circuitry configured to perform the corresponding task in response to receipt of the signal. | 01-05-2012 |
| 20110320669 | COMMUNICATION SYSTEM AND METHOD - A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted. | 12-29-2011 |
| 20110305390 | METHOD AND DEVICE FOR PROCESSING A DIGITAL IMAGE - A digital image including a plurality of pixels is processed. Each pixel has at least one colorimetric component. The processing of the image includes processing for each pixel of a group of pixels of the image and for each colorimetric component of the pixel. In this processing, a modification is made to the value of the colorimetric component so as to obtain a modified value situated inside or outside a colorimetric range. A comparison is made of the modified value to the upper and lower limits of the associated colorimetric range. If the corrected value is outside the associated colorimetric range, a corrected value equal to an additional value is assigned to the corresponding colorimetric component of the pixel. The additional value is chosen to be unique and included in the associated colorimetric range and different from the values of the limits of the associated colorimetric range. | 12-15-2011 |
| 20110302471 | CIRCUITRY FOR BUILT-IN SELF-TEST - A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested. | 12-08-2011 |
| 20110299783 | Object Detection in an Image - The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions ( | 12-08-2011 |
| 20110299581 | BUILT-IN SELF-TEST CIRCUITRY - A method of generating at least one test sequence for testing a data connection, the method involving selectively combining by a logic function ( | 12-08-2011 |
| 20110289253 | INTERCONNECTION METHOD AND DEVICE, FOR EXAMPLE FOR SYSTEMS-ON-CHIP - Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue. | 11-24-2011 |
| 20110286383 | Demodulator for High Bit Rate Transmission and Corresponding Demodulation Method - Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames. | 11-24-2011 |
| 20110278733 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE COMPRISING A CHIP WITH THROUGH-VIAS - A semiconductor device includes a first wafer having at least one first integrated-circuit chip and a first support layer surrounding the first integrated circuit chip. A first electrical-connection layer is placed on a frontside of the first wafer and includes a first electrical-connection network. A second wafer is placed on a frontside of the first electrical-connection layer. The second wafer includes at least one second integrated-circuit chip and a second support layer surrounding the second integrate circuit chip. The second integrated circuit chip has an active side facing the first electrical-connection layer, and one or more through-holes filled with a conductor forming electrical-connection vias. A second electrical-connection layer is placed on the backside of the second wafer and includes a second electrical-connection network. | 11-17-2011 |
| 20110225400 | Device for Testing a Multitasking Computation Architecture and Corresponding Test Method - A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation architecture. The execution of the instruction sequences is controlled so that the sequences are alternately executed within the computation architecture. | 09-15-2011 |
| 20110213944 | SYNCHRONIZATION SYSTEM AND RELATED INTEGRATED CIRCUIT - A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency. | 09-01-2011 |
| 20110199149 | METHOD AND DEVICE FOR DRIVING THE FREQUENCY OF A CLOCK SIGNAL OF AN INTEGRATED CIRCUIT - An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases. | 08-18-2011 |
| 20110167316 | METHOD AND DEVICE FOR ROW AND COLUMN INTERLEAVING OF BLOCKS OF VARIABLE SIZE - The present disclosure relates to a method for interleaving a stream of input data blocks, the method comprising steps of: subdividing a block into sub-blocks of fixed size in number of data rows and data columns, the sub-blocks being distributed in the block in rows of sub-blocks and in columns of sub-blocks, transferring the data contained in the block into a first memory, while respecting the order of the data in the input stream, transferring the data contained in the block by row of sub-blocks, into a second memory in which the data of each sub-block is accessible from the address of the sub-block, transferring the data of each sub-block by column of sub-blocks, from the second memory into a third memory, by putting back the data of each sub-block in data rows and columns, and transferring the data by data column from the third memory into an output stream. | 07-07-2011 |
| 20110164831 | METHOD FOR DETECTING ORIENTATION OF CONTOURS - A method for detecting orientation of the contours in an image, performs an initial transformation of the image using a non-decimated multi-resolution transform, segments the image into a plurality of blocks, determines the optimal resolution for each block, and detects the predominant direction of contour for each of the blocks. | 07-07-2011 |
| 20110160912 | METHOD AND SYSTEM FOR CONTROLLING ELECTRICAL MACHINES - An embodiment is a method, and related system, to implement the square root extraction operation, which grants a 32 bits precision, which has high execution speed and is able to process a decimal radicand. An embodiment relates to a method for controlling an electric machine, comprising the detection of the value of at least one electrical quantity characterizing the machine operation and processing the detected value of said electrical quantity. The control method controls the machine operation on the basis of this processing. In particular the processing of the detected value of the electrical quantity comprises calculating a square root of a radicand value related to the detected value of electrical quantities. The calculation of the square root includes: calculating an approximated value of the square root, having a first precision, and then calculating a corrective value and combining said approximated value with said corrective value to obtain a square root value having a second precision greater than the first precision. | 06-30-2011 |
| 20110148533 | CRYSTAL OSCILLATOR WITH FAST START-UP AND LOW CURRENT CONSUMPTION - An oscillator comprises an inverter, with a resonator connected between an input and an output of the inverter. A transistor external to the inverter is connected in a current mirror mode with a transistor of the inverter so that the inverter's transistor copies the current of the external transistor. The external transistor has its drain terminal connected to the gate terminals of the inverter's transistor and of the external transistor. A current source is connected to the gate terminal of the inverter's transistor, and a switch is connected between the drain and gate terminals of the external transistor. Circuitry controls the switch so as to open the connection between the drain and gate terminals of the external transistor at the beginning of a start-up phase of the oscillator. | 06-23-2011 |
| 20110141805 | METHOD OF PROGRAMMING AN ELECTRICALLY PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY POINT, AND CORRESPONDING MEMORY DEVICE - An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line. | 06-16-2011 |
| 20110141078 | AMBIENT LIGHT DETECTION - Ambient light is detected by a photodiode circuit by measuring the time taken for a digital output of the photodiode circuit to change state in response to exposure of a photodiode of the photodiode circuit to that ambient light. A nominal time for state change is calculated based on photodiode circuit characteristics. Furthermore, an effective time for the photodiode circuit digital output to change state is determined in a calibration mode where the photodiode has been disconnected and a reference current is applied to the circuit. An illumination value of the detected ambient light is then calculated as a function of: the measured time, the effective time and the nominal time. | 06-16-2011 |
| 20110125437 | METHOD AND DEVICE FOR ANALYZING THE BEHAVIOR OF A POWER SUPPLY IN A CIRCUIT - A method for testing an integrated circuit, comprising performing a series of at least three tests, each comprising: selecting two nodes among at least three nodes for taking a clock signal from an integrated circuit, taking two clock signals at the two selected taking nodes during a test duration, detecting and counting events appearing in a jitter signal between the two clock signals taken, during the test duration, and determining from numbers of events counted a test result proportional to a sum of jitter variances of the two clock signals taken, and at the end of the series of tests, determining by a matrix calculation the jitter variance of each clock signal taken. | 05-26-2011 |
| 20110116773 | METHOD AND DEVICE FOR CONTROLLING PLAYING SPEED OF A COMPRESSED DIGITAL VIDEO SEQUENCE (TRICKMODE) - A method of playing a compressed digital video sequence, comprising steps comprising attributing to each frame a display duration determined as a function of a playing speed set point, and at each period of a frame synchronization signal: if a display duration cumulative value is equal to or greater than a threshold value corresponding to the period of the synchronization signal, playing a previously acquired decoded frame and decreasing the cumulative value of the threshold value; and if the present cumulative value is less than the threshold value, acquiring a new decoded frame and adding the display duration attributed to the newly acquired frame to the cumulative value, until the cumulative value is equal to or greater than the threshold value, playing a last decoded frame acquired and decreasing the cumulative value of the threshold value. | 05-19-2011 |
| 20110096876 | METHOD AND DEVICE FOR DETECTING A PHASE ERROR OF A SIGNAL - A method for receiving a signal having a succession of symbols, transmitted by a digital modulation, each symbol transmitted having a phase and an amplitude belonging to a set of values in finite number, the method includes evaluating a phase error (PHE) on a received symbol (S), resulting from a signal transmission noise, correcting the phase of the received symbol according to the phase error evaluated, demodulating the symbol corrected in phase, and modeling the transmission noise by a Gaussian component not correlated with the signal received and defined by a power and an interference component defined by an amplitude and which phase is substantially uniformly distributed, the phase error of the received symbol evaluated on the basis of the power of Gaussian component and the amplitude of the interference component. | 04-28-2011 |
| 20110018135 | METHOD OF ELECTRICALLY CONNECTING A WIRE TO A PAD OF AN INTEGRATED CIRCUIT CHIP AND ELECTRONIC DEVICE - A wire is electrically connected to an electrical bonding pad of an integrated circuit chip and electronic device through an intermediate electrical interconnect block that is interposed between the electrical bonding pad and one end of the electrical lead wire. | 01-27-2011 |
| 20100325318 | DATA STREAM FLOW CONTROLLER AND COMPUTING SYSTEM ARCHITECTURE COMPRISING SUCH A FLOW CONTROLLER - A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters. | 12-23-2010 |
| 20100321082 | METHOD AND DEVICE FOR CONTROLLING A COMMON-MODE VOLTAGE OF A SWITCHED-CAPACITOR SYSTEM, IN PARTICULAR AN ANALOG-TO-DIGITAL CONVERTER - The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path. | 12-23-2010 |
| 20100308904 | DEVICE FOR GENERATING A REFERENCE VOLTAGE DESIGNED FOR A SYSTEM OF THE SWITCHED-CAPACITOR TYPE - The device generates a reference voltage, in particular designed for a system of the switched-capacitor type, based on a setpoint voltage. It includes a regulation loop having a first input to receive the setpoint voltage, and an output stage arranged as a voltage follower and looped to a second input of the loop. An additional stage is configured to deliver the reference voltage to the switched-capacitor system, this additional stage, coupled to the output stage, also being arranged as a voltage follower and paired with the output stage. | 12-09-2010 |
| 20100289472 | LOW DROPOUT VOLTAGE REGULATOR WITH LOW QUIESCENT CURRENT - The disclosure relates to a low dropout voltage regulator comprising a regulation transistor to supply an output voltage from an input voltage, a gate control stage to supply a gate voltage to the regulation transistor, and an error amplifier to supply a control voltage to a control terminal of a control transistor. The low dropout voltage regulator also comprises a quiescent current control circuit to limit a quiescent current flowing through the gate control stage when the input voltage approaches the output voltage and causes the regulation transistor to enter into an ohmic conduction mode. The quiescent current control circuit comprises a current source providing a reference current and is configured to control the quiescent current by current-mirror effect based upon the reference current. | 11-18-2010 |
| 20100272292 | METHOD AND DEVICE FOR CONTROLLING THE BROADCASTING OF AUDIO CONTENTS BY TWO LOUDSPEAKERS - The broadcasting of audio contents by two loudspeakers is controlled by delivering a first audio content to the two loudspeakers and a further processing in which an auxiliary audio content is received. A second audio content is formed by temporally delaying the auxiliary audio content with a delay dependent on the spacing between the loudspeakers and on a distance between a first loudspeaker and a spot located in front of this first loudspeaker. The second audio content is delivered to the first loudspeaker. A third audio content is formed by inverting the auxiliary audio content. The third audio content is then delivered to the second loudspeaker. | 10-28-2010 |
| 20100253429 | METHOD FOR MEASURING THE SATURATION RATE OF AN AUDIO AMPLIFIER - A method and corresponding circuit that adjusts the gain of an audio output stage having a class D amplifier, this method including the steps of setting the gain to a nominal value, analyzing an output signal during successive clock periods, counting the number of clock periods during which the signal is in a state corresponding to a saturation, decreasing the gain if the number reaches, before the end of a first time interval, a value corresponding to a first percentage, maintaining the gain constant if, at the end of a second time interval, different from the first interval, the number corresponds to a second percentage being comprised between the first percentage and a third percentage, and increasing the gain if, at the end of the second time interval, the number corresponds to a fourth percentage, lower than the third percentage. | 10-07-2010 |
| 20100244229 | SEMICONDUCTOR PACKAGE FABRICATION PROCESS AND SEMICONDUCTOR PACKAGE - A substrate is provided with electrical connection pads on a front face and on a rear face, the front pads and rear pads being selectively connected via a network passing through the substrate. A peripheral edge of the substrate is mounted on a rigid annular frame and the rearm face secured to a suction table. A layer of a dielectric sealant containing electrically conductive particles is deposited on the front face and front pads of the substrate. Integrated-circuit chips are positioned on the front face to flatten the layer of dielectric sealant, the included electrically conductive particles making electrical connection between pads of the integrated-circuit and the front pads of the substrate. The resulting assembly in then encapsulated in a block of encapsulating material positioned on top of the front face of the substrate. The block is then diced in order to obtain a plurality of semiconductor packages. | 09-30-2010 |
| 20100225509 | ANALOG-DIGITAL CONVERTER WITH PIPELINE ARCHITECTURE ASSOCIATED WITH A PROGRAMMABLE GAIN AMPLIFIER - A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold. | 09-09-2010 |
| 20100176845 | METHOD FOR DETECTING THE LOCKING OF A PHASE-LOCKED LOOP AND ASSOCIATED DEVICE - A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected. | 07-15-2010 |
| 20100157035 | ANALOG-TO-DIGITAL CONVERSION IN IMAGE SENSORS - An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear. | 06-24-2010 |
