STMicroelectronics (Canada) Inc.
|STMicroelectronics (Canada) Inc. Patent applications|
|Patent application number||Title||Published|
|20130128111||HIGH-QUALITY SINGLE-FRAME SUPERRESOLUTION TRAINING AND RECONSTRUCTION ENGINE - An image processing system includes an image reconstruction unit. The image reconstruction unit is configured to receive an image at a first resolution, apply the image to a look-up table and output a version of the image at a second resolution. The second resolution includes a higher resolution than the first resolution. In addition, the look-up table is generated inputting a plurality of training images; classifying, into a number of classes, a plurality of images patches corresponding to each of the plurality of training images; re-classifying the number of classes into a final class; and synthesizing filters corresponding to each of the class into a final filter value.||05-23-2013|
|20130027513||Apparatus and Method for Adjusting the Perceived Depth of 3D Visual Content - A system for adjusting the perceived depth of 3D content in response to a viewer input control signal. The system comprises: 1) a content source providing an input left stereoscopic image and an input right stereoscopic image; 2) a disparity estimator to receive the input left and right stereoscopic images, detect disparities between the input left and right stereoscopic images, and generate a disparities array; and 3) processing circuitry to fill in occlusion areas associated with the disparities array and apply a scale factor to the detected disparities to thereby generate a scaled disparities array. The system further comprises a warping engine to receive the scaled disparities array and generate an output left stereoscopic image and an output right stereoscopic image. The output left and right stereoscopic images have a different perceived depth than the input left and right stereoscopic images.||01-31-2013|
|20120269305||BANG-BANG OFFSET CANCELLATION (AUTOZERO) - A receive channel offset correction scheme utilizes “eye edge” samplers and demultiplexers already present and essential for operation of the CDR algorithm, and adds only simple word-rate logic, with no new analog circuitry. The result is the ability to precisely determine the offset polarity as well as to get an approximate immediate measure of the offset magnitude. The offset detected includes all of the analog circuitry in the channel, including the samplers themselves.||10-25-2012|
|20120269255||Parallel Closed-Loop DFE Filter Architecture - A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.||10-25-2012|
|20120268177||FRACTIONAL DIVIDER FOR AVOIDANCE OF LC-VCO INTERFERENCE AND JITTER - A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.||10-25-2012|
|20120170691||INTERFERENCE CANCELLATION AND IMPROVED SIGNAL-TO-NOISE RATIO CIRCUITS, SYSTEMS, AND METHODS - Interference cancellation for wideband and narrowband communications systems is provided without apriori knowledge of statistical information about an interfering signal. In one embodiment a demodulator circuit can operate in an environment where a “no lock” situation would normally occur to remove the interference and acquire signals in low signal-to-noise ratio (SNR) conditions and high signal-to-interference ration (SIR) conditions. In other embodiments, performance is improved by introducing statistics of the interfering signal, and these statistics regarding the communications channel and interference properties (i.e., characteristics of the interfering signal) can be adaptive or “learned” in other embodiments.||07-05-2012|
|20120166505||S12 TX FIR ARCHITECTURE - A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.||06-28-2012|
|20120161827||CENTRAL LC PLL WITH INJECTION LOCKED RING PLL OR DELL PER LANE - A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.||06-28-2012|
|20120139771||DIFFERENTIAL SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.||06-07-2012|
|20080272418||Semiconductor component comprising a buried mirror - A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.||11-06-2008|
Patent applications by STMicroelectronics (Canada) Inc.