STATS CHIPPAC, LTD. Patent applications |
Patent application number | Title | Published |
20160141238 | Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLB-MLP) - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation. | 05-19-2016 |
20160118333 | Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield - A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure. | 04-28-2016 |
20160118332 | Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High Yield - A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line. | 04-28-2016 |
20160111410 | Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect - A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame. | 04-21-2016 |
20160104731 | Semiconductor Device and Method of Forming EWLB Semiconductor Package with Vertical Interconnect Structure and Cavity Region - A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias. | 04-14-2016 |
20160104681 | Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die - A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated. | 04-14-2016 |
20160071813 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow. | 03-10-2016 |
20160043047 | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package - A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package. | 02-11-2016 |
20150357274 | Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconnect Using TSV and TMV - A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV. | 12-10-2015 |
20150348936 | Semiconductor Device and Method of Forming Electromagnetic (EM) Shielding for LC Circuits - A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure. The modular interconnect structure includes a height less than a height of the first component. | 12-03-2015 |
20150348861 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE LAYER OVER INSULATING LAYER FOR BONDING CARRIER TO MIXED SURFACES OF SEMICONDUCTOR DIE AND ENCAPSULANT - A semiconductor device has a semiconductor die disposed over the substrate. A conductive via is formed partially through the substrate. An encapsulant is deposited over the semiconductor die and substrate. An insulating layer is formed over the semiconductor die and encapsulant. The insulating layer includes an organic or inorganic insulating material. An adhesive layer is deposited over the insulating layer. The adhesive layer contacts only the insulating layer. A carrier is bonded to the adhesive layer. The insulating layer provides a single CTE across the entire bonding interface between the adhesive layer and semiconductor die and encapsulant. The constant CTE of the insulating layer reduces stress across the bonding interface. A portion of the substrate is removed by backgrinding to expose the conductive via. An insulating layer is formed over the substrate around the conductive via. An interconnect structure is formed over the conductive via. | 12-03-2015 |
20150325553 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP - A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer. | 11-12-2015 |
20150311172 | Semiconductor Device and Method of Forming Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than | 10-29-2015 |
20150294962 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure. | 10-15-2015 |
20150287708 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure. | 10-08-2015 |
20150279815 | Semiconductor Device and Method of Forming Substrate Having Conductive Columns - A semiconductor device has a first conductive layer disposed over a carrier. A second conductive layer is formed over a first surface of the first conductive layer. A first insulating layer is formed over the first and second conductive layers. A third conductive layer is formed over the first insulating layer. A second insulating layer is formed over the third conductive layer. The carrier is removed to expose the first conductive layer. A portion of the first conductive layer is removed from a second surface of the first conductive layer opposite the first surface to form a plurality of conductive pillars. The conductive pillars include a height of 100 micrometers or greater. The portion of the first conductive layer is removed using an etching process. The conductive pillars are disposed over a first semiconductor package. A semiconductor die or second semiconductor package is disposed over the second conductive layer. | 10-01-2015 |
20150279778 | Semiconductor Device and Method of Forming RDL and Vertical Interconnect by Laser Direct Structuring - A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. An insulating layer is formed over the semiconductor die and encapsulant. A first channel including a first conductive surface is formed in the insulating layer by laser radiation. A laser-activated catalyst is infused in the insulating layer to form the first conductive surface in the first channel upon laser radiation. A vertical interconnect is formed through the encapsulant. A first conductive layer is formed in the first channel over the first conductive surface. A second channel including a second conductive surface is formed in the encapsulant by laser radiation. The catalyst is infused in the encapsulant to form the second conductive surface in the second channel upon laser radiation. A second conductive layer is formed in the second channel over the second conductive surface. An interconnect structure is formed over the first conductive layer. | 10-01-2015 |
20150270237 | Semiconductor Device and Method of Forming 3D Dual Side Die Embedded Build-Up Semiconductor Package - A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure. | 09-24-2015 |
20150262977 | Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure - A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die. | 09-17-2015 |
20150259194 | Semiconductor Device and Method of Forming Microelectromechanical Systems (MEMS) Package - A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure. | 09-17-2015 |
20150249065 | Semiconductor Device and Method of Forming WLP With Semiconductor Die Embedded Within Penetrable Encapsulant Between TSV Interposers - A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate. | 09-03-2015 |
20150243575 | Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP) - A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die. | 08-27-2015 |
20150228628 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation - A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer. | 08-13-2015 |
20150228590 | Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die - A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer. | 08-13-2015 |
20150228552 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 08-13-2015 |
20150214182 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate. | 07-30-2015 |
20150179616 | Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate - A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. | 06-25-2015 |
20150179587 | Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure - A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar. | 06-25-2015 |
20150179570 | Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package - A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit. | 06-25-2015 |
20150179544 | Semiconductor Device and Method of Wafer Thinning Involving Edge Trimming and CMP - A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects. | 06-25-2015 |
20150179481 | Semiconductor Device and Method of Making Embedded Wafer Level Chip Scale Packages - A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die. A composite layer is formed over the encapsulant to form a panel. The carrier is removed. A conductive layer is formed over the panel. An insulating layer is formed over the conductive layer. The carrier includes a glass layer, a second composite layer formed over the glass layer, and an interface layer formed over the glass layer. The composite layer and encapsulant are selected to tune a coefficient of thermal expansion of the panel. The panel includes panel blocks comprising an opening separating the panel blocks. The encapsulant or insulating material is deposited in the opening. A plurality of support members are disposed around the panel blocks. An interconnect structure is formed over the conductive layer. | 06-25-2015 |
20150155248 | Semiconductor Device and Method of Forming Repassivation Layer for Robust Low Cost Fan-Out Semiconductor Package - A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metalization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 μm larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief. | 06-04-2015 |
20150145128 | Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die - A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant. | 05-28-2015 |
20150145126 | Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP - A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer. | 05-28-2015 |
20150140736 | Semiconductor Device and Method of Forming Wire Bondable Fan-Out EWLB Package - A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire. | 05-21-2015 |
20150137334 | Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die Disposed in a Cavity of an Interconnect Structure and Grounded Through the Die TSV - A semiconductor device has an interconnect structure with a cavity formed partially through the interconnect structure. A first semiconductor die is mounted in the cavity. A first TSV is formed through the first semiconductor die. An adhesive layer is deposited over the interconnect structure and first semiconductor die. A shielding layer is mounted over the first semiconductor die. The shielding layer is secured to the first semiconductor die with the adhesive layer and grounded through the first TSV and interconnect structure to block electromagnetic interference. A second semiconductor die is mounted to the shielding layer and electrically connected to the interconnect structure. A second TSV is formed through the second semiconductor die. An encapsulant is deposited over the shielding layer, second semiconductor die, and interconnect structure. A slot is formed through the shielding layer for the encapsulant to flow into the cavity and cover the first semiconductor die. | 05-21-2015 |
20150137322 | Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die - A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections. | 05-21-2015 |
20150123273 | Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die. | 05-07-2015 |
20150115394 | Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers. | 04-30-2015 |
20150097295 | Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent. | 04-09-2015 |
20150091165 | Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration - A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer. | 04-02-2015 |
20150091145 | Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP - A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure. | 04-02-2015 |
20150084213 | Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer - A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced. | 03-26-2015 |
20150084206 | Semiconductor Device and Method of Forming Dual Fan-Out Semiconductor Package - A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant. A plurality of conductive vias is disposed in the first encapsulant and/or the second encapsulant. | 03-26-2015 |
20150061124 | Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer. | 03-05-2015 |
20150061123 | Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation - A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer. | 03-05-2015 |
20150054167 | Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die - A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 02-26-2015 |
20150054151 | Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure - A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure. | 02-26-2015 |
20150028496 | Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure - A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die. | 01-29-2015 |
20150028471 | Semiconductor Device and Method of Forming Through Mold Hole with Alignment and Dimension Control - A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array. | 01-29-2015 |
20150021754 | Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management - A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader. | 01-22-2015 |
20150008597 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 01-08-2015 |
20140361423 | Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die - A semiconductor device has a leadframe with a plurality of bodies extending from the base plate. A first semiconductor die is mounted to the base plate of the leadframe between the bodies. An encapsulant is deposited over the first semiconductor die and base plate and around the bodies of the leadframe. A portion of the encapsulant over the bodies of the leadframe is removed to form first openings in the encapsulant that expose the bodies. An interconnect structure is formed over the encapsulant and extending into the first openings to the bodies of the leadframe. The leadframe and bodies are removed to form second openings in the encapsulant corresponding to space previously occupied by the bodies to expose the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with bumps extending into the second openings of the encapsulant to electrically connect to the interconnect structure. | 12-11-2014 |
20140353846 | Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant - A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. | 12-04-2014 |
20140327145 | Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect - A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame. | 11-06-2014 |
20140319695 | Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures - A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer. | 10-30-2014 |
20140300002 | Semiconductor Device and Method of Forming Conductive Vias Using Backside Via Reveal and Selective Passivation - A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via. | 10-09-2014 |
20140295618 | Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding - Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package. | 10-02-2014 |
20140284788 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS - A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die. | 09-25-2014 |
20140269810 | Semiconductor Device and Method of Calibrating Warpage Testing System to Accurately Measure Semiconductor Package Warpage - A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile. | 09-18-2014 |
20140264905 | Semiconductor Device and Method of Forming WLCSP with Semiconductor Die Embedded within Interconnect Structure - A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer. | 09-18-2014 |
20140264851 | Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias. | 09-18-2014 |
20140264850 | Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections - A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump. | 09-18-2014 |
20140264817 | Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package - A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die. | 09-18-2014 |
20140264786 | Semiconductor Device Including RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect - A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL. | 09-18-2014 |
20140264736 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 09-18-2014 |
20140252654 | Semiconductor Device and Method of Forming Repassivation Layer with Reduced Opening to Contact Pad of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer. | 09-11-2014 |
20140252641 | Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package - A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film. | 09-11-2014 |
20140252631 | Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die - A semiconductor wafer contains a plurality of semiconductor die each having a plurality of contact pads. A sacrificial adhesive is deposited over the contact pads. Alternatively, the sacrificial adhesive is deposited over the carrier. An underfill material can be formed between the contact pads. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier such that the sacrificial adhesive is disposed between the contact pads and temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and sacrificial adhesive is removed to leave a via over the contact pads. An interconnect structure is formed over the encapsulant. The interconnect structure includes a conductive layer which extends into the via for electrical connection to the contact pads. The semiconductor die is offset from the interconnect structure by a height of the sacrificial adhesive. | 09-11-2014 |
20140252573 | Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB - A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to V | 09-11-2014 |
20140246779 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over the Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 09-04-2014 |
20140239509 | Semiconductor Device and Method of Forming Topside and Bottom-side Interconnect Structures Around Core Die with TSV - A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV. | 08-28-2014 |
20140239496 | Semiconductor Device and Method of Forming Micro-Vias Partially Through Insulating Material Over Bump Interconnect Conductive Layer for Stress Relief - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief. | 08-28-2014 |
20140239495 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed. | 08-28-2014 |
20140231989 | Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump. | 08-21-2014 |
20140217609 | Semiconductor Device and Method of Forming Conductive Vias with Trench in Saw Street - A semiconductor wafer has a plurality of semiconductor die separated by a peripheral region. A trench is formed in the peripheral region of the wafer. A via is formed on the die. The trench extends to and is continuous with the via. A first conductive layer is deposited in the trench and via to form conductive TSV. The first conductive layer is conformally applied or completely fills the trench and via. The trench has a larger area than the vias which accelerates formation of the first conductive layer. A second conductive layer is deposited over a front surface of the die. The second conductive layer is electrically connected to the first conductive layer. The first and second conductive layers can be formed simultaneously. A portion of a back surface of the wafer is removed to expose the first conductive layer. The die can be electrically interconnected through the TSVs. | 08-07-2014 |
20140217597 | Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package - A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias. | 08-07-2014 |
20140203443 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 07-24-2014 |
20140199838 | Semiconductor Device and Method of Forming Through-Silicon-Via with Sacrificial Layer - A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via. | 07-17-2014 |
20140197540 | Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad. | 07-17-2014 |
20140183761 | Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages - A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less. | 07-03-2014 |
20140183718 | Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale Packages - A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die. | 07-03-2014 |
20140175661 | Semiconductor Device and Method of Making Bumpless Flipchip Interconnect Structures - A semiconductor device includes a substrate with contact pads. A mask is disposed over the substrate. Aluminum-wettable conductive paste is printed over the contact pads of the substrate. A semiconductor die is disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure over the contact pads of the substrate. The contact pads include aluminum. Contact pads of the semiconductor die are disposed over the aluminum-wettable conductive paste. The aluminum-wettable conductive paste is reflowed to form an interconnect structure between the contact pads of the semiconductor die and the contact pads of the substrate. The interconnect structure is formed directly on the contact pads of the substrate and semiconductor die. The contact pads of the semiconductor die are etched prior to reflowing the aluminum-wettable conductive paste. An epoxy pre-dot to maintain a separation between the semiconductor die and substrate. | 06-26-2014 |
20140175642 | Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 06-26-2014 |
20140175640 | Semiconductor Device and Method of Bonding Semiconductor Die to Substrate in Reconstituted Wafer Form - A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate. | 06-26-2014 |
20140175639 | Semiconductor Device and Method of Simultaneous Molding and Thermalcompression Bonding - A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold. An encapsulant is deposited over and between the semiconductor die and substrate simultaneous with bonding the semiconductor die to the substrate in the chase mold. The semiconductor die is bonded to the substrate using thermocompression by application of force and elevated temperature. An electrical interconnect structure, such as a bump, pillar bump, or stud bump, is formed over the semiconductor die. A flux material is deposited over the interconnect structure. A solder paste or SOP is deposited over a conductive layer of the substrate. The flux material and SOP provide temporary bond between the semiconductor die and substrate. The interconnect structure is bonded to the SOP. Alternatively, the interconnect structure can be bonded directly to the conductive layer of the substrate, with or without the flux material. | 06-26-2014 |
20140175623 | Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die - A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path. | 06-26-2014 |
20140159251 | Semiconductor Device and Method of Forming Low Profile Fan-Out Package with Vertical Interconnection Units - A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure. A plurality of vias is formed through the insulating layer and into the first interconnect structure with the second interconnect structure disposed within the vias. | 06-12-2014 |
20140159236 | Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating - An interconnect structure for a semiconductor device is made by forming a contact pad on a substrate, forming an under bump metallization layer over the contact pad, forming a photoresist layer over the substrate, removing a portion of the photoresist layer to form an opening which exposes the UBM, depositing a first conductive material into the opening of the photoresist, removing the photoresist layer, depositing a second conductive material over the first conductive material, and coating the second conductive material with an organic solderability preservative. The interconnect structure is formed without solder reflow. The first conductive layer is nickel and the second conductive layer is copper. The organic solderability preservative is made with benzotriazole, rosin, rosin esters, benzimidazole compounds, or imidazole compounds. The interconnect structure decreases the pitch between the core pillars in the interconnect array and increases the density of I/O contacts on the semiconductor device. | 06-12-2014 |
20140131869 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow. | 05-15-2014 |
20140127858 | Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure. | 05-08-2014 |
20140113446 | Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch - A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate. | 04-24-2014 |
20140110861 | Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer. | 04-24-2014 |
20140110860 | Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable. | 04-24-2014 |
20140103527 | Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units - A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. | 04-17-2014 |
20140103509 | Semiconductor Device and Method of Forming Conductive Ink Layer as Interconnect Structure Between Semiconductor Packages - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or LDA. A plurality of bumps is optionally formed over the semiconductor die. A bump is recessed within the opening of the encapsulant. A conductive ink is formed over the first surface of the encapsulant, bump and sidewall of the opening. The conductive ink can be applied by a printing process. An interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The interconnect structure is electrically connected to the semiconductor die. A semiconductor package is disposed over the first surface of the encapsulant with a plurality of bumps electrically connected to the conductive ink layer. The semiconductor package may contain a memory device. | 04-17-2014 |
20140103503 | Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability - A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate. | 04-17-2014 |
20140091482 | Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP - A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. | 04-03-2014 |
20140091455 | Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging - A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die. | 04-03-2014 |
20140091454 | Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale Package - A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer. | 04-03-2014 |
20140084424 | Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 03-27-2014 |
20140084415 | Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer - A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die. | 03-27-2014 |
20140077389 | Semiconductor Device and Method of Using Substrate Having Base and Conductive Posts to Form Vertical Interconnect Structure in Embedded Die Package - A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts. | 03-20-2014 |
20140077381 | Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants - A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die. | 03-20-2014 |
20140077364 | Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP - A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate. | 03-20-2014 |
20140077363 | Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in Fo-WLCSP - A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant is deposited around the semiconductor die. A first interconnect structure is formed over the semiconductor die and first encapsulant. A second encapsulant is deposited over the substrate, semiconductor die, and first interconnect structure. The second encapsulant can be formed over a portion of the semiconductor die and side surface of the substrate. A portion of the second encapsulant is removed to expose the substrate and first interconnect structure. A second interconnect structure is formed over the second encapsulant and first interconnect structure and electrically coupled to the wire studs. A discrete semiconductor device can be formed on the interconnect structure. | 03-20-2014 |
20140077362 | Semiconductor Device and Method of Forming Dual-Sided Interconnect Structures in FO-WLCSP - A semiconductor device has a substrate with first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the bumps. An encapsulant is deposited over the substrate and semiconductor die. A portion of the bumps extends out from the encapsulant. A portion of the encapsulant is removed to expose the substrate. An interconnect structure is formed over the encapsulant and semiconductor die and electrically coupled to the bumps. A portion of the substrate can be removed to expose the first or second conductive layer. A portion of the substrate can be removed to expose the bumps. The substrate can be removed and a protection layer formed over the encapsulant and semiconductor die. A semiconductor package is disposed over the substrate and electrically connected to the substrate. | 03-20-2014 |
20140077361 | Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over Carrier for Testing at Interim Stages - A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber. | 03-20-2014 |
20140077344 | Semiconductor Device with Protective Layer Over Exposed Surfaces of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die. | 03-20-2014 |
20140070427 | Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding - A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers. | 03-13-2014 |
20140070410 | Semiconductor Device and Method of Forming Multi-Layered UBM with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer - A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers. | 03-13-2014 |
20140061944 | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP - A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. | 03-06-2014 |
20140054802 | Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. | 02-27-2014 |
20140048932 | Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure - A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die. | 02-20-2014 |
20140048906 | Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters. | 02-20-2014 |
20140027929 | Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP - A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array. | 01-30-2014 |
20140011315 | Optical Semiconductor Device Having Pre-Molded Leadframe with Window and Method Therefor - A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads. | 01-09-2014 |
20140008792 | Semiconductor Device and Method of Forming Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate. | 01-09-2014 |
20140008783 | Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape - A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and contact pads of the substrate. A solder tape formed as a continuous body of solder material with a plurality of recesses is disposed between the contact pads of the semiconductor die and substrate. The solder tape is brought to a liquidus state to separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads of the semiconductor die and substrate. The contact pads on the semiconductor die and substrate can be formed with an extension or recess to increase surface area of the contact pads. | 01-09-2014 |
20140004659 | Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die | 01-02-2014 |
20140002207 | Semiconductor Device Having Balanced Band-Pass Filter Implemented with LC Resonators | 01-02-2014 |
20140001627 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation | 01-02-2014 |
20130341789 | Semiconductor Device and Method of Forming a Wafer Level Package with Top and Bottom Solder Bump Interconnection - A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps. | 12-26-2013 |
20130341784 | Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package - A semiconductor device includes a ball grid array (BGA) package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package. | 12-26-2013 |
20130328189 | Bump-on-Lead Flip Chip Interconnection - A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump. | 12-12-2013 |
20130320523 | Semiconductor Device and Method of Reflow Soldering for Conductive Column Structure in Flip Chip Package - A semiconductor device comprises a substrate and a semiconductor die. Bumps are formed over the substrate or a first surface of the semiconductor die. Conductive columns devoid of solder are formed over the substrate or the first surface of the semiconductor die. The semiconductor die is disposed over the substrate. A collet including a first cavity and a second cavity formed in a surface of the first cavity is mounted over the semiconductor die with a second surface of the semiconductor die opposite the first surface disposed within the first cavity. The bumps are reflowed. A force is applied to the collet to hold the bumps to the conductive columns while reflowing the bumps to make electrical connection to the conductive columns. The collet is removed. An underfill material is deposited between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and substrate. | 12-05-2013 |
20130320519 | Semiconductor Device and Method of Backgrinding and Singulation of Semiconductor Wafer while Reducing Kerf Shifting and Protecting Wafer Surfaces - A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer. | 12-05-2013 |
20130300004 | Semiconductor Device and Method of Controlling Warpage in Semiconductor Package - A semiconductor device has a substrate. An insulating layer is formed over a surface of the substrate. A semiconductor die is mounted over the surface of the substrate. A channel is formed in the insulating layer around the semiconductor die. An underfill material is deposited between the semiconductor die and the substrate and in the channel. A heat spreader is mounted over the semiconductor die with the heat spreader thermally connected to the substrate. A thermal interface material is formed over the semiconductor die. The underfill material is deposited between the semiconductor die and the substrate along a first edge of the semiconductor die and along a second edge of the semiconductor die opposite the first edge. The channel extends partially through the insulating layer formed over the substrate with the insulating layer maintaining coverage over the substrate within a footprint of the channel. | 11-14-2013 |
20130299995 | Semiconductor Device and Method of Depositing Underfill Material With Uniform Flow Rate - A semiconductor device has a substrate and insulating layer formed over a surface of the substrate. A first conductive layer is formed over the surface of the substrate. A second conductive layer is formed over an opposing surface of the substrate. A conductive via is formed through the substrate. An opening is formed in the insulating layer while leaving the first conductive layer intact. The opening narrows with a non-linear side or linear side. The opening can have a rectangular shape. A semiconductor die is mounted over the surface of the substrate. An underfill material is deposited between the semiconductor die and substrate. The opening in the insulating layer reduces a flow rate of the underfill material proximate to the opening. The flow rate of the underfill material proximate to the opening is substantially equal to a flow rate of the underfill material away from the opening. | 11-14-2013 |
20130277827 | Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu—OSP can be formed over the substrate. | 10-24-2013 |
20130277826 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP-ON-LEAD INTERCONNECTION - A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate. | 10-24-2013 |
20130256861 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE CIRCUITRY AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals. | 10-03-2013 |
20130249115 | Semiconductor Method and Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 09-26-2013 |
20130249111 | Semiconductor Device and Method of Forming RDL Wider than Contact Pad Along First Axis and Narrower than Contact Pad along Second Axis - A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. | 09-26-2013 |
20130249106 | Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer - A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure. | 09-26-2013 |
20130249105 | Semiconductor Device and Method of Forming Micro-Vias Partially through Insulating Material over Bump Interconnect Conductive Layer for Stress Relief - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief. | 09-26-2013 |
20130249104 | Semiconductor Device and Method of Forming Conductive Layer Over Metal Substrate for Electrical Interconnect of Semiconductor Die - A semiconductor device has a substrate with a cavity. A conductive layer is formed within the cavity and over the substrate outside the cavity. A plurality of indentations can be formed in a surface of the substrate opposite the cavity for stress relief. A first semiconductor die is mounted within the cavity. A plurality of conductive vias can be formed through the first semiconductor die. An insulating layer is disposed between the first semiconductor die and substrate with the first conductive layer embedded within the first insulating layer. An encapsulant is deposited over the first semiconductor die and substrate. An interconnect structure is formed over the encapsulant. The interconnect structure is electrically connected to the first semiconductor die and first conductive layer. The substrate is removed to expose the first conductive layer. A second semiconductor die is mounted to the conductive layer over the first semiconductor die. | 09-26-2013 |
20130249101 | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units - A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die. | 09-26-2013 |
20130249090 | Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die - A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate. | 09-26-2013 |
20130249080 | Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation - A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer. | 09-26-2013 |
20130249079 | Semiconductor Device and Method of Singulating Semiconductor Wafer along Modified Region within Non-Active Region Formed by Irradiating Energy through Mounting Tape - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. | 09-26-2013 |
20130249076 | Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces - A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the first conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad. | 09-26-2013 |
20130248859 | Semiconductor Device and Method of Simultaneous Testing of Multiple Interconnects for Electro-Migration - A semiconductor device has a substrate and conductive layer over the substrate. A resistive element is formed between first and second portions of the conductive layer. A plurality of semiconductor die each with first and second bumps is mounted to the substrate with the first and second bumps electrically connected to the first and second portions of the conductive layer. A test current is routed in sequence through the first portion of the conductive layer, through the first and second bumps, and through the second portion of the conductive layer until continuity failure of the second bump. The test current originates from a single power supply. The test current continues to flow through the resistive element after the continuity failure of the second bump. The continuity failure can be detected by sensing an increase in voltage across the second bump. | 09-26-2013 |
20130241080 | Semiconductor Device and Method of Forming Interposer and Opposing Build-Up Interconnect Structure with Connecting Conductive TMV for Electrical Interconnect of FO-WLCSP - A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure. | 09-19-2013 |
20130241071 | Semiconductor Device and Method of Forming Compliant Conductive Interconnect Structure in Flipchip Package - A semiconductor device has a semiconductor die. The semiconductor die has a contact pad. A first conductive layer is formed over the contact pad. A conductive shell having a hollow core is formed over the first conductive layer. A compliant material is deposited in the hollow core. The semiconductor die is mounted over a substrate with the conductive shell electrically connected to a conductive trace on the substrate. A second conductive layer is formed over the conductive shell. The compliant material is an insulating material. A bump material is deposited around the conductive shell. A pre-solder material is deposited over the conductive trace. The conductive shell has a cross-sectional width less than 7 micrometers. The second conductive layer is a conductive lip. Mounting the semiconductor die over the substrate further includes mounting the semiconductor die over the substrate in a bump on lead (BOL) configuration. | 09-19-2013 |
20130241048 | Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers - A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture. | 09-19-2013 |
20130241039 | Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material - A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover. | 09-19-2013 |
20130241030 | Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die - A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires. | 09-19-2013 |
20130234324 | Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate - A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device. | 09-12-2013 |
20130234322 | Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration - A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die. | 09-12-2013 |
20130234318 | Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability - A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate. | 09-12-2013 |
20130228919 | Semiconductor Device and Method of Forming Protective Coating Over Interconnect Structure to Inhibit Surface Oxidation - A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium. | 09-05-2013 |
20130228917 | Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLP-MLP) - A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation. | 09-05-2013 |
20130221452 | Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus - A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die. | 08-29-2013 |
20130214409 | Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP - A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer. | 08-22-2013 |
20130214398 | Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die - A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die. | 08-22-2013 |
20130214385 | Package-in-Package Using Through-Hole Via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 08-22-2013 |
20130207247 | Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure - A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die. | 08-15-2013 |
20130200528 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure. | 08-08-2013 |
20130200527 | Semiconductor Device and Method of Forming Pre-Molded Substrate to Reduce Warpage During Die Molding - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and conductive layer formed over the substrate. A first encapsulant is deposited over the substrate outside a die attach area of the substrate. The first encapsulant surrounds each die attach area over the substrate and the die attach area is devoid of the first encapsulant. A channel connecting adjacent die attach areas is also devoid of the first encapsulant. A first semiconductor die is mounted over the substrate within the die attach area after forming the first encapsulant. A second semiconductor die is mounted over the first die within the die attach area. An underfill material can be deposited under the first and second die. A second encapsulant is deposited over the first and second die and first encapsulant. The first encapsulant reduces warpage of the substrate during die mounting. | 08-08-2013 |
20130181323 | Semiconductor Device and Method of Forming an Inductor on Polymer Matrix Composite Substrate - A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer. | 07-18-2013 |
20130175701 | Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection - A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers. | 07-11-2013 |
20130175696 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 07-11-2013 |
20130175668 | Semiconductor Device and Method of Making Integrated Passive Devices - A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization. | 07-11-2013 |
20130171800 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 07-04-2013 |
20130161833 | Semiconductor Device and Method of Forming Extended Semiconductor Device with Fan-Out Interconnect Structure to Reduce Complexity of Substrate - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate. | 06-27-2013 |
20130161824 | Semiconductor Device and Method of Forming Insulating Layer in Notches Around Conductive TSV for Stress Relief - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer. | 06-27-2013 |
20130154108 | Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro Via Array for 3-D FO-WLCSP - A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole. | 06-20-2013 |
20130154090 | Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 06-20-2013 |
20130154076 | Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect - A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads. | 06-20-2013 |
20130154067 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure. | 06-20-2013 |
20130147065 | Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material - A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel. | 06-13-2013 |
20130147055 | Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV through Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings. | 06-13-2013 |
20130147054 | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP - A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device. | 06-13-2013 |
20130147053 | Semiconductor Device and Method of Making Single Layer Substrate with Asymmetrical Fibers and Reduced Warpage - A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer. | 06-13-2013 |
20130147036 | Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias. | 06-13-2013 |
20130147035 | Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate - A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray. | 06-13-2013 |
20130147019 | Semiconductor Device and Method of Forming Insulating Layer Around Semiconductor Die - A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die. | 06-13-2013 |
20130146872 | Semiconductor Device and Method of Forming Conductive Pillars Having Recesses or Protrusions to Detect Interconnect Continuity Between Semiconductor Die and Substrate - A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection. | 06-13-2013 |
20130140719 | Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers - A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture. | 06-06-2013 |
20130140691 | Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration - A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer. | 06-06-2013 |
20130140683 | Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die - In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path. | 06-06-2013 |
20130134586 | Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer. | 05-30-2013 |
20130134580 | Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer. | 05-30-2013 |
20130127042 | Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent. | 05-23-2013 |
20130127039 | Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface - A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking. | 05-23-2013 |
20130127018 | Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 05-23-2013 |
20130119559 | Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die - A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. | 05-16-2013 |
20130113118 | Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer - A semiconductor device has a semiconductor die with bumps formed over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate and conductive layer. A masking layer having an opaque portion and linear gradient contrast portion is formed over the patterning layer. The linear gradient contrast portion transitions from near transparent to near opaque. The patterning layer is exposed to ultraviolet light through the masking layer. The masking layer is removed and a portion of the patterning layer is removed to form an opening having a sloped surface to expose the conductive layer. The sloped surface in patterning layer can be formed by laser direct ablation. The semiconductor die is mounted to the substrate with the bumps electrically connected to the conductive layer and physically separated from the patterning layer. | 05-09-2013 |
20130113093 | Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package - A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. | 05-09-2013 |
20130113092 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-09-2013 |
20130105989 | Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect | 05-02-2013 |
20130105970 | Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe | 05-02-2013 |
20130105967 | Semiconductor Die and Method of Forming Sloped Surface in Photoresist Layer to Enhance Flow of Underfill Material Between Semiconductor Die and Substrate | 05-02-2013 |
20130105963 | Semiconductor Device and Method of Forming Thermal Interface Material and Heat Spreader Over Semiconductor Die | 05-02-2013 |
20130099378 | Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die. | 04-25-2013 |
20130099356 | Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing - A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property. | 04-25-2013 |
20130093100 | Semiconductor Device and Method of Forming Conductive Pillar Having an Expanded Base - A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias partially through a first surface of the first semiconductor die. A portion of a second surface of the first semiconductor die is removed to expose the conductive vias. A plurality of conductive pillars is formed over the first surface the first semiconductor die. The conductive pillars include an expanded base electrically connected to the conductive vias. A width of the expanded base of the conductive pillars is greater than a width of a body of the conductive pillars. A conductive layer is formed over a second surface of the first semiconductor die. The conductive layer is electrically connected to the conductive vias. A second semiconductor die is mounted to the first semiconductor die with a second conductive pillar having an expanded base. | 04-18-2013 |
20130093068 | Semiconductor Device and Method of Forming Air Gap Adjacent to Stress Sensitive Region of the Die - A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure. | 04-18-2013 |
20130087931 | Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 04-11-2013 |