| StarDFX Technologies, Inc. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110022908 | ROBUST SCAN SYNTHESIS FOR PROTECTING SOFT ERRORS - A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level. | 01-27-2011 |
| 20110022907 | FPGA Test Configuration Minimization - A method for automatically generating test patterns using a close-to-minimum number of configurations for a Field Programmable Gate Array (FPGA) to reduce test data volume and test application time. The FPGA can be a standalone programmable device or a circuit embedded in an Application Specific Integrated Circuit (ASIC). | 01-27-2011 |
