| ST Microelectronics Patent applications |
| Patent application number | Title | Published |
|---|
| 20110303990 | Semiconductor Device and Method Making Same - A FET comprising an LDD region having a high overlap extension beneath the gate thereof and a pit region on the surface of the substrate immediately below the gate and entirely surrounded by said LDD region. The surface dopant concentration is in the vicinity of the gate corner so as to reduce the local field strength, and thereby decrease the GIDL, whilst keeping high overlap extension so a to maintain a high Ion current. More particularly a region under the gate corner but enclosed by the conventional LDD is counterdoped. Counter-doping of the LDD is performed with a sufficiently low energy, a specific dose and a low angle that the counter-doped region is enclosed into the LDD (at the substrate/gate-oxide interface and keeping high overlap extension between the gate oxide and the non-counter-doped LDD). As an optimum, the counter-doped region is under the gate corner. In that way, high Ion current is ensure with a overlap length is not altered. | 12-15-2011 |
| 20100293366 | FREQUENCY AND SYMBOL LOCKING USING SIGNAL GENERATED CLOCK FREQUENCY AND SYMBOL IDENTIFICATION - Methods and systems are described for displaying video data after a hot plug event during a start-up dead period. In particular, approaches for receiving data, determining whether link training can be performed and, if not, self-configuring a receiver to display the information in a proper format even during the dead period. | 11-18-2010 |
