| SPANSION LLC Patent applications |
| Patent application number | Title | Published |
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| 20120066464 | APPARATUS AND METHOD FOR PROGRAMMABLE READ PREAMBLE - A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data. | 03-15-2012 |
| 20120066434 | APPARATUS, METHOD, AND MANUFACTURE FOR USING A READ PREAMBLE TO OPTIMIZE DATA CAPTURE - A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern. | 03-15-2012 |
| 20120066433 | Apparatus and method for read preamble disable - A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble. | 03-15-2012 |
| 20120063243 | APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE - A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to. | 03-15-2012 |
| 20120056260 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 03-08-2012 |
| 20120038051 | BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME - A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect. | 02-16-2012 |
| 20120034755 | METHOD AND MANUFACTURE FOR HIGH VOLTAGE GATE OXIDE FORMATION AFTER SHALLOW TRENCH ISOLATION FORMATION - A method and manufacture for fabrication of flash memory is provided. In fabricating the periphery region of the flash memory, the low voltage gate oxides and high voltage gate oxides are grown to the same height as each other prior to STI etching. After STI etching and gap fill, the nitride above the high voltage gate oxide regions are etched, and the oxide in high voltage gate oxide regions is grown to the appropriate thickness for a high voltage gate oxide. | 02-09-2012 |
| 20120032308 | GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS - Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD. | 02-09-2012 |
| 20110317466 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-29-2011 |
| 20110278660 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 11-17-2011 |
| 20110238866 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus. | 09-29-2011 |
| 20110237060 | SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved. | 09-29-2011 |
| 20110236773 | FUEL CELL CATALYST REGENERATION - Systems that facilitate operating proton exchange membrane (PEM) fuel cells are provided. The systems employ a fuel supply component that supplies fuel to the proton exchange membrane fuel cell; and a regeneration component that provides a reducing agent comprising a mixture of hydrogen and nitrogen, or a reducing plasma to a cathode catalyst of the proton exchange membrane fuel cell to reduce the cathode catalyst. | 09-29-2011 |
| 20110235430 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 09-29-2011 |
| 20110235412 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 09-29-2011 |
| 20110225348 | ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES - System and methods for assembling electronic devices ( | 09-15-2011 |
| 20110225327 | SYSTEMS AND METHODS FOR CONTROLLING AN ELECTRONIC DEVICE - Systems and methods ( | 09-15-2011 |
| 20110224810 | HOME AND BUILDING AUTOMATION | 09-15-2011 |
| 20110221006 | NAND ARRAY SOURCE/DRAIN DOPING SCHEME - An electronic device includes a substrate having isolation features defining active regions coextending over a surface of the substrate. The device also includes coextending line patterns crossing over the active regions, including string and ground selection lines and word lines between the string and ground selection lines. The device further includes first implant regions of a first conductivity type in the active regions between the word lines and having a first carrier concentration. The device further includes second implant regions of the first conductivity type in the active regions between edge ones of the word lines and an adjacent one of the string selection line and the ground selection line. In the device, the second implant region includes a low doping portion abutting the edge word lines and a high doping portion spaced from the edge word line by the low doping portion and having a second carrier concentration greater than the first carrier concentration. | 09-15-2011 |
| 20110220981 | NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers. | 09-15-2011 |
| 20110199819 | APPARATUS AND METHOD FOR EXTENDED NITRIDE LAYER IN A FLASH MEMORY - A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench. | 08-18-2011 |
| 20110195578 | PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH - A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed. | 08-11-2011 |
| 20110179319 | FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES - An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors. | 07-21-2011 |
| 20110179215 | PROGRAMMABLE READ PREAMBLE - The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment. | 07-21-2011 |
| 20110179195 | FIELD UPGRADABLE FIRMWARE FOR ELECTRONIC DEVICES - An electronic device includes an input/output (I/O) interface and a plurality of memory elements comprising a non-volatile memory portion for storing a default firmware and a working memory portion having a firmware area. The device also includes a controller coupled to the I/O interface and the memory elements, where the controller is configured for operating the memory elements, according to the firmware area, and for monitoring the I/O interface. In the device, the controller is also configured for loading the default firmware into the firmware area when the controller is enabled and for granting access to the firmware area for loading an alternate firmware if a bypass code is detected at the I/O interface. | 07-21-2011 |
| 20110176363 | JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES - A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. | 07-21-2011 |
| 20110169069 | HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 07-14-2011 |
| 20110164452 | MEMORY DEVICE | 07-07-2011 |
| 20110156130 | METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE - A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures. | 06-30-2011 |
| 20110153915 | READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION - Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point within a window of data validity. | 06-23-2011 |
| 20110153900 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 06-23-2011 |
| 20110149630 | HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS - Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices. | 06-23-2011 |
| 20110136268 | PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS - A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed. | 06-09-2011 |
| 20110129976 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 06-02-2011 |
| 20110122708 | METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS - A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation. | 05-26-2011 |
| 20110095355 | SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS - Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes. | 04-28-2011 |
| 20110084330 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 04-14-2011 |
| 20110080792 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 04-07-2011 |
| 20110051529 | MEMORY DEVICE - Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The first pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate. | 03-03-2011 |
| 20110037115 | SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE - A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench. | 02-17-2011 |
| 20110008966 | PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP - A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components. | 01-13-2011 |
| 20100330762 | METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES - A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity, | 12-30-2010 |
| 20100329024 | MEMORY EMPLOYING SEPARATE DYNAMIC REFERENCE AREAS - A memory that employs separate Dynamic reference (Dref) areas to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, a reference array, and one or more sense amplifiers. The data area is arranged to provide an output signal, the reference cell and the separate Dref areas are arranged to provide the threshold voltage reference signal, and the sense amplifiers are arranged to receive the output signal and the threshold voltage reference signal. | 12-30-2010 |
| 20100329003 | MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS - A memory that employs separate Dref areas that are independently accessed to provide a threshold voltage reference signal. The memory includes the separate Dref areas, a data area positioned between the Dref areas, one or more sense amplifiers, and a switch component. The switch component is arranged to receive addressing data and to independently couple one of the separate Dref areas to the sense amplifiers based, at least in part, on a physical proximity of individual memory cells along a word line. | 12-30-2010 |
| 20100327417 | ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL - An electronic device includes a packaged integrated circuit having an integrated circuit die having an active surface, and a molding compound overlaying the active surface of the integrated circuit die. In a particular embodiment, the packaged integrated circuit includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound. In another embodiment, the packaged integrated circuit includes approximately 0.3 μmol/cm | 12-30-2010 |
| 20100314753 | SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING - A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate. | 12-16-2010 |
| 20100294946 | RADIATION DETECTING DEVICE AND METHOD OF OPERATING - A method of operating a radiation-detecting device includes charging a first charge storage region of a charge storage structure to place a first charge value at the first charge storage region, and charging a second charge storage region of the charge storage structure to place a second charge value at the second charge storage region. The method further includes conducting a first read operation to determine a change in the first charge value at the first charge storage region at a first time after charging the first charge storage region, and determining a first radiation flux value for an environment containing the charge storage structure based on the change in the first charge value at the first time. | 11-25-2010 |
| 20100289072 | Electronic Device Including a Gate Electrode Having Portions with Different Conductivity Types - An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type. | 11-18-2010 |
| 20100281293 | REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY - Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period. | 11-04-2010 |
| 20100280817 | DIRECT POINTER ACCESS AND XIP REDIRECTOR FOR EMULATION OF MEMORY-MAPPED DEVICES - A system, apparatus and method for emulating memory-mapped devices in the development of software where a device is mapped to protected memory space. When an instruction causing an attempted read or write to the protected space occurs, an exception or interrupt occurs, the instruction is analyzed and converted into a function call. The function call is sent to a device simulator for execution. The results of the function call are then used to update the registers of the processor and execution of application program will resume at a subsequent instruction. | 11-04-2010 |
| 20100264519 | GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS - Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD. | 10-21-2010 |
| 20100264480 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 10-21-2010 |
| 20100240210 | STRAPPING CONTACT FOR CHARGE PROTECTION - A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area. | 09-23-2010 |
| 20100219486 | METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY - A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide. | 09-02-2010 |
| 20100213535 | ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT - Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space. | 08-26-2010 |
| 20100208527 | SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY - A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase. | 08-19-2010 |
| 20100208517 | PIN DIODE DEVICE AND ARCHITECTURE - A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line. | 08-19-2010 |
| 20100207191 | METHOD AND DEVICE EMPLOYING POLYSILICON SCALING - A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack. | 08-19-2010 |
| 20100187596 | Self-aligned double patterning for memory and other microelectronic devices - A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process. | 07-29-2010 |
| 20100177568 | READ MODE FOR FLASH MEMORY - A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed. | 07-15-2010 |
| 20100155817 | HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 06-24-2010 |
| 20100155816 | HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions. | 06-24-2010 |
| 20100155785 | HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION - Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines. | 06-24-2010 |
| 20100155618 | RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING - A method of operating an electronic device including determining an initial charge level at a non-volatile charge storage structure of a radiation-sensitive device including a radiation-reactive material and determining if a first radiation event has occurred based upon the non-volatile charge storage device having a different charge level than the initial charge level. The method further includes identifying the first radiation event as associated with either a first type of radiation or a second type of radiation based upon the different charge level. | 06-24-2010 |
| 20100155611 | RADIATION-DETECTING STRUCTURES - A mobile device including a housing, a wireless signal transceiver contained within the housing, and a radiation-detecting structure comprising a charge storage structure contained within the housing to detect radiation. | 06-24-2010 |
| 20100142284 | DETERMINISTIC-BASED PROGRAMMING IN MEMORY - Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt. | 06-10-2010 |
| 20100142269 | MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS - A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access. | 06-10-2010 |
| 20100135082 | MOVING PROGRAM VERIFY LEVEL FOR PROGRAMMING OF MEMORY - Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level. | 06-03-2010 |
| 20100133605 | SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE - A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate. | 06-03-2010 |
| 20100131676 | SPI ADDRESSING BEYOND 24-BITS - A system and/or methodology that facilitates serial peripheral interface (SPI) addressing beyond 24 bits, by portioning a conventional SPI command byte into a plurality of nibbles. A new set of commands are mapped to the first nibble, and selected from the set of unused binary values under the conventional SPI command protocol. A number of address bytes required to access the storage location for the command are mapped on a second nibble, and a user and/or system definable number of dummy bytes to be sent after the command are mapped on a third nibble. | 05-27-2010 |
| 20100128524 | MULTI-PHASE PROGRAMMING OF MULTI-LEVEL MEMORY - Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels. | 05-27-2010 |
| 20100128521 | APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB - Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount. | 05-27-2010 |
| 20100122908 | ELECTROPLATING APPARATUS AND METHOD WITH UNIFORMITY IMPROVEMENT - An electroplating system is provided. The electroplating system includes a divided electrode that is arranged to simultaneously provide a plurality of line currents for an electroplating process. The system includes a current control component that is coupled to the divided electrode. The current control component is configured to determine the magnitude of each of the line currents. The current control component is also configured to regulate individual line currents based, at least in part, on the determined magnitude of each of the line currents. | 05-20-2010 |
| 20100122146 | ERROR CORRECTION FOR FLASH MEMORY - Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory. | 05-13-2010 |
| 20100120239 | MEMORY DEVICE ETCH METHODS - A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF | 05-13-2010 |
| 20100110819 | Apparatus and Method for Placement of Boosting Cell With Adaptive Booster Scheme - A memory is provided. The memory includes memory arrays and boost converter circuitry. The boost converter circuitry provides at least one boosted voltage to each of the memory arrays when the memory array is being accessed. The boosted voltages may include a word line voltage, and/or a pass gate voltage provided to the gates of pass line transistor in a sector decoders and/or an array decoder for the memory cells being accessed. The boost converter circuitry includes at least two boost converters, and a switch. When one of the memory arrays is accessed, the switch either couples the boost converters together or does not couple the boost converters together based on the distance of the memory array being accessed from the boost converters. | 05-06-2010 |
| 20100109070 | FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS - A device and method employing a polyoxide-based charge trapping component. A charge trapping component is patterned by etching a layered stack that includes a tunneling layer positioned on a substrate, a charge trapping layer positioned on the tunneling layer, and an amorphous silicon layer positioned on the charge trapping layer. An oxidation process grows a gate oxide layer from the substrate and converts the amorphous silicon layer into a polyoxide layer. | 05-06-2010 |
| 20100103732 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 04-29-2010 |
| 20100099249 | SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-22-2010 |
| 20100097876 | APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY - A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator. | 04-22-2010 |
| 20100074009 | QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL - Flash memory systems and methodologies are provided herein for facilitating single logical cell erasure and quad or more bit storage in a flash device. The single logical cell erasure can be accomplished by employing a single program and erase entity as a single logical cell. The single program and erase entity is a combination of neighboring drain/source regions of two adjacent physical memory cells. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis. The memory cells can contain four or more data states, and each of the two adjacent memory cells in the single program and erase entity can be programmed independently from each other. As a result, the single program and erase entity can store four or more bits. | 03-25-2010 |
| 20100074008 | SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES - Flash memory systems and methodologies are provided for providing multiple virtual ground decoding schemes in a flash device. The flash device can include sector configure registers for selecting a specific ground scheme at sector level. The sector configure registers can select a decoding scheme from multiple virtual ground decoding schemes including a conventional dual bit decoding scheme and a single program and erase entity decoding scheme. Since the single program and erase entity decoding scheme can emulate EEPROM functionality in a flash device, the combination of the conventional dual bit decoding scheme and the single program and erase entity decoding scheme can provide both dual bit high density storage and EEPROM emulation in a single flash device. | 03-25-2010 |
| 20100074007 | FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL - Flash memory systems and methods are provided for facilitating a single logical cell erasure in a flash memory device. Logical cell mapping is changed from using a single physical cell to using pair physical cells, thereby creating a single program and erase entity as a single logical cell. By mapping two adjacent physical cells as a single logical cell, the flash memory device can be programmed and erased on a single bit or variable bit length basis with conventional technologies. Various operations can be performed on a flash device on a basis of the single program and erase entity. | 03-25-2010 |
| 20100074006 | DYNAMIC ERASE STATE IN FLASH DEVICE - Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory cells. The dynamic erase state can involve an indicator bit that indicates an erase direction of a low voltage state or a high voltage state. The single logical cell erasure can be performed by changing a voltage state of a single program and erase entity according to the indicated erase direction. By employing the indicator bit with the single program and erase entity decoding scheme, the methods and systems can reduce erase time and/or a number of cycles, thereby increasing system reliability, efficiency, and/or durability. | 03-25-2010 |
| 20100074005 | EEPROM EMULATION IN FLASH DEVICE - Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device. | 03-25-2010 |
| 20100074004 | HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN - Flash memory systems and methodologies are provided herein for using a high voltage state as an erase condition in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a single logical cell, thereby creating a single program and erase entity. Logical cell erase, program, and/or read can be accomplished by using two channel regions in union. This combination can allow for single logical cell erasure in a flash device and the use of a high voltage state as an erased state. A default erased state can be a high voltage state. As a result, program operations can be performed by changing a voltage state of the single program and erase entity to a low voltage state, and erase operations can be performed by changing a voltage state of the single program and erase entity to a high voltage state. | 03-25-2010 |
| 20100059762 | HEAT REMOVAL FACILITATED WITH DIAMOND-LIKE CARBON LAYER IN SOI STRUCTURES - Described are Silicon-on-Insulator devices containing a diamond-like carbon layer, methods of making the Silicon-on-Insulator devices, and methods of using the Silicon-on-Insulator devices. | 03-11-2010 |
| 20100058151 | IMPLEMENTATION OF RECYCLING UNUSED ECC PARITY BITS DURING FLASH MEMORY PROGRAMMING - Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory with new user data. Re-encoding ECC comprises comparing new ECC with the most recent ECC of the previous syndrome, correcting a bit error in the new ECC, and indicating if the new ECC has failed. | 03-04-2010 |
| 20100055809 | PROCESS OF FABRICATING A WORKPIECE USING A TEST MASK - A product workpiece can be processed to form product dice. A test mask can allow intentional changes to be made to a feature on the product workpiece to examine how the altered feature performs. Use of the test mask may be used or not used based on the needs or desires of skilled artisans. By using the test mask, a separate dedicated test structure is not required to be formed in a scribe lane or within an area that could otherwise be used for a product die. Thus, the sampling level by using the test mask can be varied. Also, separate test workpieces, which may not be processed using a significantly different process flow or at significantly different times as compared to product workpieces, are not required. The product workpiece with the altered feature can be electrically tested without the need to form test or bond pads. | 03-04-2010 |
| 20100037032 | Multi-Level Storage Algorithm To Emphasize Disturb Conditions - Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages, based on a cell's current characteristic state, or directly store the desired characteristic state of each cell of the plurality of multi-cell memory devices, based on an ordering of desired characteristic states of cells of the multi-cell memory devices. Further, a step component can gradate the equivalent characteristic state between successive storage stages. In this way, the overlap of distributions of electrical characteristics associated with different bits of one or more memory cells can be reduced. | 02-11-2010 |
| 20100018202 | THERMOELECTRIC DEVICE FOR USE WITH STIRLING ENGINE - An exhaust gas manifold having thermoelectric devices in the exhaust manifold of a stirling engine is disclosed. | 01-28-2010 |
| 20100013504 | PROBE APPARATUS, A PROCESS OF FORMING A PROBE HEAD, AND A PROCESS OF FORMING AN ELECTRONIC DEVICE - A probing apparatus includes a set of conductors configured to contact a surface of a workpiece simultaneously. A processor activates subsets of the conductors to determine a four-point-probe parameter, wherein the subset is less than the set of conductors. Another subset determines another four-point-probe parameter. The set of conductors remain in contact with the surface of the workpiece during and between activating each subset. A process of forming a probe head includes a probe substrate and associated conductive leads. An insulating layer is formed over the probe substrate and patterned to expose the leads. Conductors, connected to the leads, are formed over the insulating layer and define a probing area of at least 250 cm | 01-21-2010 |
| 20090316481 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 12-24-2009 |
| 20090303798 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 12-10-2009 |
| 20090303795 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 12-10-2009 |
| 20090303793 | MEMORY DEVICE AND METHOD - During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed. | 12-10-2009 |
| 20090302203 | IMAGING DEVICE - An imaging device suitable for detecting certain imaging particles and recording the detection of imaging particles, and as such can include certain recording devices such as a charge storage structure. | 12-10-2009 |
| 20090300318 | ADDRESS CACHING STORED TRANSLATION - Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation. | 12-03-2009 |
| 20090300312 | INSTANT HARDWARE ERASE FOR CONTENT RESET AND PSEUDO-RANDOM NUMBER GENERATION - Systems and methods that facilitate securing data associated with a memory from security breaches are presented. A memory component includes nonvolatile memory, and a secure memory component (e.g., volatile memory) used to store information such as secret information related to secret processes or functions (e.g., cryptographic functions). A security component detects security-related events, such as security breaches or completion of security processes or functions, associated with the memory component and in response to a security-related event, the security component can transmit a reset signal to the secure memory component to facilitate efficiently erasing or resetting desired storage locations in the secure memory component in parallel and in a single clock cycle to facilitate data security. A random number generator component can facilitate generating random numbers after a reset based on a change in scrambler keys used by a scrambler component to descramble data read from the reset storage locations. | 12-03-2009 |
| 20090273998 | BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF - A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved. | 11-05-2009 |
| 20090261367 | OPTICAL ERASE MEMORY STRUCTURE - A method for providing an optical erase memory structure including: forming a metal-insulator-metal memory cell; positioning a light emitting diode adjacent to the metal-insulator-metal memory cell; and emitting a light emission from the light emitting diode for erasing the metal-insulator-metal memory cell. | 10-22-2009 |
| 20090256242 | METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE STORAGE ELEMENT IN A TRENCH OF A WORKPIECE - A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls. | 10-15-2009 |
| 20090249015 | OPERATING SYSTEM BASED DRAM / FLASH MANAGEMENT SCHEME - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090249014 | SECURE MANAGEMENT OF MEMORY REGIONS IN A MEMORY - Systems and/or methods that facilitate controlling access to memory regions in a memory component(s) are presented. A memory component can comprise an access management component that can facilitate controlling access to memory regions that can be respectively associated with authentication credentials. The access control component can facilitate access of a memory region when received authentication information matches authentication information contained in a security record associated with the memory region. The access management component can facilitate a wipe erase of a memory region(s) to facilitate secure removal of information from the memory region when predetermined criteria is satisfied. The access management component can facilitate locking a memory region when a maximum number of attempts to access a memory region are unsuccessful to facilitate security of the memory regions and/or data associated therewith, where a locked memory region remains locked until a reset is performed. | 10-01-2009 |
| 20090248959 | FLASH MEMORY AND OPERATING SYSTEM KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090248958 | FLASH MEMORY USABILITY ENHANCEMENTS IN MAIN MEMORY APPLICATION - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090248957 | MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
| 20090246584 | FUEL CELL CATALYST REGENERATION - Systems and methods that facilitate operating proton exchange membrane (PEM) fuel cells are provided. The methods can involve contacting a reducing agent comprising a mixture of hydrogen and nitrogen, or a reducing plasma with a cathode catalyst of a proton exchange membrane fuel cell to reduce the cathode catalyst. The systems employ a fuel supply component that supplies fuel to the proton exchange membrane fuel cell; and a regeneration component that provides a reducing agent comprising a mixture of hydrogen and nitrogen, or a reducing plasma to a cathode catalyst of the proton exchange membrane fuel cell to reduce the cathode catalyst. | 10-01-2009 |
| 20090244989 | BITLINE VOLTAGE DRIVER - A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage. | 10-01-2009 |
| 20090239468 | WIRELESS MASS STORAGE FLASH MEMORY - Systems and/or methods are presented that can facilitate access of a memory device by the use of wireless communication technologies. A memory module is presented which combines memory with a wireless adapter component and a memory controller component to facilitate the wireless transmission and reception of data and/or commands from and to host component that requests access to the memory and the data stored therein. The memory module can dynamically switch between one wireless communication technology to another based on signal strength, signal quality, the distance between the memory module and a host component, power usage, as well as other criteria to facilitate an optimal data transmission or throughput rate. | 09-24-2009 |
| 20090233422 | SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE - Systems and methodologies are provided for forming a diode component integral with a memory cell to facilitate programming arrays of memory cells created therefrom. Such a diode component can be part of a PN junction of memory cell having a passive and active layer with asymmetric semiconducting properties. Such an arrangement reduces a number of transistor-type voltage controls and associated power consumption, while enabling individual memory cell programming as part of a passive array. Moreover, the system provides for an efficient placement of memory cells on a wafer surface, and increases an amount of die space available for circuit design. | 09-17-2009 |
| 20090222910 | MEMORY DEVICE AND CHIP SET PROCESSOR PAIRING - Systems, devices and/or methods that facilitate mutual authentication for processor and memory pairing are presented. A processor and a suitably equipped memory can be provided with a shared secret to facilitate mutual authentication. In addition, the memory can be configured to verify that the system operating instructions have not been subjected to unauthorized alterations. System integrity can be ensured according to the disclosed subject matter by mutual authentication of the processor and memory and verification of the authenticity of system operating instructions at or near each system power up. As a result, the disclosed subject matter can facilitate relatively low complexity assurance of system integrity as a replacement or supplement to conventional techniques. | 09-03-2009 |
| 20090217058 | SECURE DATA TRANSFER AFTER AUTHENTICATION BETWEEN MEMORY AND A REQUESTER - Systems and/or methods are presented that can facilitate controlling access to secure memory blocks within a memory module. The subject innovation can employ key components that can contain two or more storage locations for authentication information that can facilitate controlling access to secure memory block components. Secure memory block counter components can be employed to indicate which storage location within the key component contains current authentication information associated with the respective secure memory block components. The disclosed subject matter allows for multiple secure memory block components to have separate authentication information to provide more than one user or entity to store data in their own secure memory block component. Multiple storage locations associated with the key components to substantially alleviated or eliminate the loss of secure areas of a memory module if power is lost during the updating of the authentication information associated with the secure areas. | 08-27-2009 |
| 20090209107 | METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS - A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature. | 08-20-2009 |
| 20090206386 | DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES - One embodiment of the present invention relates to a flash memory array. The flash memory array comprises at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further comprises a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level. Other methods and circuits are also disclosed. | 08-20-2009 |
| 20090201724 | MEMORY DEVICE AND METHOD THEREOF - A device and corresponding method of using a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier is disclosed. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent disclosing time can be achieved at a sense node of a sense amplifier. | 08-13-2009 |
| 20090198874 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198873 | PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198872 | HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090198871 | EXPANSION SLOTS FOR FLASH MEMORY BASED MEMORY SUBSYSTEM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
| 20090193193 | TRANSLATION TABLE COHERENCY MECAHANISM USING CACHE WAY AND SET INDEX WRITE BUFFERS - Systems and/or methods are presented that provide for recording transactions that occur during a write process in an organized, self-aggregated manner for the purpose of recovering the transactions in the event of a power loss. By implementing an organization that reflects the cache architecture that is organized according to the cache way and set index of each transaction, the amount of time and effort required to recover the modified data from a sudden loss of power event is minimized. In this regard, the cache way and set index cache architecture provides for a post-power loss search operation that is limited to identifying duplicate locations within the cache-line and keeping only the most recent modification. By providing for such pre-organization in terms of self-aggregation by cache way and set index recording, the overall search process is greatly reduced and flexibility can be implemented in cache-line eviction processing in the event that the cache is determined to be full. | 07-30-2009 |
| 20090189212 | ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM - An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom. | 07-30-2009 |
| 20090189202 | ELECTRONIC DEVICE INCLUDING A GATE ELECTRODE HAVING PORTIONS WITH DIFFERENT CONDUCTIVITY TYPES AND A PROCESS OF FORMING THE SAME - An electronic device can include a gate electrode having different portions with different conductivity types. In an embodiment, a process of forming the electronic device can include forming a semiconductor layer over a substrate, wherein the semiconductor layer has a particular conductivity type. The process can also include selectively doping a region of the semiconductor layer to form a first doped region having an opposite conductivity type. The process can further include patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region. In a particular embodiment, the electronic device can have a gate electrode having edge portions of one conductivity type and a central portion having an opposite conductivity type. | 07-30-2009 |
| 20090187700 | RETARGETING OF A WRITE OPERATION RETRY IN THE EVENT OF A WRITE OPERATION FAILURE - Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer. | 07-23-2009 |
| 20090180345 | VOLTAGE BOOSTER BY ISOLATION AND DELAYED SEQUENTIAL DISCHARGE - Systems and methods for improving efficiency of a voltage booster for read mode operations of memory cells and discharging a boosted supply voltage safely are disclosed. The system contains a plurality of boosting stages coupled in series including a plurality of boosting capacitors, a plurality of isolators. The isolator can be used to prevent boosting of one capacitor from negatively affecting a charge of the other adjacent capacitor to improve the efficiency of the voltage booster. A voltage booster circuit can accurately boost a supply voltage with a suitable number of boosting stages depending on a level of the supply voltage being provided. Since boosters contain a suitable number of boosting stages, the boosters can discharge a boosted voltage sequentially. With this sequential discharge method, memory cells can not have a hot switching problem. | 07-16-2009 |
| 20090175441 | METHOD FOR PROTECTING DATA AGAINST DIFFERNTIAL FAULT ANALYSIS INVOLVED IN RIVEST, SHAMIR, AND ADLEMAN CRYPTOGRAPHY USING THE CHINESE REMAINDER THEOREM - Systems and methods for effectively protecting data against differential fault analysis involved in Rivest, Shamir, and Adleman (“RSA”) cryptography using the Chinese Remainder Theorem (“CRT”) are described herein. A CRT RSA component facilitates modular exponentiation of a received message, and a verification component reconstructs the received message. An exponentiation component performs a first modular exponentiation and a second modular exponentiation of the received message. A recombination component performs a recombination step utilizing CRT computation as a function of the first and second modular exponentiations. A modular exponentiation component performs first and second public exponent derivations as a function of a private exponent. The verification component can reconstructs the received message as a function of the first and second public exponent derivations. The verification component calculates the received message utilizing Chinese Remainder Theorem computation. | 07-09-2009 |
| 20090172345 | TRANSLATION MANAGEMENT OF LOGICAL BLOCK ADDRESSES AND PHYSICAL BLOCK ADDRESSES - Systems and/or methods that facilitate PBA and LBA translations associated with a memory component(s) are presented. A memory controller component facilitates determining which memory component, erase block, page, and data block contains a PBA in which a desired LBA and/or associated data is stored. The memory controller component facilitates control of performance of calculation functions, table look-up functions, and/or search functions to locate the desired LBA. The memory controller component generates a configuration sequence based in part on predefined optimization criteria to facilitate optimized performance of translations. The memory controller component and/or associated memory component(s) can be configured so that the translation attributes are determined in a desired order using the desired translation function(s) to determine a respective translation attribute based in part on the predefined optimization criteria. The LBA to PBA translations can be performed in parallel by memory components. | 07-02-2009 |
| 20090172250 | RELOCATING DATA IN A MEMORY DEVICE - Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 07-02-2009 |
| 20090166550 | ARRAYED NEUTRON DETECTOR WITH MULTI SHIELDING ALLOWING FOR DISCRIMINATION BETWEEN RADIATION TYPES - Neutron detectors including one or more gamma shields over memory dies and methods of making the neutron detectors are provided. The neutron detectors can contain two or more memory dies, neutron-reactant layers over the two or more memory dies, and one or more gamma shields over at least a portion of or an entire of the two or more memory dies. By containing the gamma shield over the at least a portion of or an entire of the two or more memory dies, the neutron detector can detect and discriminate neutrons in the presence of gamma rays. | 07-02-2009 |
| 20090165086 | RANDOM NUMBER GENERATION THROUGH USE OF MEMORY CELL ACTIVITY - Systems and/or methods that facilitate security of data are presented. A random number generation component generates random numbers based in part on electron activity in a select memory cell(s) to facilitate data security. Sensor components that are highly sensitive can be employed to sense activity of the select memory cell(s) and/or reference memory cell in a noise margin associated with respective memory cells in the memory component. The activity of the select memory cell is compared to the reference memory cell(s) to facilitate generating binary data. The binary data is provided to the random number generation component where the binary data is evaluated to determine whether a predetermined level of entropy exists in the binary data. The binary data, or a portion thereof, can be processed to generate random numbers that are utilized in cryptographic processes and/or as a physical signature to facilitate data security. | 06-25-2009 |
| 20090165020 | COMMAND QUEUING FOR NEXT OPERATIONS OF MEMORY DEVICES - Systems and/or methods that facilitate transferring data between a processor component and memory components are presented. A transfer controller component facilitates controlling data transfers in part by receiving respective subsets of data from respective memory components and arranging the respective subsets of data based in part on a desired predefined data order. The processor component generates a transfer map that includes information to facilitate arranging data in a predefined order. The processor component generates respective subsets of commands that are provided to queue components in respective memory components to retrieve desired data from the respective memory components. Each memory component services the commands in its queue component in an independent and parallel manner, and transfers the data retrieved from memory to the transfer controller component, which can arrange the received data in a predefined order for transfer to the processor component. | 06-25-2009 |
| 20090164836 | ERROR CORRECTION IN FLASH MEMORY ARRAY - Systems and/or methods that facilitate that facilitate error correction of data stored in memory components, such as flash memory devices are presented. An optimized correction component can be used to break data into two or more data blocks. The optimized correction component can facilitated creating one or two redundancy blocks that can be associated with the data blocks, wherein data blocks and the redundancy blocks can be assembled into a data stripe that can be stored in three or more of the memory components. Upon retrieval of the data stripe, the optimal correction component, an error correction code (ECC) component or a combination thereof can correct data blocks that contain errors wherein the decision whether the optimized correction component or the error correction code (ECC) component corrects the errors can be based in part on a predetermined criteria. | 06-25-2009 |
| 20090164789 | AUTHENTICATED MEMORY AND CONTROLLER SLAVE - Systems and methods that can facilitate the utilization of a memory as a slave to a host are presented. The host and memory can provide authentication information to each other and respective rights can be granted based in part on the respective authentication information. The host can determine the available functionality of the memory. The host can activate the desired functionality in the memory and can request memory to perform the desired function(s) with regard to data stored in the memory. An optimized controller component in the memory can facilitate performing the desired function(s) associated with the data to generate a result. The result can be provided to the host, while the data and associated information utilized to generate the result can remain in the memory and are cannot be accessed by the host. | 06-25-2009 |
| 20090164750 | DATA COMMIT ON MULTICYCLE PASS COMPLETE WITHOUT ERROR - A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data. | 06-25-2009 |
| 20090164704 | HIGH PERFORMANCE FLASH CHANNEL INTERFACE - Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface. | 06-25-2009 |
| 20090164703 | FLEXIBLE FLASH INTERFACE - Systems and methods that can facilitate providing a flexible flash interface component that can accommodate communicating with almost any flash memory component (e.g., Open NAND Flash Interface (ONFI) compliant and ONFI noncompliant flash memory). A micro-operations component can contain one or more micro-operation that can be used to execute commands within the flash interface component. To facilitate a flexible flash interface, the micro-operations can include such commands as, but are not limited to, sending a command to the flash memory, sending a row address, sending a column address, transmit data (TXD), receive data (RXD), have the flash interface wait for a ready signal from the flash memory, read a status register from a flash memory, and/or provide an end of sequence (EOS) indication to the flash interface, for example. | 06-25-2009 |
| 20090164702 | FREQUENCY DISTRIBUTED FLASH MEMORY ALLOCATION BASED ON FREE PAGE TABLES - Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time. | 06-25-2009 |
| 20090164700 | EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN - Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component. | 06-25-2009 |
| 20090164696 | PHYSICAL BLOCK ADDRESSING OF ELECTRONIC MEMORY DEVICES - Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation. | 06-25-2009 |
| 20090161466 | EXTENDING FLASH MEMORY DATA RETENSION VIA REWRITE REFRESH - Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate. | 06-25-2009 |
| 20090161462 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 06-25-2009 |
| 20090161430 | BIT MAP CONTROL OF ERASE BLOCK DEFECT LIST IN A MEMORY - Systems and methods that facilitate bad block management in a memory device that comprises nonvolatile memory are presented. One or more memory blocks of a memory device are each associated with one or more additional, dedicated bits that facilitate indicating whether the associated memory block is defective. These additional bits, called bad block bits, can be stored in a hardware-based storage mechanism within the memory device. Once a defect is detected in a memory block, at least one of the associated bad block bits can be set to indicate that the memory block is defective. If at least one of the bad block bits associated with a memory block indicates a memory block is defective, access to the memory block can be prevented. | 06-25-2009 |
| 20090159958 | ELECTRONIC DEVICE INCLUDING A SILICON NITRIDE LAYER AND A PROCESS OF FORMING THE SAME - An electronic device can include a silicon nitride layer. In an embodiment, the silicon nitride layer can include boron, grains, or both. The silicon nitride layer may be used as part of a charge storage layer within a nonvolatile memory cell within the electronic device. In a particular embodiment, the boron within the silicon nitride layer may be no greater than approximately 9 atomic % of the layer. The boron can be incorporated into the silicon nitride layer as it is being formed. The layer can be formed using chemical vapor deposition, physical vapor deposition, another suitable formation process, or any combination thereof. | 06-25-2009 |
| 20090159321 | ELECTRONIC DEVICES WITH ULTRAVIOLET BLOCKING LAYERS AND PROCESSES OF FORMING THE SAME - An electronic device can include a conductive feature and an ultraviolet (“UV”) blocking layer overlying the conductive feature. The electronic device can also include an insulating layer overlying the UV blocking layer. The electronic device can further include a conductive structure extending into an opening within the insulating layer, wherein the conductive structure is electrically connected to the conductive feature. In one aspect, the UV blocking layer lies within 90 nm of the conductive structure. The insulating layer can be at least 4 times thicker than the UV blocking layer. In another aspect, a method can be used in forming the electronic device. In still a further aspect, a system can include the electronic device, a processor, and a display, wherein the processor is electrically coupled to the electronic device and the display. | 06-25-2009 |
| 20090158085 | POWER SAFE TRANSLATION TABLE OPERATION IN FLASH MEMORY - Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error. | 06-18-2009 |
| 20090158023 | ADAPTIVE SYSTEM BOOT ACCELERATOR FOR COMPUTING SYSTEMS - An acceleration mechanism for boot-up processing in a computing system is provided. The acceleration mechanism relies on recording most, if not all, of the read transactions, associated with requests and retrievals made during a boot-up and, in some aspects most, if not all, of the write transactions, associated with requests and stores made during a shutdown process. Prior to executing the boot-up process, data associated with the transactions is pre-fetched based on the recorded information and used to make the requests or information retrievals during the ensuing boot-up process. Additionally, since the mechanism of the present innovation provides for continual recording and the transaction data, the acceleration of the boot-up process can be adaptive even if hardware additions/changes or any other changes that affect the boot-up or shutdown process occur. | 06-18-2009 |
| 20090158005 | CLOCK ENCODED PRE-FETCH TO ACCESS MEMORY DATA IN CLUSTERING NETWORK ENVIRONMENT - Systems and/or methods that facilitate reading data from a memory component associated with a network are presented. A pre-fetch generation component generates a pre-fetch request based in part on a received read command. To facilitate a reduction in latency associated with transmitting the read command via an interconnect network component to which the memory component is connected, the pre-fetch request is transmitted directly to the memory component bypassing a portion of the interconnect network component. The memory component specified in the pre-fetch request receives the pre-fetch request and reads the data stored therein, and can store the read data in a buffer and/or transmit the read data to the requester via the interconnect network component, even though the read command has not yet reached the memory component. The read data is verified by comparison with the read command at a convergence point. | 06-18-2009 |
| 20090157948 | INTELLIGENT MEMORY DATA MANAGEMENT - Systems and/or methods that facilitate data management on a memory device are presented. A data management component can log and tag data creating data tags. The data tags can comprise static metadata, dynamic metadata or a combination thereof. The data management component can perform file management to allocate placement of data and data tags to the memory or to erase data from the memory. Allocation and erasure are based in part on the characteristics of the data tags, and can follow embedded rules, an intelligent component or a combination thereof. The data management component can provide a search activity that can utilize the characteristics of the data tags and an intelligent component. The data management component can thereby optimize the useful life, increase operating speed, improve accuracy and precision, improve efficiency of non-volatile (e.g., flash) memory and provide improved functionality to memory devices. | 06-18-2009 |
| 20090155992 | HIGH K STACK FOR NON-VOLATILE MEMORY - A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material. | 06-18-2009 |
| 20090155726 | METHODS OF FORMING ELECTRONIC DEVICES BY ION IMPLANTING - A method of forming an electronic device is provided that includes forming a resist layer over a substrate having a first region, a second region, and a third region. The method further includes directing radiation through a reticle, wherein the reticle comprises different radiation zones having significantly different transmission values with respect to each other, and the first region is exposed to a significantly different amount of radiation as compared to the second region. The method also includes removing part of the resist layer to leave a remaining portion such that the second region of the resist layer is significantly thinner than the third region of the resist layer, and then ion implanting the substrate while the remaining portion of the resist layer overlies the substrate to form a first implant region and a second implant region having different depths. | 06-18-2009 |
| 20090154261 | REFERENCE-FREE SAMPLED SENSING - Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells. | 06-18-2009 |
| 20090154260 | SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS - Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli | 06-18-2009 |
| 20090154251 | ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT - Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states. | 06-18-2009 |
| 20090154246 | PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS - Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed. | 06-18-2009 |
| 20090154235 | REDUCED STATE QUADBIT - A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell. | 06-18-2009 |
| 20090154234 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 06-18-2009 |
| 20090154215 | REDUCING NOISE AND DISTURBANCE BETWEEN MEMORY STORAGE ELEMENTS USING ANGLED WORDLINES - Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and other segments that are angled from a direction parallel to the x-axis based in part on a predetermined angle. Adjacent storage elements can be positioned at respective ends of an angled segment of a wordline to facilitate increasing the distance between such storage elements, as compared to the distance between storage elements associated with an orthogonal memory array, where the increase in distance can be based in part on the predetermined angle. The size of the memory array can be the same or substantially the same size, as compared to an orthogonal memory array. | 06-18-2009 |
| 20090152669 | SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT - Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss. | 06-18-2009 |
| 20090152617 | HETERO-STRUCTURE VARIABLE SILICON RICHNESS NITRIDE FOR MLC FLASH MEMORY DEVICE - Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n-1th charge storage layer is higher than a k-value of an nth charge storage layer; n-1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers. | 06-18-2009 |
| 20090150646 | MEMORY ARRAY SEARCH ENGINE - Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page. | 06-11-2009 |
| 20090147589 | Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory - A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase. | 06-11-2009 |
| 20090147587 | CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE - Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass. | 06-11-2009 |
| 20090147585 | FLEXIBLE WORD LINE BOOSTING ACROSS VCC SUPPLY - Systems and methods for producing a boosted voltage which can be used as a boosted word line voltage for read mode operations of memory cells are disclosed. The system contains a VCC comparator, a look up table, and a boosting circuit including a set of boosting capacitors. The look up table has a list of trim codes that indicates desired boosting ratios. The boosting ratio can vary depending on a level of a supply voltage to provide a sufficient word line voltage, thereby preventing and/or mitigating delay in reading operations. The number of the capacitors in the boosting circuit can be predetermined to be turned on or off according to the trim code. Accordingly, the voltage boost circuit provides a sufficient boosted word line voltage to a core cell gate with flexibility despite fluctuation of the supply voltage level. | 06-11-2009 |
| 20090146201 | WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTIPLE CHARGE STORAGE ELEMENTS IN AN UNDERCUT REGION - A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided. | 06-11-2009 |
| 20090144486 | DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT - Conventional processor and memory configurations place holes into silicon or use expensive multi-layer-laminates/substrates to connect the processor with memory. Using a direct contact between the memory and processor allows for signaling between the two units. By judicious arrangement of the contact areas as well as employing other structures such as carriers and redistributors, adequate power and ground supply can be maintained for the processor. Therefore, there is little-to-no damage done to the silicon and expensive multi-layer-laminates/substrates can be avoided. Furthermore, there can be faster processing speeds since the memory and processor are close together. | 06-04-2009 |
| 20090144045 | DATA TRANSMISSION SYSTEM-ON-CHIP MEMORY MODEL BASED VALIDATION - Systems and/or methods that facilitate simulation, verification, and optimization of a data transmission system by utilizing simulation memory component(s) are presented. A simulation memory component can be used to replace memory components and/or hardware components to facilitate early simulation and/or verification of the overall interconnectivity of the system. A simulation memory component(s) can be configured to emulate various sizes of memory components associated with the system. Data throughput can be measured during simulation, and the depth and/or width associated with a simulation memory component can be adjusted to facilitate obtaining a desired data throughput based in part on predefined data throughput criteria. | 06-04-2009 |
| 20090142473 | Method of operating a processing chamber used in forming electronic devices - Provided herein is a method of processing an electronic device including operating a processing chamber at a first temperature while a workpiece is being processed and removing the workpiece and a carrier holding the workpiece from the processing chamber while decreasing the temperature within the processing chamber to a second temperature significantly lower than the first temperature. The method also includes increasing the temperature within the processing chamber to a third temperature significantly greater than the second temperature and significantly less than the first temperature while the processing chamber has no workpiece or carrier within. | 06-04-2009 |
| 20090140325 | FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE - A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness. | 06-04-2009 |
| 20090139572 | WEAVABLE FIBER PHOTOVOLTAIC COLLECTORS - Photovoltaic fibers and methods of making photovoltaic fibers are provided. The photovoltaic fiber contains a core, bottom metal-semiconductor compounds over the core, a semiconductor layer comprising semiconductor elements and insulating materials over the bottom metal-semiconductor compounds, and upper metal-semiconductor compounds over the semiconductor layer. The photovoltaic fiber can be weavable. Fabrics including the photovoltaic fibers can be utilized in any suitable application or photovoltaic collector. | 06-04-2009 |
| 20090138628 | MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS - Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers. | 05-28-2009 |
| 20090135659 | ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE - Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift | 05-28-2009 |
| 20090129172 | HIGH RELIABLE AND LOW POWER STATIC RANDOM ACCESS MEMORY - Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading. | 05-21-2009 |
| 20090121361 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device has a first semiconductor chip | 05-14-2009 |
| 20090119447 | CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY - Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring. | 05-07-2009 |
| 20090117734 | PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS - A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed. | 05-07-2009 |
| 20090114542 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING A CONDUCTIVE LAYER OVER A SEED LAYER - A process of forming an electronic device can include placing a seed layer into an electroplating solution within an electroplating tool. The electroplating tool can include a first electrode and a second electrode, wherein the first electrode is electrically connected to the seed layer. The process can also include depositing a first portion of a conductive layer using a first signal of a first type (e.g., direct current) between the first electrode and a second electrode, and depositing a second portion of the conductive layer over the first portion of the conductive layer, using a second signal of a second type (e.g., alternating current) between the first electrode and the second electrode of the electroplating tool. | 05-07-2009 |
| 20090113272 | ERROR CORRECTION CODING IN FLASH MEMORY DEVICES - Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to be written to determine whether parity code can be written for the incoming data and/or whether error correction can be enabled with respect to the incoming data. Error correction can be enabled when an indicator bit associated with the data is unprogrammed (e.g., bit set to ‘1’ state) and can be disabled by programming the indicator bit (e.g., bit set to a ‘0’ state). | 04-30-2009 |
| 20090111265 | SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-30-2009 |
| 20090109769 | SIGNAL DESCRAMBLING DETECTOR - Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The descrambler component can determine the bit order of the data signals based on such patterns and can generate a transformation function that can facilitate rearranging data, which can be received from or sent to the memory device, into a predetermined bit order. | 04-30-2009 |
| 20090109760 | DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES - Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell. | 04-30-2009 |
| 20090109758 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE - A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells. | 04-30-2009 |
| 20090109742 | CONTROL OF TEMPERATURE SLOPE FOR BAND GAP REFERENCE VOLTAGE IN A MEMORY DEVICE - Systems and/or methods are presented that can facilitate regulating performance of operations in a memory device based on controlling an operating temperature slope associated with the memory device. A regulator component can facilitate controlling the operating temperature slope level and controlling a reference voltage(s) associated with a word-line(s) and/or bit-line(s) to facilitate execution of operations in a memory, while also controlling a respective current level(s) associated with the reference voltage to minimize errors in the memory or harm to the memory. The reference voltage can be controlled based on a first resistance and the current level can be controlled based on a second resistance that can be based on the first resistance. An analyzer component can facilitate determining a desired operating temperature slope level. Trim bits can be employed to facilitate setting the first resistance and/or the second resistance. | 04-30-2009 |
| 20090109721 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE. - An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines. | 04-30-2009 |
| 20090108330 | SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS - Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes. | 04-30-2009 |
| 20090106626 | LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE - An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output. | 04-23-2009 |
| 20090106577 | OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY - Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the determination of different clock frequencies that an electronic device(s) can accommodate for transmitting data to and receiving data from the electronic device. The host component can facilitate transmitting data to the electronic device at a higher clock frequency than the clock frequency utilized to transmit data from the electronic device to the host component in order to facilitate programming large amounts of data to the electronic device efficiently. The host component can select a downlink and/or uplink clock frequency based in part on the type of electronic device(s), the size of a memory buffer associated with the nonvolatile memory device, and/or a type of protocol associated with the electronic device. | 04-23-2009 |
| 20090106563 | TAMPER REACTIVE MEMORY DEVICE TO SECURE DATA FROM TAMPER ATTACKS - Systems and methods that can facilitate securing data associated with a memory from tampering are presented. A counter tamper component can detect tamper attacks or tamper attempts associated with a memory and/or data stored therein or associated therewith and reacts to such tamper attacks/attempts, as the counter tamper component can provide evidence of, provide a response to, and/or resist tamper attacks/attempts. The counter tamper component can be associated with a memory module that includes a memory device(s) module and is contained in an electronic device and the memory module can change a color state to provide evidence of tampering. A window component is positioned on the casing of the electronic device so that the memory module is visible to the user so the user can perceive that a tamper attack associated with the module has occurred. | 04-23-2009 |
| 20090106483 | SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES - Systems and/or methods that facilitate programming content to a plurality of nonvolatile memory devices are presented. A wafer program component facilitates programming content to a plurality of memory devices contained on a wafer. The wafer program component can interface with the wafer and can employ parallel processes to program the memory devices on the wafer at substantially the same time. The content programmed to the memory devices can be the same content or different content. A portion of the content can be access-restricted where authentication information is to be provided in order to be granted access to such content, where access-restricted content can include content associated with subscriptions or personal information of a user(s). | 04-23-2009 |
| 20090106481 | HYBRID FLASH MEMORY DEVICE - A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage. along with fast programming/erasure speeds and fast random access speeds. | 04-23-2009 |
| 20090104432 | PHOTOVOLTAIC THIN COATING FOR COLLECTOR GENERATOR - Photovoltaic coatings and methods of making photovoltaic coatings are provided. The photovoltaic coating contains a semiconductor layer containing semiconductor elements such as silicon particles between bottom metal-semiconductor compounds and upper metal-semiconductor compounds. The upper metal-semiconductor compounds can exist at uppermost boundary portions between semiconductor elements and not substantially over uppermost surfaces of the semiconductor elements. The method can involve forming a semiconductor layer comprising semiconductor elements such as silicon particles over a conductive layer; forming first metal-semiconductor compounds at a bottom surface of the semiconductor layer; and forming second metal-semiconductor compounds at uppermost boundary portions between the semiconductor elements. | 04-23-2009 |
| 20090101963 | SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS - Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes. | 04-23-2009 |
| 20090097637 | RANDOMIZED RSA-BASED CRYPTOGRAPHIC EXPONENTIATION RESISTANT TO SIDE CHANNEL AND FAULT ATTACKS - Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates data encryption, data decryption, and/or generation of digital signatures, associated with messages. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and/or generation of digital signatures by exponentiating exponents associated with messages. A random number is generated and utilized to randomize the value of a message. After an exponentiation is performed on the randomized message value, intermediate results can be analyzed to determine if there was error in the exponentiation. If there was no error in the exponentiation, a final value of the exponentiation is determined and provided as output as decrypted data or a digital signature; if there is error, an “error” output can be provided. | 04-16-2009 |
| 20090081824 | STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING - The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device. | 03-26-2009 |
| 20090067617 | SECURE MODULAR EXPONENTIATION BY RANDOMIZATION OF EXPONENT SCANNING - Systems and/or methods that facilitate secure electronic communication of data are presented. A cryptographic component facilitates securing data associated with messages in accordance with a cryptographic protocol. The cryptographic component includes a randomized exponentiation component that facilitates decryption of data and generation of digital signatures by exponentiating exponents associated with messages. An exponent is divided into more than one subexponent at an exponent bit that corresponds to a random number. Exponentiation of the first subexponent can be performed based on a left-to-right-type of exponentiation algorithm, and exponentiation of the second subexponent can be performed based on a right-to-left square-and-multiply-type of exponentiation algorithm. The final value is based on the exponentiations of the subexponents and can be decrypted data or a digital signature, which can be provided as an output. | 03-12-2009 |
| 20090061650 | SACRIFICIAL NITRIDE AND GATE REPLACEMENT - Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved. | 03-05-2009 |
| 20090061631 | GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT - Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide. | 03-05-2009 |
| 20090051051 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip. | 02-26-2009 |
| 20090051043 | DIE STACKING IN MULTI-DIE STACKS USING DIE SUPPORT MECHANISMS - Systems, methods, and devices that facilitate stacking dies in a multi-die stack using die support mechanisms (DSMs) are presented. DSMs are employed to place a smaller die and attached wires underneath a larger die. DSMs can be placed on each side of the smaller die where the larger die overhangs when placed above the smaller die. The DSMs can be optimally sized to provide support to the larger die to reduce overhang and sagging, while providing a buffer region to protect the smaller die and associated wires. DSMs are employed to facilitate stacking dies that are the same or similar in size by placing a DSM between the dies. The DSM can be optimally sized to provide a buffer region to protect the wires bonded to the top side of the lower die from the upper die, while minimizing overhang to provide support to the upper die. | 02-26-2009 |
| 20090050471 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS - A process of forming an electronic device can include depositing a first layer over a substrate and depositing a second layer over the first layer. In one embodiment, depositing the first layer is performed at a first alternating current (“AC”) power, and depositing the second layer is performed at a second AC power that is different from the first AC power. In another embodiment, the first layer is formed by a physical vapor deposition technique at a first power sufficient to remove the insulating layer using first metal ions, wherein the first layer includes an overhanging portion extending over the bottom of the opening. In a further embodiment, the second layer is formed by the physical vapor deposition technique using second metal ions and a second power sufficient to reduce a lateral dimension of the overhanging portion. | 02-26-2009 |
| 20090049231 | EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION - Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for programming, erase, and soft programming operations at address bit combinations available for the respective operations. The characterization component can utilize external address bits that can be fixed when performing the operations to minimize disruption to the drain voltage measurement flow. The characterization component can detect when a particular operation has already been performed based in part on an applicable portion of the address bit combination associated with such operation, and can bypass such operation at that address bit combination to proceed to the next operation that has yet to be performed thereby efficiently setting and measuring drain voltage levels for various operations and trim settings to characterize the memory device. | 02-19-2009 |
