| SKYWORKS SOLUTIONS, INC. Patent applications |
| Patent application number | Title | Published |
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| 20130119535 | FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE - Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. | 05-16-2013 |
| 20130116017 | APPARATUS AND METHODS FOR POWER AMPLIFIERS - Apparatus and methods for power amplifiers are disclosed. In one embodiment, a power amplifier circuit assembly includes a power amplifier and an impedance matching network. The impedance matching network is operatively associated with the power amplifier and is configured to provide a load line impedance to the power amplifier between about 6 Ω and about 10 Ω. The impedance matching network includes a fundamental matching circuit and one or more termination circuits, and the fundamental matching circuit and each of the of the one or more termination circuits include separate input terminals for coupling to an output of the power amplifier so as to allow the fundamental matching circuit and each of the one or more termination circuits to be separately tuned. | 05-09-2013 |
| 20130115895 | DEVICES AND METHODS RELATED TO FIELD-EFFECT TRANSISTOR STRUCTURES FOR RADIO-FREQUENCY APPLICATIONS - Disclosed are devices and methods related to field-effect transistor (FET) structures configured to provide reduced per-area values of resistance in the linear operating region (Rds-on). Typical FET devices such as silicon-on-insulator (SOI) device require larger device sizes to desirably lower the Rds-on values. However, such increases in size result in undesirably larger die sizes. Disclosed are various examples of shapes of source, drain, and corresponding gate that yield reduced Rds-on values without having to increase the device size. In some implementations, such FET devices can be utilized in high power radio-frequency (RF) switching applications. | 05-09-2013 |
| 20130115160 | SPECIALTY MATERIALS PROCESSING TECHNIQUES FOR ENHANCED RESONANT FREQUENCY HEXAFERRITE MATERIALS FOR ANTENNA APPLICATIONS AND OTHER ELECTRONIC DEVICES - Processing techniques for forming a textured hexagonal ferrite materials such as Z-phase barium cobalt ferrite Ba | 05-09-2013 |
| 20130113575 | RADIO-FREQUENCY SWITCHES HAVING EXTENDED TERMINATION BANDWIDTH AND RELATED CIRCUITS, MODULES, METHODS, AND SYSTEMS - Circuits and methods related to a switch having extended termination bandwidth are disclosed. A switch having an input end and an output end, and capable of being in an ON state and an OFF state, can include a termination circuit configured to yield an extended frequency bandwidth in which a desired OFF state termination impedance is provided. A termination circuit may include two or more electrically parallel resistor-capacitor branches coupled to the switch input or output end. A switch termination circuit may provide an OFF state termination impedance that is substantially equal to the switch ON state termination impedance. Also, a termination circuit may enable a desired termination impedance without sacrificing other switch performance features, including insertion loss, isolation, or VSWR difference between ON and OFF states. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of fabrication. | 05-09-2013 |
| 20130100993 | DUAL MODE POWER AMPLIFIER CONTROL INTERFACE WITH A THREE-MODE GENERAL PURPOSE INPUT/OUTPUT INTERFACE - In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a three-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier. | 04-25-2013 |
| 20130090077 | GAIN CONTROL SYSTEMS AND METHODS FOR CONTROLLING AN ADJUSTABLE POWER LEVEL - A system, such as a transceiver, for controlling an adjustable power level includes first and second power detectors, a network of attenuators, a compensator, a comparator, and a controller. The first power detector measures the power of a signal. The network of attenuators receives the signal and generates an attenuated signal. The compensator receives the attenuated signal and generates a compensated signal. The second power detector measures the power of the compensated signal. The comparator receives the respective outputs from the first and second power detectors and generates a first error signal. The controller enables the fixed attenuation, correspondingly adjusts the variable attenuation, receives a second error signal, and provides a control signal to the network of attenuators to nullify an attenuation mismatch introduced between the fixed attenuation and the variable attenuation. A corresponding method for controlling an adjustable power level is also disclosed. | 04-11-2013 |
| 20130078929 | APPARATUS AND METHODS FOR VARIABLE DC BIAS TO IMPROVE LINEARITY IN SIGNAL PROCESSING CIRCUITS - To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a variable current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region. | 03-28-2013 |
| 20130078928 | APPARATUS AND METHODS FOR FIXED DC BIAS TO IMPROVE LINEARITY IN SIGNAL PROCESSING CIRCUITS - To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a fixed current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region. | 03-28-2013 |
| 20130069622 | ELECTRON RADIATION MONITORING SYSTEM TO PREVENT GOLD SPITTING AND RESIST CROSS-LINKING DURING EVAPORATION - Disclosed herein are systems and methods for in-situ measurement of impurities on metal slugs utilized in electron-beam metal evaporation/deposition systems, and for increasing the production yield of a semiconductor manufacturing processes utilizing electron-beam metal evaporation/deposition systems. A voltage and/or a current level on an electrode disposed in a deposition chamber of an electron-beam metal evaporation/deposition system is monitored and used to measure contamination of the metal slug. Should the voltage or current reach a certain level, to the deposition is completed and the system is inspected for contamination. | 03-21-2013 |
| 20130059554 | MULTI-MODE POWER SUPPLY REGULATOR FOR POWER AMPLIFIER CONTROL - A radio frequency (RF) power amplification system in which a combination of a linear voltage regulator having a PFET pass device and a DC-DC converter having an NFET pass device is used to supply power to an RF power amplifier. The RF power amplifier receives power from either the linear voltage regular and its associated PFET pass device or the DC-DC converter and its NFET pass device, depending upon the condition of a mode signal. | 03-07-2013 |
| 20130057451 | TRANSMISSION LINE FOR HIGH PERFORMANCE RADIO FREQUENCY APPLICATIONS - This disclosure relates to a transmission line for high performance radio frequency (RF) applications. One such transmission line can include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer can have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the transmission line can include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer. | 03-07-2013 |
| 20130052968 | REDUCED CLOCK FEED-THROUGH SYSTEMS, METHODS AND APPARATUS - Implementations of radio frequency switch controllers within the scope of the appended claims are configured to reduce the impact of the clock signal induced spurs. In particular, implementations of switch controllers described herein include a poly-phase clocking scheme, as opposed to a single phase to clock the charge pump stages of an negative voltage generator. In some implementations poly-phase clocking schemes reduce the clock signal induced spurs and may preclude the need for additional on-chip or off-chip decoupling capacitors that add to the cost and physical size of a complete front end module solution. | 02-28-2013 |
| 20130050041 | RARE EARTH REDUCED GARNET SYSTEMS AND RELATED MICROWAVE APPLICATIONS - Disclosed are synthetic garnets and related devices that can be used in radio-frequency (RF) applications. In some embodiments, such RF devices can include garnets having reduced or substantially nil Yttrium or other rare earth metals. Such garnets can be configured to yield high dielectric constants, and ferrite devices, such as TM-mode circulators/isolators, formed from such garnets can benefit from reduced dimensions. Further, reduced or nil rare earth content of such garnets can allow cost-effective fabrication of ferrite-based RF devices. In some embodiments, such ferrite devices can include other desirable properties such as low magnetic resonance linewidths. Examples of fabrication methods and RF-related properties are also disclosed. | 02-28-2013 |
| 20130049859 | SATURATION PROTECTION OF A REGULATED VOLTAGE - A system for preventing power amplifier supply voltage saturation includes a multiple stage voltage regulator configured to provide a regulated voltage, a power amplifier configured to receive the regulated voltage, and a saturation protection circuit configured to apply a current into a first stage of the multiple stage voltage regulator when the regulated voltage reaches a reference voltage, the applied current causing a subsequent stage of the multiple stage voltage regulator to prevent the regulated voltage from exceeding the reference voltage. | 02-28-2013 |
| 20130037924 | ANTENNA SWITCH MODULES AND METHODS OF MAKING THE SAME - Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die. | 02-14-2013 |
| 20130029620 | LOW VARIATION CURRENT MULTIPLIER - Aspects of the present disclosure relate to a current multiplier that can generate an output current with high linearity and/or high temperature compensation. Such current multipliers can be implemented by complementary metal oxide semiconductor (CMOS) circuit elements. In one embodiment, the current multiplier can include a current divider and a core current multiplier. The current divider can generate a divided current by dividing an input current by an adjustable division ratio. The division ratio can be adjusted, for example, based on a comparison of the input current with a reference current. The core current multiplier can generate the output current based on multiplying the divided current and a different current. According to certain embodiments, the output current can be maintained within a predetermined range as the input current to the current divider varies within a relatively wide range. | 01-31-2013 |
| 20130029619 | SIGNAL PATH TERMINATION - This disclosure relates to a harmonic termination circuit that is separate from a load line. In one embodiment, the load line is configured to match an impedance at the power amplifier output at a fundamental frequency of the power amplifier output and the harmonic termination circuit is configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. According to certain embodiments, the load line and the harmonic termination circuit can be electrically coupled to the power amplifier output external to a power amplifier die via different output pins of the power amplifier die. | 01-31-2013 |
| 20130021219 | RADIO-FREQUENCY MODULES HAVING TUNED SHIELDING-WIREBONDS - Disclosed are devices and methods related to radio-frequency (RF) shielding of RF modules. In some embodiments, tuned shielding can be achieved by utilizing different structures and/or arrangements of shielding-wirebonds to increase shielding in areas where needed, and to decrease shielding where not needed. Such tuning of shielding requirements can be obtained by measuring RF power levels at different locations of a module having a given design. Such tuned RF shielding configurations can improve the overall effectiveness of shielding, and can also be more cost effective to implement. | 01-24-2013 |
| 20120329635 | NOVEL ENHANCED HIGH Q MATERIAL COMPOSITIONS AND METHODS OF PREPARING SAME - A framework for developing high quality factor (Q) material for electronic applications in the radio frequency range is provided. In one implementation, ceramic materials having a tungsten bronze crystal structure is modified by substituting one or more elements at one or more lattice sites on the crystal structure. The substitute elements are selected based on the ionic radius and other factors. In other implementations, the modified ceramic material is prepared in combination with compositions such as rutile or a perovskite to form a orthorhombic hybrid of perovskite and tetragonal tungsten bronze. | 12-27-2012 |
| 20120322206 | METHOD FOR WAFER LEVEL PACKAGING OF ELECTRONIC DEVICES - A method of packaging a semiconductor device that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device. | 12-20-2012 |
| 20120319747 | PHASE-LOCKED LOOP LOCK DETECT - Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time. | 12-20-2012 |
| 20120293254 | VARIABLE SWITCHED DC-TO-DC VOLTAGE CONVERTER - A voltage converter can be switched among two or more modes to produce an output voltage tracking a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. One or more voltages generated from a power supply voltage, such as a battery voltage, can be compared with the reference voltage to determine whether to adjust the mode. The reference voltage can be independent of the power supply voltage. | 11-22-2012 |
| 20120286878 | APPARATUS AND METHODS FOR ELECTRONIC AMPLIFICATION - Apparatus and methods for electronic amplification are disclosed herein. In certain implementations, an amplifier is provided for amplifying a RF signal, and the amplifier includes a first transistor and a second transistor electrically connected in a Darlington configuration. The first and second transistors can be, for example, bipolar or field effect transistors and the first transistor can amplify an input signal and provide the amplified input signal to the second transistor. The first and second transistors are electrically connected to a power low node such as a ground node through first and second bias circuits, respectively. In certain implementations, the first transistor includes an inductor disposed in the path from the first transistor to the power low voltage. By including the inductor in the path from the first transistor to the ground node, the third order distortion of the amplifier can be improved. | 11-15-2012 |
| 20120286873 | APPARATUS AND METHODS FOR BIASING POWER AMPLIFIERS - Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit. The primary biasing circuit is configured to use the correction current to correct for a variation in gain of the power amplifier when the power amplifier is enabled. | 11-15-2012 |
| 20120280760 | APPARATUS AND METHODS RELATED TO FERRITE BASED CIRCULATORS - Apparatus and methods related to ferrite based circulators are disclosed. A ferrite disk used in a circulator can be configured to reduce intermodulation distortion when routing radio-frequency signals having closely spaced frequencies. Such a reduction in intermodulation distortion can be achieved by adjusting magnetization at the edge portion of the ferrite disk. By way of an example, a ferrite disk with a reduced saturation magnetization (4 PiMs) edge portion can reduce intermodulation distortion. Example configurations with such a reduced 4 PiMs edge portions are disclosed. | 11-08-2012 |
| 20120280730 | APPARATUS AND METHODS FOR ADJUSTING VOLTAGE CONTROLLED OSCILLATOR GAIN - Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations. | 11-08-2012 |
| 20120269240 | APPARATUS AND METHODS FOR ENVELOPE TRACKING - Apparatus and methods for envelope tracking are disclosed. In one embodiment, a power amplifier system including a power amplifier and an envelope tracker is provided. The power amplifier is configured to amplify a radio frequency (RF) signal, and the envelope tracker is configured to control a supply voltage of the power amplifier using an envelope of the RF signal. The envelope tracker includes a buck converter for generating a buck voltage from a battery voltage and a digital-to-analog conversion (DAC) module for adjusting the buck voltage based on the envelope of the RF signal to generate the supply voltage for the power amplifier. | 10-25-2012 |
| 20120249273 | MAGNETIC-DIELECTRIC ASSEMBLY - A magnetic-dielectric disc assembly includes a magnetic ceramic disc coaxially secured within a dielectric ceramic ring by an adhesive that includes a powdered ceramic in an epoxy matrix. The powdered ceramic is selected from the group consisting of alumina, titania, silica, and zirconia. The magnetic-dielectric disc assembly can be used as a component of, for example, a circulator, isolator, or similar electrical assembly. | 10-04-2012 |
| 20120242379 | VARIABLE FREQUENCY CIRCUIT CONTROLLER - Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator. | 09-27-2012 |
| 20120235737 | APPARATUS AND METHODS FOR CAPACITIVE LOAD REDUCTION - Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a power amplifier configured to amplify a radio frequency (RF) signal of a first frequency and an envelope tracker configured to control a supply voltage of the power amplifier using an envelope of the RF signal. The power amplifier system further includes an inductor electrically connected between the power amplifier and the envelope tracker and a capacitor electrically connected between the power amplifier and the envelope tracker. The capacitor and the inductor are configured to have a resonance near the first frequency. | 09-20-2012 |
| 20120235731 | CONTINUOUS TUNABLE LC RESONATOR USING A FET AS A VARACTOR - A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET. | 09-20-2012 |
| 20120233374 | DUAL MODE SERIAL/PARALLEL INTERFACE AND USE THEREOF IN IMPROVED WIRELESS DEVICES AND SWITCHING COMPONENTS - Systems, methods, and devices for communicating with a serial/parallel interface are described herein. In an aspect, a wireless device includes a transceiver configured to output a plurality of transmission paths, and an antenna configured to output a signal corresponding to at least one of the transmission paths. The wireless device further includes a wireless switching component including a radio-frequency switch configured to selectively connect the antenna to one of the transmission paths, a plurality of signal pins, a serial interface including a plurality of serial inputs electrically coupled to at least one pin of the plurality of signal pins, a parallel interface including a plurality of parallel inputs electrically coupled to at least one pin of the plurality of signal pins, a decoder, and a level shifter configured to control the radio-frequency switch, the at least one pin electrically coupled to both a serial input and a parallel input. | 09-13-2012 |
| 20120225629 | SYSTEM AND METHOD FOR TUNING A RADIO RECEIVER - A system for tuning a radio receiver includes a radio receiver configured to provide a downconverted digital error signal, a digital synthesizer circuit configured to generate a first local oscillator control signal, a digital automatic frequency control (AFC) circuit configured to generate a second local oscillator control signal, wherein the digital synthesizer circuit is enabled to generate the first local oscillator control signal when the digital AFC circuit is disabled, the first local oscillator control signal corresponds to an estimate of a desired local oscillator frequency, the digital AFC circuit is enabled to generate the second local oscillator control signal when the digital synthesizer circuit is disabled and the second local oscillator control signal corresponds to the desired local oscillator frequency. | 09-06-2012 |
| 20120223788 | SEAL RING INDUCTOR AND METHOD OF FORMING THE SAME - Apparatuses and methods for providing inductance are disclosed. In one embodiment, a method for providing an inductor includes forming an electrical circuit on a substrate, forming a seal ring around the perimeter of the electrical circuit, providing a break in at least one layer of the seal ring, and electrically connecting the seal ring such that the seal ring operates as an inductor. | 09-06-2012 |
| 20120223422 | APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad. | 09-06-2012 |
| 20120222892 | WIRE BOND PAD SYSTEM AND METHOD - To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material. | 09-06-2012 |
| 20120218039 | SYSTEMS AND METHODS FOR SATURATION CORRECTION IN A POWER CONTROL LOOP - A power amplification circuit includes a power amplifier, an RF detector, an error amplifier, a saturation detector, and an offset circuit. The power amplifier provides an amplified signal based on an input signal and a gain control signal. The RF detector provides a detection signal indicative of a logarithm of the power of the amplified signal. The error amplifier provides the gain control signal based on an amplification control signal and the detection signal. The saturation detector provides a saturation signal in response to the gain control signal differing from a reference signal by less than a first predetermined voltage. The offset circuit decreases a voltage level of the amplification control signal by up to a second predetermined voltage in response to the saturation signal and the amplification control signal differing from the detection signal by less than the second predetermined voltage. | 08-30-2012 |
| 20120211888 | APPARATUS AND METHODS FOR UNIFORM METAL PLATING - Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate. | 08-23-2012 |
| 20120202438 | SYSTEM AND METHOD OF TRANSISTOR SWITCH BIASING IN A HIGH POWER SEMICONDUCTOR SWITCH - A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity. | 08-09-2012 |
| 20120200354 | APPARATUS AND METHODS FOR ENVELOPE TRACKING CALIBRATION - Apparatus and methods for envelope tracking calibration are provided. In one embodiment, a method of calibrating an envelope tracker having an envelope shaping table generated at a desired gain compression of a power amplifier is provided. The method includes generating a supply voltage for the power amplifier using the envelope tracker, operating the supply voltage of the power amplifier at a first voltage level associated with substantially no gain compression of the power amplifier, and measuring an output power of the power amplifier at the first voltage level. The method further includes decreasing a voltage level of the supply voltage one or more times and measuring the output power at each voltage level, determining a second voltage level of the power amplifier associated with a gain compression equal to about that of the desired gain compression, and calibrating the envelope tracker based on the determination. | 08-09-2012 |
| 20120190313 | COMPACT SWITCH WITH ENHANCED LINEARITY PERFORMANCE - A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates. | 07-26-2012 |
| 20120190311 | FREQUENCY GENERATOR AND GAIN CALIBRATION TECHNIQUE FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP - A frequency generator includes a phase-locked loop (PLL) and a voltage controlled oscillator (VCO), where the VCO is arranged to receive low-pass data via a first input and high-pass data at a second input. The first input is coupled to a first set of varactors in the VCO. The second input is coupled to a second set of varactors in the VCO. A controller sets the input voltage at the first input and directs a charge pump to operate in a tri-state mode that opens the feedback loop of the PLL. The controller applies different voltages via the second input and measures the change in output frequency. A present gain of the VCO is determined from the ratio of the change in frequency and the change in voltage at the second input and is used to calibrate a portable transceiver. | 07-26-2012 |
| 20120185623 | APPARATUS AND METHODS FOR SERIAL INTERFACES - Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers. | 07-19-2012 |
| 20120182074 | SINGLE DIE POWER AMPLIFIER WITH CLOSED LOOP POWER CONTROL - An apparatus on a single integrated circuit (IC) die includes a multiple stage power amplifier having at least first and second stages, a multiple stage voltage regulator for providing a regulated voltage signal to the at least first and second stages of the multiple stage power amplifier, a power coupler for providing a portion of a power output of the multiple stage power amplifier to a power detector, the power detector for developing a power detect signal, and a power control loop including at least the second stage and an output stage of the multiple stage power amplifier, the power coupler, the power detector, and at least one stage of the multiple stage voltage regulator, the power control loop controlling only the second stage and the output stage of the multiple stage power amplifier. | 07-19-2012 |
| 20120178384 | APPARATUS AND METHODS FOR BIASING A POWER AMPLIFIER - Apparatus and methods for biasing a power amplifier are provided. In one embodiment, a packaged circuit includes a power amplifier, a bond wire electrically connected between a system voltage source and a supply input of the power amplifier, a current source, a reference resistor electrically connected between the system voltage source and the current source, and a comparator. The comparator is configured to compare a sense voltage that is based on a voltage across the bond wire to a reference voltage that is based on a voltage across the reference resistor. The comparator is configured to generate a saturation control signal for clamping a bias current of the power amplifier when the sense voltage exceeds the reference voltage. | 07-12-2012 |
| 20120171973 | SYSTEMS AND METHODS FOR IMPLEMENTING A HARMONIC REJECTION MIXER - Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics. | 07-05-2012 |
| 20120171971 | LOW NOISE RF DRIVER - A low noise RF driver circuit including at least two series-coupled driver stages which receive a frequency modulated signal and an amplitude modulated signal that is applied to the supply voltage input of the driver stages, and provide a combined output signal. The RF driver circuit can be implemented in CMOS technology and integrated with other components of an RF communication subsystem, such as an RF transceiver circuit and power amplifier. Each driver stage includes a complementary pair of transistors with source degeneration resistors for linearity and gain control. | 07-05-2012 |
| 20120171968 | DUAL MODE TRANSCEIVER - A circuit is disclosed with an external coupling port for coupling to an external antenna, for example. The circuit has an FDD receive path including a narrowband passband filter. The circuit has a TDD receive path bypassing the narrowband passband filter but relying on a same amplifier. The circuit also has an FDD transmit path including a narrowband passband filter. The circuit has a TDD transmit path bypassing the narrowband passband filter of the FDD transmit path but relying on a same transmit amplifier. A switching configuration allows the circuit to operate in TDD mode, alternating between the TDD receive path and the TDD transmit path and in the FDD mode wherein the FDD transmit and receive paths are simultaneously coupled to the external coupling port. | 07-05-2012 |
| 20120171967 | THIN FILM RESISTOR HAVING IMPROVED POWER HANDLING CAPABILITY - Designs and methodologies related to attenuators having a thin-film resistor assembly are disclosed. In some embodiments, the thin-film assembly can include a first and second thin-film resistor, each having a main portion with an input end and an output end. The input end of the first thin-film resistor is interconnected to the input end of the second thin-film resistors, and the output end of the first thin-film resistor is interconnected to the output end of the second thin-film resistor. The first and second thin-film resistors are disposed relative to one another so as to define a separation. The separation region reduces the likelihood of hot spot regions forming at or near the center of the thin-film structure and improves power handling capability for a given resistor width. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of fabrication. | 07-05-2012 |
| 20120170624 | SYSTEMS AND METHODS FOR POWER CONTROL IN A MULTIPLE STANDARD MOBILE TRANSMITTER - A transmitter adjusts a transmitted power level by modifying a control input of a variable gain amplifier. A power amplifier control system includes an envelope extractor, an error extractor, and a feed-forward multiplier. The envelope extractor receives data signal inputs and computes the envelope of the combined signal. The error extractor generates an error signal as a function of the combined signal and the output power generated by the power amplifier. The feed-forward multiplier generates a modified error signal that is responsive to a function of the gain in a feedback path. A corresponding method for controlling a power level is also disclosed. In some embodiments, a transmit chain with a power control loop is used to adjust the transmit signal power applied at an input of a variable gain amplifier. A corresponding method for adjusting the transmit signal power level is also included. | 07-05-2012 |
| 20120166677 | DYNAMICALLY CONFIGURABLE SERIAL DATA COMMUNICATION INTERFACE - A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols. | 06-28-2012 |
| 20120161878 | POWER AMPLIFIER CONTROL CIRCUIT - This disclosure provides systems, apparatus, and methods for switching a portion of a power amplifier on and off during different modes of operation. In one aspect, a control circuit can include separate switches to provide bias currents to different portions of a power amplifier. The control circuit can include another switch to electrically connect outputs of the separate switches in a first mode of operation (for example, a high power mode) and electrically isolate the outputs of the separate switches in a second mode of operation (for example, a low power mode). In some implementations, a circuit element, such as a field effect transistor or a diode, can turn off one of the separate switches in the second mode. Alternatively or additionally, another circuit element, such as a field effect transistor or a diode, can prevent a power amplifier portion from turning on in the second mode. | 06-28-2012 |
| 20120161845 | SWITCHING SYSTEM WITH LINEARIZING CIRCUIT - A transistor-based switch is coupled to a replica circuit that includes transistor circuitry similar to that of the switch. The replica circuit biases a switched transistor to promote linear operation of the switch. | 06-28-2012 |
| 20120154054 | APPARATUS AND METHODS FOR OSCILLATION SUPPRESSION - Apparatus and methods for oscillation suppression are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers for amplifying an input radio frequency (RF) signal to generate an output RF signal. The plurality of power amplifiers include a first power amplifier, a second power amplifier, and a third power amplifier, each of which are configured to be individually switchable between an enabled state and a disabled state so as to control a power amplification of the power amplifier system. A first capacitor is electrically connected between the outputs of the first and second power amplifiers, and a second capacitor is electrically connected between the outputs of the second and third power amplifiers. The first and second capacitors are configured to allow signals generated using the first, second, and third power amplifiers to combine constructively to generate the output RF signal. | 06-21-2012 |
| 20120153477 | METHODS FOR METAL PLATING AND RELATED DEVICES - Methods for plating metal over features of a semiconductor wafer and devices that can be formed by these methods are disclosed. One such method includes forming a barrier layer over the substrate using electroless plating and forming a copper layer over the barrier layer. In some implementations, the semiconductor wafer is a GaAs wafer. Alternatively or additionally, the feature over which metal is plated can be a through-wafer via. In some implementations, a seed layer over the barrier layer can be formed using electroless plating. | 06-21-2012 |
| 20120153476 | ETCHED WAFERS AND METHODS OF FORMING THE SAME - Etched wafers and methods of forming the same are disclosed. In one embodiment, a method of etching a wafer is provided. The method includes forming a metal hard mask on the wafer using electroless plating, patterning the metal hard mask, and etching a plurality of features on the wafer using an etcher. The plurality of featured are defined by the metal hard mask. | 06-21-2012 |
| 20120149316 | RADIO FREQUENCY POWER AMPLIFIER WITH LINEARIZING PREDISTORTER - A power amplifier circuit includes an amplifier MOSFET and a predistorter MOSFET. The predistorter MOSFET source and drain are connected together, and the predistorter MOSFET is connected between the gate of the amplifier MOSFET and a second bias voltage signal. This biasing of the predistorter MOSFET causes it to provide a nonlinear capacitance at the gate of the amplifier MOSFET. The combined non-linear capacitances of the amplifier MOSFET and predistorter MOSFET provide predistortion that promotes cancellation of the distortion or nonlinearity contributed by the amplifier MOSFET alone. | 06-14-2012 |
| 20120146734 | APPARATUS AND METHODS FOR BIASING A POWER AMPLIFIER - Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a power amplifier system includes a power amplifier configured to amplify a radio frequency (RF) signal and a bias control circuit for generating a bias current for the power amplifier. The bias control circuit is configured to receive an envelope of the RF signal and to change an amplitude of the bias current based at least in part on the envelope. | 06-14-2012 |
| 20120146178 | OVERMOLDED SEMICONDUCTOR PACKAGE WITH WIREBONDS FOR ELECTROMAGNETIC SHIELDING - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 06-14-2012 |
| 20120139641 | APPARATUS AND METHODS FOR CAPACITIVE LOAD REDUCTION - Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes an envelope tracker configured to provide a supply voltage to a plurality of power amplifiers. The power amplifiers include power supply inputs electrically connected in a star configuration so as to reduce a capacitive load of the envelope tracker. The distributed capacitance of the power amplifiers is used to provide RF grounding so as to reduce the size of or eliminated the use of bypass capacitors. | 06-07-2012 |
| 20120139006 | DEVICES AND METHODOLOGIES RELATED TO STRUCTURES HAVING HBT AND FET - A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device. | 06-07-2012 |
| 20120134402 | CIRCUITS, SYSTEMS, AND METHODS FOR MANAGING AUTOMATIC GAIN CONTROL IN QUADRATURE SIGNAL PATHS OF A RECEIVER - A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine. | 05-31-2012 |
| 20120133452 | EFFECTIVE SUBSTITUTIONS FOR RARE EARTH METALS IN COMPOSITIONS AND MATERIALS FOR ELECTRONIC APPLICATIONS - Embodiments disclosed herein include methods of modifying synthetic garnets used in RF applications to reduce or eliminate Yttrium or other rare earth metals in the garnets without adversely affecting the magnetic properties of the material. Some embodiments include substituting Bismuth for some of the Yttrium on the dodecahedral sites and introducing one or more high valency ions to the octahedral and tetrahedral sites. Calcium may also be added to the dodecahedral sites for valency compensation induced by the high valency ions, which could effectively displace all or most of the Yttrium (Y) in microwave device garnets. The modified synthetic garnets with substituted Yttrium (Y) can be used in various microwave magnetic devices such as circulators, isolators and resonators. | 05-31-2012 |
| 20120133426 | PHASE-LOCKED LOOP BASED CONTROLLER FOR ADJUSTING AN ADAPTIVE CONTINUOUS-TIME FILTER - A direct conversion radio-frequency (RF) receiver includes a controller and an adaptive continuous-time filter. The adaptive continuous-time filter receives a multiple-bit control signal generated by the controller to adjust a characteristic of the continuous-time filter. The controller generates the multiple-bit control signal in response to process variation in the semi-conductor material used to implement the controller and the adaptive continuous-time filter. A method for tuning an adaptive continuous-time filter comprises determining a RC time constant, converting the RC time constant to a digital word, comparing a select bit of the digital word to a respective bit of a predetermined reference word to generate a control bit, applying the control bit to an adjustable element to modify the RC time constant, repeating the determining, converting, comparing and applying steps until the control bits generate an output word and providing the output word to the adaptive continuous-time filter. | 05-31-2012 |
| 20120115426 | POWER AMPLIFIER SATURATION DETECTION - In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation. | 05-10-2012 |
| 20120092075 | POWER AMPLIFICATION SYSTEMS AND METHODS - A power amplifier system includes a power amplifier element that provides a power output signal in response to a bias signal, and a voltage converter. The voltage converter provides at least one discrete voltage output level to the power amplifier element, where the discrete voltage output level is used to develop the bias signal. | 04-19-2012 |
| 20120083130 | APPARATUS AND METHODS FOR SHIELDING A PLASMA ETCHER ELECTRODE - Apparatus and methods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature plate within a chamber of a plasma etcher, providing a plasma source gas within the chamber, providing an anode above the feature plate and a cathode below the feature plate, connecting a portion of the cathode to the feature plate, generating plasma ions using a radio frequency power source and the plasma source gas, directing the plasma ions toward the wafer using an electric field, and providing an electrode shield around the cathode. The electrode shield is configured to protect the cathode from ions directed toward the cathode including the portion of the cathode connected to the feature plate. | 04-05-2012 |
| 20120083129 | APPARATUS AND METHODS FOR FOCUSING PLASMA - Apparatus and methods for plasma etching are disclosed. In one embodiment, a method for etching a plurality of features on a wafer includes positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, and focusing the plasma ions using a plasma focusing ring. The plasma focusing ring is configured to increase a flux of plasma ions arriving at a surface of the wafer to control the formation of the plurality of features and structures associated therewith. | 04-05-2012 |
| 20120083118 | METHODS OF EVAPORATING METAL ONTO A SEMICONDUCTOR WAFER IN A TEST WAFER HOLDER - Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers. | 04-05-2012 |
| 20120083051 | APPARATUS AND METHODS FOR ELECTRICAL MEASUREMENTS IN A PLASMA ETCHER - Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate. | 04-05-2012 |
| 20120083050 | DETECTING A DEPOSITION CONDITION - Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam. | 04-05-2012 |
| 20120080832 | DEVICES FOR METHODOLOGIES RELATED TO WAFER CARRIERS - Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed. | 04-05-2012 |
| 20120080790 | APPARATUS AND METHOD FOR UNIFORM METAL PLATING - Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate. | 04-05-2012 |
| 20120080150 | FIXTURES AND METHODS FOR UNBONDING WAFERS BY SHEAR FORCE - Disclosed are systems, devices and methodologies for separating wafers from carrier plates. In certain wafer processing operations, it is desirable to temporarily mount a wafer on a carrier plate for support and ease of handling. Such a mounting can be achieved by bonding the wafer and the carrier plate with an adhesive. Once such operations are completed, the wafer needs to be separated or unbonded from the carrier plate. Such a separation process can be achieved by applying a mechanical shear force to the wafer-carrier plate assembly. Various devices and methodologies, and related features, are disclosed. | 04-05-2012 |
| 20120080132 | SECURING MECHANISM AND METHOD FOR WAFER BONDER - Disclosed are various features associated with a securing mechanism for a wafer bonder. In certain situations, operation of securing mechanisms can generate undesirable particles and debris, and some them can be introduced to a wafer being bonded. In certain implementations, a securing mechanism can be configured to reduce the likelihood of such particles and debris being introduced to the wafer. | 04-05-2012 |
| 20120080052 | DEVICES FOR METHODOLOGIES FOR HANDLING WAFERS - Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations such as solvent and plasma cleaning. In an example situation, a wafer that has been separated from a support plate can be cleaned. The wafer still needs to be handled carefully during such a cleaning operation. Various devices and methodologies that facilitate efficient handling of wafers and wafer-cleaning operations are disclosed. | 04-05-2012 |
| 20120079138 | DYNAMICALLY CONFIGURABLE SERIAL DATA COMMUNICATION INTERFACE - A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols. | 03-29-2012 |
| 20120077551 | HIGH-VOLTAGE TOLERANT VOLTAGE REGULATOR - Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication. | 03-29-2012 |
| 20120071118 | DATA CONVERSION USING A SERIAL INTERFACE CLOCK IN A POWER AMPLIFIER MODULE - In a mobile wireless telecommunication device, a bidirectional serial interface is used to transfer a digital representation of an analog value from a first chip associated with a power amplifier module to a second chip. In an exemplary embodiment, circuitry on the first chip receives this clock signal from the second chip during the address portion of a read operation and uses this clock signal to generate a conversion clock signal. An analog-to-digital converter (ADC) on the first chip operates in response to the conversion clock signal to convert an analog value to a digital output. Circuitry on the first chip then transfers the digital output of the ADC from the first chip to the second chip via the serial interface. | 03-22-2012 |
| 20120068103 | COMPOSITIONS AND MATERIALS FOR ELECTRONIC APPLICATIONS - Embodiments disclosed herein relate to using cobalt (Co) to fine tune the magnetic properties, such as permeability and magnetic loss, of nickel-zinc ferrites to improve the material performance in electronic applications. The method comprises replacing nickel (Ni) with sufficient Co | 03-22-2012 |
| 20120064953 | CONTROLLER AND METHOD FOR USING A DC-DC CONVERTER IN A MOBILE HANDSET - A controller enables the integration of a DC-DC converter in an amplitude modulation power control loop in a mobile handset. The controller includes an input conditioner and an event sensor. The input conditioner uses a peak detector to track the output of a regulator and responds to available baseband input signals. The event sensor controls a switch that connects the DC-DC converter to a battery in response to a bypass event. The controller bypasses the DC-DC-converter when a transmitter is not enabled. The DC-DC converter is enabled prior to a transmission burst. A target voltage is determined from a series of detected peak voltages from the output of the regulator. The controller commands the DC-DC converter to transition to the target voltage until the end of a transmission burst. | 03-15-2012 |
| 20120063555 | SAW-LESS, LNA-LESS LOW NOISE RECEIVER - A low noise receiver includes a downconverter configured to receive a radio frequency (RF) signal, the downconverter comprising a switching architecture configured to generate a plurality of output phases based on a respective plurality of local oscillator (LO) signals, a differencing circuit configured to combine the plurality of output phases such that an nth output phase is differenced with an (n+K)th output phase, resulting in gain-added output phases, and a summation filter configured to receive the gain-added output phases and configured to combine the gain-added output phases such that a response of the receiver effectively reduces odd harmonics of the RF signal. | 03-15-2012 |
| 20120044980 | MULTI-MODE HIGH EFFICIENCY LINEAR POWER AMPLIFIER - A power amplifier includes a plurality of amplification paths in which at least one amplification path is selectively enabled and disabled, wherein each amplification path includes an output impedance modification element and an output phase shift element that is operable independently from the output impedance modification element, and wherein the output impedance modification element in each amplification path provides selective impedance for each amplification path. | 02-23-2012 |
| 20120039401 | PROGRAMMABLE TRANSMIT CONTINUOUS-TIME FILTER - A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provided to an upconversion mixer for conversion to RF for transmission. The TX-CTF includes amplifier circuitry and passive circuitry that together define the filter parameters. The TX-CTF further includes programmable current circuitry that provides a programmable bias current to the amplifier circuitry. The TX-CTF system also includes control logic that receives one or more transmitter control signals and, in response, generates signals that control the bias current provided to the TX-CTF. | 02-16-2012 |
| 20120038436 | REDUCING COUPLING COEFFICIENT VARIATION USING INTENDED WIDTH MISMATCH - A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace with a first edge substantially parallel to a second edge and substantially equal in length to the second edge. The first trace includes a third edge substantially parallel to a fourth edge. The fourth edge is divided into three segments. The outer segments are a first distance from the third edge. The middle segment is a second distance from the third edge. Further, the coupler includes a second trace, which includes a first edge substantially parallel to a second edge and substantially equal in length to the second edge. The second trace includes a third edge substantially parallel to a fourth edge. The fourth edge is divided into three segments. The outer segments are a first distance from the third edge. The middle segment is a second distance from the third edge. | 02-16-2012 |
| 20120038433 | REDUCING COUPLING COEFFICIENT VARIATION BY USING ANGLED CONNECTING TRACES - A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace associated with a first port and a second port. The first trace includes a first main arm, a first connecting trace connecting the first main arm to the second port, and a non-zero angle between the first main arm and the first connecting trace. Further, the coupler includes a second trace associated with a third port and a fourth port. The second trace includes a second main arm. | 02-16-2012 |
| 20120038418 | dB-LINEAR VOLTAGE-TO-CURRENT CONVERTER - A dB-linear voltage-to-current (V/I) converter that is amenable to implementation in CMOS technology. In a representative embodiment, the dB-linear V/I converter has a voltage scaler, a current multiplier, and an exponential current converter serially connected to one another. The voltage scaler supplies an input current to the current multiplier based on an input voltage. The current multiplier multiplies the input current and a current proportional to absolute temperature and supplies the resulting current to the exponential current converter. The exponential current converter has a differential MOSFET pair operating in a sub-threshold mode and generating an output current that is proportional to a temperature-independent, exponential function of the input voltage. | 02-16-2012 |
| 20120036710 | OVERMOLDED ELECTRONIC MODULE WITH AN INTEGRATED ELECTROMAGNETIC SHIELD USING SMT SHIELD WALL COMPONENTS - An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure. | 02-16-2012 |
| 20120034956 | SYSTEM AND METHOD FOR BIASING A POWER AMPLIFIER - A system and method for biasing a power amplifier includes a power amplifier having a driver stage and an output stage, the driver stage having a plurality of driver devices, a bias current source configured to deliver a bias current to each of the plurality of driver devices, and a current directing element configured to receive the bias current and selectively bias each of the plurality of driver devices based on a reference voltage and a system voltage. | 02-09-2012 |
| 20120034713 | PROCESS, VOLTAGE, TEMPERATURE SENSOR - An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level. | 02-09-2012 |
| 20120033758 | SYSTEMS AND METHODS FOR CONTROLLING LOCAL OSCILLATOR FEED-THROUGH - A method for controlling local oscillator (LO) feed-through in a direct transmitter includes detecting a signal level corresponding to LO feed-through in a radio frequency (RF) signal that is output by a direct transmitter. Responsive to detecting the signal level corresponding to LO feed-through, DC offset levels are modified for an in-phase (I) signal and/or a quadrature-phase (Q) signal in the direct transmitter. | 02-09-2012 |
| 20120032735 | REDUCING COUPLING COEFFICIENT VARIATION BY USING CAPACITORS - A coupler is presented that has high-directivity and low coupling coefficient variation. The coupler includes a first trace associated with a first port and a second port. The first port is configured substantially as an input port and the second port is configured substantially as an output port. The coupler further includes a second trace associated with a third port and a fourth port. The third port is configured substantially as a coupled port and the fourth port is configured substantially as an isolated port. In addition, the coupler includes a first capacitor configured to introduce a discontinuity to induce a mismatch in the coupler. | 02-09-2012 |
| 20120032711 | SYSTEM AND METHOD FOR PRE-CHARGING A CURRENT MIRROR - A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter. | 02-09-2012 |
| 20120020294 | SYSTEM AND METHOD FOR DYNAMICALLY IMPROVING CALL CONNECTION - A method for controlling an output of a power amplifier of a portable communication device includes determining a power level of a signal received at the portable communication device, generating a receive reference signal (RXLEV) that is indicative of the power level of the signal received at the portable communication device, and determining whether the receive reference signal is within a threshold value window. When the receive reference signal is within the threshold value window a nominal power output of a power amplifier in the portable communication device is transmitted during a random access channel signal transmission. When the receive reference signal is below the threshold value, a power output of the power amplifier in the portable communication device is increased during the random access channel signal transmission. When the receive reference signal is above the threshold value, a power output of the power amplifier in the portable communication device is decreased during the random access channel signal transmission. | 01-26-2012 |
| 20120019288 | FREQUENCY DIVIDER CIRCUIT - Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle. | 01-26-2012 |
| 20110309883 | Integrated Linear Power Detection In An RF Power Amplifier - A radio frequency (RF) power amplifier system having a power detection feature includes a balanced power amplifier, an in-phase branch current detector, an out-of-phase branch current detector, and detection circuitry. The balanced power amplifier includes a phase splitter, an in-phase power amplifier branch, an out-of-phase power amplifier branch, and a phase combiner. The in-phase branch current detector provides an indication of current in the in-phase power amplifier branch. The out-of-phase branch current detector provides an indication of current in the out-of-phase power amplifier branch. The detection circuitry combines the indications of current in the in-phase and out-of-phase power amplifier branches to produce an indication of current in the balanced power amplifier. | 12-22-2011 |
| 20110303987 | BIPOLAR FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS OF FORMING THE SAME - Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET. | 12-15-2011 |
| 20110300899 | CMOS RF SWITCH DEVICE AND METHOD FOR BIASING THE SAME - Disclosed are CMOS-based devices for switching radio frequency (RF) signals and methods for biasing such devices. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, an isolated well of such a triple-well structure can be provided with different bias voltages for on and off states of the switch to yield desired performance features during switching of amplification modes. | 12-08-2011 |
| 20110300898 | HIGH LINEARITY CMOS RF SWITCH PASSING LARGE SIGNAL AND QUIESCENT POWER AMPLIFIER CURRENT - Disclosed are high linearity CMOS-based devices capable of passing large signal and quiescent power amplifier current for switching radio frequency (RF) signals, and methods for biasing such devices. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, a bias voltage applied to an isolated well of such a triple-well structure can be substantially tied to a source voltage coupled to source and drain, so as to yield desired performance features such as high amplification linearity even when the source voltage changes. | 12-08-2011 |
| 20110298559 | APPARATUS AND METHOD FOR DIRECTIONAL COUPLING - Apparatuses and methods for directional coupling are disclosed. In one embodiment, an apparatus includes a directional coupler, a termination impedance, a switch, and a control block. The directional coupler includes a power input terminal, a power output terminal, a couple terminal and a terminate terminal. The power input terminal can receive a radio frequency signal from a power amplifier, and the power output terminal can be electrically connected to a load. The switch has an ON state and an OFF state, and includes an input electrically connected to the terminate terminal and an output electrically connected to the termination impedance. The switch is configured to provide a relatively low impedance path between the input and the output when in the ON state and to provide a relatively high impedance path between the input and the output when in the OFF state. The control block can set the state of the switch. | 12-08-2011 |
| 20110298546 | SATURATION PROTECTION OF A REGULATED VOLTAGE - A system for preventing power amplifier supply voltage saturation includes a multiple stage voltage regulator configured to provide a regulated voltage, a power amplifier configured to receive the regulated voltage, and a saturation protection circuit configured to apply a current into a first stage of the multiple stage voltage regulator when the regulated voltage reaches a reference voltage, the applied current causing a subsequent stage of the multiple stage voltage regulator to prevent the regulated voltage from exceeding the reference voltage. | 12-08-2011 |
| 20110298538 | APPARATUS AND METHOD FOR CURRENT SENSING USING A WIRE BOND - An apparatus for sensing power amplifier current includes a system voltage source that is used to develop a reference voltage, a wire bond structure connected between the system voltage source and a power amplifier, where a sense voltage developed across the wire bond structure is indicative of a current flowing through the power amplifier, and a current source configured to compensate the reference voltage for changes in resistance of the wire bond structure due to a temperature coefficient of the wire bond structure. | 12-08-2011 |
| 20110298537 | VOLTAGE DISTRIBUTION FOR CONTROLLING CMOS RF SWITCH - Disclosed are voltage distribution device and method for controlling CMOS-based devices for switching radio frequency (RF) signals. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, various bias voltages applied to such a CMOS RF switch can be facilitated by a voltage distribution component. | 12-08-2011 |
| 20110298526 | APPARATUS AND METHOD FOR DISABLING WELL BIAS - Apparatuses and methods for disabling well bias are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well. The gate is formed adjacent the well between the source and drain, and the source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a well bias control block for biasing the well voltage of the first switch and a disable circuit for disabling the well bias control block so as to prevent the well bias control block from biasing the well. The well bias control block can bias the well voltage of the first switch to at least two voltage levels. | 12-08-2011 |
| 20110298523 | APPARATUS AND METHOD FOR WELL BUFFERING - Apparatuses and methods for well buffering are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well, and the gate is formed adjacent the well between the source and drain. The source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a gate bias control block for biasing the gate voltage of the switch, a well bias control block for biasing the well voltage of the switch, and a buffer circuit for increasing the impedance between the well bias control block and the well of the switch. | 12-08-2011 |
| 20110298444 | APPARATUS AND METHOD FOR DIFFUSION SENSING - Apparatuses and methods for diffusion sensing are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch and a switch sense block. The switch includes a gate, a drain, a source, and a well. The source and drain are formed in the well. The gate is formed adjacent the well between the source and drain, and the source is configured to receive a bias voltage from a power amplifier. The switch sense block is configured to measure a signal indicative of the voltage of at least one of the source or drain voltage of the switch and to generate an output signal based on the measurement. | 12-08-2011 |
| 20110298435 | APPARATUS AND METHOD FOR VOLTAGE DISTRIBUTION - Apparatus and methods for providing regulated voltages are disclosed. Using a single voltage regulator, a plurality of regulated voltages can be generated with a voltage distribution function. These regulated voltages can be used in a variety of applications, for example, as a bias voltage for a power amplifier. In addition, the distributed regulated voltages can implement a variety of functions, such as selectively enabling or disabling power amplifiers. | 12-08-2011 |
| 20110298432 | APPARATUS AND METHOD FOR VARIABLE VOLTAGE FUNCTION - Apparatus and methods for providing variable regulated voltages are disclosed. Variable voltage control elements can adjust a regulated voltage provided by a single voltage regulator, thereby providing a variable regulated voltage. The regulated voltage can be used in a variety of applications, for example, as a bias voltage for a power amplifier. | 12-08-2011 |
| 20110298280 | APPARATUS AND METHOD FOR VARIABLE VOLTAGE DISTRIBUTION - Apparatus and methods for providing regulated voltages are disclosed. Using a single voltage regulator, a plurality of regulated voltages can be generated with a voltage distribution function. In addition, variable voltage control elements can be used to adjust a regulated voltage, thereby providing a variable regulated voltage. Together, voltage distribution and variable voltage control can create variable voltage distribution of regulated voltages. These regulated voltages can be used in a variety of applications, for example, as a bias voltage for a power amplifier. | 12-08-2011 |
| 20110297329 | DEBONDERS AND RELATED DEVICES AND METHODS FOR SEMICONDUCTOR FABRICATION - Disclosed are systems, devices and methodologies for debonding wafers from carrier plates. In certain wafer processing operations, it is desirable to temporarily mount a wafer on a carrier plate for support and ease of handling. Such a mounting can be achieved by bonding the wafer and the carrier plate with an adhesive. Once such operations are completed, the wafer needs to be debonded from the carrier plate. Such a debonding process can be achieved by applying a suction force to the wafer-carrier plate assembly. Various debonding systems, devices and methodologies, and related features, are disclosed. | 12-08-2011 |
| 20110281400 | NEAR CHIP SCALE SEMICONDUCTOR PACKAGES - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die. | 11-17-2011 |
| 20110275330 | SYSTEM AND METHOD FOR POWER AMPLIFIER OVER-VOLTAGE PROTECTION - A system for power amplifier over-voltage protection includes a power amplifier configured to receive a system voltage, a bias circuit configured to provide a bias signal to the power amplifier, and a power amplifier over-voltage circuit configured to interrupt the bias signal when the system voltage exceeds a predetermined value, while the system voltage remains coupled to the power amplifier. | 11-10-2011 |
| 20110263411 | DIELECTRIC CERAMIC MATERIALS AND ASSOCIATED METHODS - Ceramic dielectric materials that can be utilized as electronic components, such as dielectric resonators are disclosed. The material can have a formula Ba | 10-27-2011 |
| 20110235772 | SYSTEMS AND METHODS FOR PROVIDING A CLOCK SIGNAL - Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled. | 09-29-2011 |
| 20110227678 | MAGNETIC-DIELECTRIC ASSEMBLIES AND METHODS OF FABRICATION - A method for making a composite magnetic-dielectric disc assembly includes forming a dielectric ceramic annular cylinder, forming a magnetic ceramic rod, assembling the magnetic ceramic rod coaxially inside the dielectric ceramic cylinder, joining the magnetic ceramic rod to the dielectric ceramic cylinder using an adhesive comprising a ceramic material to form a rod-and-cylinder assembly, and slicing the rod-and-cylinder assembly to form a plurality of composite magnetic-dielectric disc-shaped assemblies. The magnetic-dielectric disc assemblies can be used as components of, for example, circulators, isolators, or similar electrical assemblies. | 09-22-2011 |
| 20110220723 | RFID DEVICE HAVING LOW-LOSS BARIUM-BASED CERAMIC OXIDE - An RFID chip is embedded in a device having a body that includes a low-dielectric loss material including at least one of barium stannate, barium cerate, barium tungstate and barium molybdate. | 09-15-2011 |
| 20110218020 | SYSTEM AND METHOD FOR POWER AMPLIFIER CONTROL SATURATION DETECTION AND CORRECTION - A system for power amplifier control saturation detection and correction includes a comparator configured to receive a power control signal and a detected power signal and generate a regulated voltage, a power amplifier configured to receive the regulated voltage and develop an output power, a power detector configured to sense the output power and develop the detected power signal, a saturation detector configured to receive the regulated voltage and a system voltage and determine whether the power amplifier is operating in a saturation mode during a transmit burst, and a current generator configured to reduce the power control signal when the power control signal exceeds a predetermined value and after expiration of a predetermined period of time, preventing the power control signal from exceeding the detected power signal. | 09-08-2011 |
| 20110186966 | GAAS INTEGRATED CIRCUIT DEVICE AND METHOD OF ATTACHING SAME - A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAs devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer. | 08-04-2011 |
| 20110176591 | LOAD INSENSITIVE QUADRATURE POWER AMPLIFIER POWER DETECTOR - A power detector includes a first phase shift element implemented to shift a phase of a first input signal to generate a first phase-shifted signal, a second phase shift element implemented to alter a phase of a second input signal to generate a second phase-shifted signal, a combiner for combining the first phase-shifted signal and the second phase-shifted signal to generate a combined single-phase signal, and a single element power detector for determining a power of the combined single-phase signal. | 07-21-2011 |
| 20110151776 | COMPACT LOW LOSS HIGH FREQUENCY SWITCH WITH IMPROVED LINEARITY PEROFRMANCE - A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates. | 06-23-2011 |
| 20110149452 | SURFACE MOUNT SPARK GAP - A spark gap device includes an optional insulating layer formed on a substrate, a metal layer formed on a surface of the insulating layer, a solder resist layer formed on a surface of the metal layer, and first and second contacts. The metal layer includes a central portion and a peripheral portion separated by an air gap that surrounds the central portion of the metal layer and exposes the insulating layer. The solder resist layer includes a central portion disposed on the central portion of the metal layer having a first opening exposing a central region of the central portion of the metal layer, and a peripheral portion disposed on the peripheral portion of the metal layer having a second opening exposing a peripheral region of the peripheral portion of the metal layer. The first contact is formed in the first opening and the second contact is formed in the second opening. | 06-23-2011 |
| 20110128762 | VOLTAGE CONVERSION METHOD IN A CONTINUOUSLY VARIABLE SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER - In a voltage converter, a mode configuration is selected in response to a mode control signal using a switch matrix having two or more mode configurations. Each mode configuration corresponds to one of two or more output signal voltages. The output signal is compared with a reference signal to produce a direction comparison signal. The direction comparison signal is used to produce the mode control signal. | 06-02-2011 |
| 20110128761 | CONTINUOUSLY VARIABLE SWITCHED CAPACITOR DC-DC VOLTAGE CONVERTER - A voltage converter is switched among two or more modes to produce an output voltage matching a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. The output voltage is compared with the reference voltage to determine whether to adjust the mode. | 06-02-2011 |
| 20110116403 | LMS Adaptive Filter for Digital Cancellation of Second Order Inter-Modulation Due to Transmitter Leakage - A transmit signal second-order inter-modulation (IM2) canceller for a portable handset using a full duplex mode of operation (e.g., WCDMA) is used to controllably reduce IM2 introduced by a transmit signal that appears in a received signal in a receive channel of the portable handset. The transmit signal IM2 canceller includes a delay estimator and a digital signal adjuster. The delay estimator receives a first input from a receive channel and a second input from a transmit channel. The delay estimator generates an estimate of the IM2 that the transmit channel introduces in the receive channel. The digital signal adjuster removes the estimate of the IM2 before forwarding a modified receive channel signal to a baseband subsystem of the portable handset. | 05-19-2011 |
| 20110084378 | SEMICONDUCTOR PACKAGE WITH INTEGRATED INTERFERENCE SHIELDING AND METHOD OF MANUFACTURE THEREOF - An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices. | 04-14-2011 |
| 20110084368 | OVERMOLDED SEMICONDUCTOR PACKAGE WITH A WIREBOND CAGE FOR EMI SHIELDING - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 04-14-2011 |
| 20110075777 | Phase-Locked Loop Based Controller for Adjusting an Adaptive Continuous-Time Filter - A direct conversion radio-frequency (RF) receiver includes a controller and an adaptive continuous-time filter. The adaptive continuous-time filter receives a multiple-bit control signal generated by the controller to adjust a characteristic of the continuous-time filter. The controller generates the multiple-bit control signal in response to process variation in the semiconductor material used to implement the controller and the adaptive continuous-time filter. A method for tuning an adaptive continuous-time filter comprises determining a RC time constant, converting the RC time constant to a digital word, comparing a select bit of the digital word to a respective bit of a predetermined reference word to generate a control bit, applying the control bit to an adjustable element to modify the RC time constant, repeating the determining, converting, comparing and applying steps until the control bits generate an output word and providing the output word to the adaptive continuous-time filter. | 03-31-2011 |
| 20110074512 | CIRCUIT AND METHOD FOR BIASING A GALLIUM ARSENIDE (GaAs) POWER AMPLIFIER - A circuit for biasing a gallium arsenide (GaAs) power amplifier includes a reference voltage generator circuit implemented in a gallium arsenide (GaAs) material system, a field effect transistor (FET) bias circuit implemented in the gallium arsenide material system and adapted to receive an output of the reference voltage generator circuit and adapted to provide an output to a radio frequency (RF) amplifier stage. | 03-31-2011 |
| 20110057736 | Linear, Voltage-Controlled Ring Oscillator With Current-Mode, Digital Frequency And Gain Control - In a voltage-controlled ring oscillator, one or more controllable current sources generate a bias current in response to a tuning voltage. Any of several features can be included to promote frequency tuning linearity. In accordance with one feature, the ring oscillator circuit transistors can be sized relative to one another to skew the rise and fall times of the ring oscillator output signal with respect to one another. In accordance with another feature, a peak limiter can limit the oscillation amplitude in response to the bias current. In accordance with still another feature, a controllable bias current source can include a voltage-to-current converter and one or more groups of digitally controlled current source transistors. | 03-10-2011 |
| 20110032037 | POWER AMPLIFIER BIAS CIRCUIT HAVING CONTROLLABLE CURRENT PROFILE - A power amplifier bias circuit having a controllable current profile includes a first transistor device configured as a switch, and configured to receive a non-regulated system voltage, and a plurality of resistors configured to provide a current and configured to determine an amount of a bias current that flows through a second transistor device, where the second transistor device is part of a current mirror comprising a third transistor device and the amount of bias current flowing through the second transistor device determines a power output of the third transistor device. | 02-10-2011 |
| 20110032030 | SYSTEMS AND METHODS FOR SATURATION DETECTION AND CORECTION IN A POWER CONTROL LOOP - Systems and methods are described for detecting and correcting saturation in a power amplification circuit. An exemplary circuit comprises a power amplifier that provides an amplified output signal based upon an input signal and a gain control signal; a power detector that provides a detector signal indicative of the amplified signal magnitude; an error amplifier that generates the gain control signal based upon a setpoint signal and the detector signal; and a saturation detector that provides a saturation detection signal indicating whether gain control signal exceeds a reference signal. In another embodiment the circuit comprises an offset generator that provides a correction to the setpoint signal in response to the saturation detection signal indicating that the gain control signal exceeds the reference signal. In still another embodiment the circuit includes an offset cutoff circuit that freezes the correction to the setpoint signal in response to the correction exceeding a threshold. | 02-10-2011 |
| 20110029266 | PROCESS, VOLTAGE, AND TEMPERATURE SENSOR - An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level. | 02-03-2011 |
| 20110021237 | Closed-Loop Adaptive Power Control For Adjusting Bandwidth In A Mobile Handset Transmitter - A mobile handset is arranged with an adaptive power controller to controllably adjust transmit power. The adaptive power controller is coupled to a power amplifier module to form a closed feedback loop. The adaptive power control module includes a first shifter, a first sealer, an accumulator and a hold element. The first shifter and first sealer receive respective bandwidth control signals and an error signal. The first shifter and first sealer generate a modified error signal that is forwarded to and filtered by the accumulator and the hold element to generate a power control signal. The power control signal, which is generated the radio frequency subsystem of the handset can quickly and accurately track rapid changes in transmit power. | 01-27-2011 |
| 20110008934 | NEAR CHIP SCALE PACKAGE INTEGRATION PROCESS - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die. | 01-13-2011 |
| 20110006841 | SWITCHABLE BALANCED AMPLIFIER - A switchable balanced amplifier having multiple, configurable independent input/output paths. Switching networks coupled to the input and/or output quadrature couplers of the balanced amplifier are used to configurably direct any of one or more input signals to any of one or more output ports. In one example, each output port is coupled to circuitry tailored to a specific type of input signal, operating protocol and/or operating frequency band. | 01-13-2011 |
| 20100327438 | NEAR CHIP SCALE SEMICONDUCTOR PACKAGES - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die. | 12-30-2010 |
| 20100317299 | SYSTEM AND METHOD FOR ADJACENT CHANNEL POWER DETECTION AND DYNAMIC BANDWIDTH FILTER CONTROL - A system for detecting and minimizing interference in a radio receiver includes a plurality of bandpass filters having different response characteristics, a power detector configured to compare a power output of a first bandpass filter and a second bandpass filter, and logic to cascade a third bandpass filter when the difference in power output between the power output of the first bandpass filter and the power output of the second bandpass filter exceeds a threshold amount. | 12-16-2010 |
| 20100264991 | SWITCHED CAPACITOR VOLTAGE CONVERTER FOR A POWER AMPLIFIER - A voltage converter includes a plurality of capacitors and corresponding first switch elements, the capacitors coupled in series and arranged to each charge to a voltage level during a first clock period, the voltage level determined by a supply voltage level, the number of capacitors and a value of each capacitor; and a plurality of second switch elements configured to cause the plurality of capacitors to be connected in parallel and to discharge into an output capacitor during a second clock period, the output capacitor charged to a discrete voltage output level so that the output capacitor provides the discrete voltage output level, wherein the discrete voltage output level is less than the supply voltage level and wherein the discrete voltage output level is used to develop a bias signal that is supplied to a power amplifier element. | 10-21-2010 |
| 20100253398 | Fully Differential Single-Stage Frequency Divider Having 50% Duty Cycle - A fully differential frequency divider includes a first fully differential single-stage latch circuit configured to receive an input signal and provide a corresponding output signal upon transition of a clock signal, the output signal corresponding to an in-phase portion of a communication signal, and a second fully differential single-stage latch circuit coupled to the first fully differential single-stage latch circuit, the second fully differential single-stage latch circuit configured to provide a corresponding output signal upon transition of the clock signal. The second fully differential single-stage latch circuit is also configured to receive as an input signal the output signal of the first fully differential single-stage latch circuit, the output signal of the second fully differential single-stage latch circuit corresponding to a quadrature-phase portion of the communication signal, where the output signal of the second fully differential single-stage latch circuit is provided as the input signal to the first fully differential single-stage latch circuit. | 10-07-2010 |
| 20100253397 | FREQUENCY DIVIDER CIRCUIT - Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle. | 10-07-2010 |
| 20100244161 | WAFER LEVEL PACKAGING USING FLIP CHIP MOUNTING - A semiconductor packaged device, and method of packaging that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device. | 09-30-2010 |
| 20100237433 | Bipolar/Dual FET Structure Having FETs With Isolated Channels - According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET. | 09-23-2010 |
| 20100229143 | DETECTION AND REMOVAL OF HAZARDS DURING OPTIMIZATION OF LOGIC CIRCUITS - A method of generating a hazard-free representation of a logic circuit that can leverage the powerful and mature synchronous-circuit CAD synthesis tools. In a representative embodiment of the method, an initial representation of a specified asynchronous logic circuit is synthesized using one of such CAD tools. The initial representation is then analyzed to identify hazardous transitions and modified, e.g., by iteratively inserting additional logic aimed at preventing the identified hazardous transitions from producing glitches, until a hazard-free representation of the specified asynchronous logic circuit is produced. | 09-09-2010 |
| 20100213513 | Hyperabrupt Diode Structure And Method For Making Same - A hyperabrupt diode structure includes a substrate formed from a low-ohmic contact material, a graded semiconductor layer comprising gallium arsenide, an offset layer comprising indium gallium phosphide over the graded semiconductor layer, a contact layer comprising gallium arsenide over the offset layer, a first electrical contact on the substrate, the first electrical contact forming a cathode of the hyperabrupt diode structure, and a second electrical contact over the contact layer, the second electrical contact forming an anode of the hyperabrupt diode structure. | 08-26-2010 |
| 20100197365 | ERROR VECTOR MAGNITUDE CONTROL WITHIN A LINEAR TRANSMITTER - In a portable radio transceiver, such as a mobile wireless telephone, conditions indicative of transmitter distortion (as represented by error vector magnitude (EVM)) are sensed, and transmitted RF power is adjusted in response, so as to reduce distortion and decrease EVM. The conditions can include high VSWR or a combination of high VSWR and low battery power. | 08-05-2010 |
| 20100194493 | BALUN SIGNAL SPLITTER - A balun signal splitter for use in transceiver systems, such as wireless communications systems, including a wide-band balun with a secondary winding for signal splitting between two operating bands (e.g., high-band and low-band) or modes. An example of a balun signal splitter configured for dual-band or dual-mode operation or includes a balun having a primary winding and a secondary winding, the secondary winding having a first port and a second port, a first network coupled to the first port and configured to present a short circuit impedance at the first port at out-of-band frequencies or during out-of-mode operation, and a second network coupled to the second port and configured to present a short circuit impedance at the second port at out-of-band frequencies or during out-of-mode operation. | 08-05-2010 |
| 20100194443 | dB-LINEAR VOLTAGE-TO-CURRENT CONVERTER - A dB-linear voltage-to-current (V/I) converter that is amenable to implementation in CMOS technology. In a representative embodiment, the dB-linear V/I converter has a voltage scaler, a current multiplier, and an exponential current converter serially connected to one another. The voltage scaler supplies an input current to the current multiplier based on an input voltage. The current multiplier multiplies the input current and a current proportional to absolute temperature and supplies the resulting current to the exponential current converter. The exponential current converter has a differential MOSFET pair operating in a sub-threshold mode and generating an output current that is proportional to a temperature-independent, exponential function of the input voltage. | 08-05-2010 |
| 20100188146 | High Efficiency Power Amplifier Having Embedded Switching - A power amplifier includes at least one amplification path comprising at least a first amplification device and a second amplification device, where the first amplification device has a common control terminal to provide amplification when biased on and to prevent conduction of a signal through the amplification path when biased off. | 07-29-2010 |
| 20100178960 | DATA CONVERSION USING A SERIAL INTERFACE CLOCK IN A POWER AMPLIFIER MODULE - In a mobile wireless telecommunication device, a bidirectional serial interface is used to transfer a digital representation of an analog value from a first chip associated with a power amplifier module to a second chip. In an exemplary embodiment, circuitry on the first chip receives this clock signal from the second chip during the address portion of a read operation and uses this clock signal to generate a conversion clock signal. An analog-to-digital converter (ADC) on the first chip operates in response to the conversion clock signal to convert an analog value to a digital output. Circuitry on the first chip then transfers the digital output of the ADC from the first chip to the second chip via the serial interface. | 07-15-2010 |
| 20100172450 | Circuits, Systems, and Methods for Managing Automatic Gain Control in Quadrature Signal Paths of a Receiver - A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine. | 07-08-2010 |
| 20100171576 | TEMPERATURE-COMPENSATED PIN-DIODE ATTENUATOR - Temperature compensation is provided for a PIN-diode attenuator by temperature-sensitive resistive networks. In one embodiment, each temperature-sensitive resistive network includes a resistor connected in series to a parallel network formed from another resistor and an n-type thermistor, whose resistance decreases as temperature increases. As a result, as temperature increases, the currents applied by the resistive networks to PIN diodes in the attenuator also increases to compensate (at least partially) for the temperature dependence of the operations of the PIN-diode attenuator. Low-pass filters are provided in the resistive networks to inhibit relatively high-frequency (e.g., RF) signals in the attenuator from reaching and distorting the operations of the thermistors. | 07-08-2010 |
| 20100156476 | SYSTEMS AND METHODS FOR PROVIDING A CLOCK SIGNAL - Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate. The controller can be configured to receive the phase detection signal and to enable the output gate when the value of the phase shift corresponds to a predetermined value. The output gate can provide the output signal when enabled. | 06-24-2010 |
| 20100105448 | POWER AMPLIFIER SATURATION DETECTION - In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation. | 04-29-2010 |
| 20100073255 | Overmolded semiconductor package with an integrated antenna - According to an exemplary embodiment, an overmolded semiconductor package includes at least one semiconductor die situated over a package substrate. The overmolded semiconductor package further includes a mold compound overlying the at least one semiconductor die and the package substrate. The overmolded semiconductor package further includes a conductive layer situated on an outer surface of the mold compound and having an opening. The overmolded semiconductor package further includes an antenna feed line situated in the mold compound and having a portion exposed in the opening in the conductive layer, thereby providing an antenna input on the outer surface of the mold compound. | 03-25-2010 |
| 20100072517 | Bipolar/dual FET structure including enhacement and depletion mode fets with isolated channels - According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET. | 03-25-2010 |
| 20100068831 | Method for wafer trimming for increased device yield - According to an exemplary embodiment, a method for site-specific trimming of a wafer to provide a target parameter value for a plurality of devices on the wafer includes performing a first measurement of a parameter at a subset of the number of devices on the wafer. The method further includes forming a top layer over the wafer after performing the first measurement. The method further includes performing a second measurement of the parameter at the subset of the devices on the wafer after forming the top layer. The method further includes determining an amount of the top layer to remove across the wafer to provide the target parameter value for the devices by utilizing the first and second measurements of the parameter. The method can be utilized to, for example, achieve a more uniform characteristic frequency for bulk acoustic wave (BAW) filters. | 03-18-2010 |
| 20100067622 | Circuit, Controller and Methods for Dynamic Estimation and Cancellation of Phase and Gain Imbalances in Quadrature Signal Paths of a Receiver - A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions. | 03-18-2010 |
| 20100062813 | POWER AMPLIFIER LOAD LINE SWITCH FOR A PORTABLE TRANSCEIVER - In a portable radio transceiver, a power amplifier system includes a load line switch that operates in response to a mode control signal to promote high efficiency in both a high-power mode and a low-power mode. The switching circuit is operable to couple the inductance to the shunt capacitance in response to a control signal indicating operation in a low-power mode. The switching circuit is further operable to decouple the inductance from the shunt capacitance in response to a control signal indicating operation in a high-power mode. In the low-power mode, the inductance couples with the shunt capacitance to decrease total capacitance at the output of the power amplifier. In the high-power mode, the total capacitance at the output of the power amplifier is substantially equal to the shunt capacitance alone, and the inductance essentially has no effect on total capacitance at the power amplifier output. | 03-11-2010 |
| 20100054375 | SYSTEM AND METHOD FOR FORWARD AND BACKWARD RECURSIVE COMPUTATION - A system and method is provided for improved and efficient forward and backward recursive computations that may be used, for example, with turbo code decoding applications. The invention performs the forward computations using a full length of a sequence to be decoded and performs the reverse computations using a sliding window over the sequence. | 03-04-2010 |
| 20100002345 | RADIO FREQUENCY SWITCH ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD)-protected radio frequency (RF) transceiver switching circuit includes two or more switchable RF transmit and receive port circuits, a diode-based ESD-protection circuit, and a voltage-dividing circuit. The voltage-dividing circuit, which can be a switching circuit, minimizes the number of diode devices needed to protect against ESD by dividing the voltage at the antenna node down to a lower voltage across the diode devices. | 01-07-2010 |
| 20090267457 | Bulk acoustic wave resonator with reduced energy loss - According to an exemplary embodiment, a bulk acoustic wave (BAW) resonator includes a piezoelectric layer having a disrupted texture region, where the disrupted texture region is situated in a controlled thickness region of the BAW resonator. The BAW resonator further includes lower and upper electrodes situated on opposite surfaces of the piezoelectric layer. The controlled thickness region has controlled electromechanical coupling and includes a segment of material situated over the upper electrode. The segment of material can be a metal or a dielectric material. The disrupted texture region can be situated at an edge of the BAW resonator and can extend along a perimeter of the BAW resonator. | 10-29-2009 |
| 20090267453 | BULK ACOUSTIC WAVE RESONATOR WITH CONTROLLED THICKNESS REGION HAVING CONTROLLED ELECTROMECHANICAL COUPLING - According to an exemplary embodiment, a bulk acoustic wave (BAW) resonator includes a piezoelectric layer situated between upper and lower electrodes, where each of the upper and lower electrodes are a high density metal. The BAW resonator further includes a controlled thickness region including a low density metal segment, where the low density metal segment is situated adjacent to the piezoelectric layer, and where the controlled thickness region has controlled electromechanical coupling. The controlled thickness region can provide reduced electromechanical coupling into lateral modes. The low density metal segment can extend along the perimeter of the BAW resonator. | 10-29-2009 |
| 20090249619 | OVERMOLDED ELECTRONIC MODULE WITH AN INTEGRATED ELECTROMAGNETIC SHIELD USING SMT SHIELD WALL COMPONENTS - An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure. | 10-08-2009 |
| 20090243163 | CO-FIRING OF MAGNETIC AND DIELECTRIC MATERIALS FOR FABRICATING COMPOSITE ASSEMBLIES FOR CIRCULATORS AND ISOLATORS - A method for making a composite magnetic-dielectric disc assembly includes forming a dielectric ceramic cylinder, forming a magnetic ceramic rod, assembling the magnetic ceramic rod coaxially inside the dielectric ceramic cylinder to form a rod-and-cylinder assembly, kilning (firing) the rod-and-cylinder assembly, slicing the rod-and-cylinder assembly to form a plurality of composite magnetic-dielectric disc-shaped assemblies. The magnetic-dielectric disc assemblies can be used in manufacturing, for example, circulators, isolators or similar electronic components. Accordingly, the method for making the disc assemblies can be included as part of a method for making such electronic components. | 10-01-2009 |
| 20090239495 | DC-COMPENSATED IP2 CALIBRATION FOR WCDMA RECEIVER - Second-order intermodulation distortion can be suppressed in a direct conversion radio receiver having a downconversion mixer by calibrating resistors and a current source in the mixer. A test signal is applied to the signal inputs of the mixer transconductor. The resistances of first and second variable resistor circuits connected to the switching quad are then varied while also varying a variable current source. Each time the resistances and current are set to new values, the resulting mixer output signal is measured. When the measured output signal is determined to be at a minimum, the variable resistors and current source are left at the corresponding values to which they have been set. Adjusted in this manner, the current source counteracts the DC offset voltage at the mixer output. | 09-24-2009 |
| 20090219100 | VOLTAGE-CONTROLLED OSCILLATOR GAIN CALIBRATION FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP - A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB. | 09-03-2009 |
| 20090045704 | Method for forming a multi-layer electrode underlying a piezoelectric layer and related structure - According to an exemplary embodiment, a method of forming a multi-layer electrode for growing a piezoelectric layer thereon includes a step of forming a high conductivity metal layer over a substrate. The method further includes a step of forming a seed layer over the high conductivity metal layer. The method further includes a step of forming a high density metal layer over the seed layer. The method further includes a step of forming a piezoelectric layer over the high density metal layer. The high conductivity metal layer, the seed layer, and the high density metal layer form the multi-layer electrode on which the piezoelectric layer is grown. | 02-19-2009 |
| 20090045703 | Bulk acoustic wave structure with aluminum cooper nitride piezoelectric layer and related method - According to an exemplary embodiment, a bulk acoustic wave structure includes a lower electrode situated over a substrate. The bulk acoustic wave structure further includes a piezoelectric layer situated over the lower electrode, where the piezoelectric layer comprises aluminum copper nitride. The bulk acoustic wave structure further includes an upper electrode situated over the lower electrode. The bulk acoustic wave structure can further include a bond pad connected to the upper electrode, where the bond pad comprises aluminum copper. The lower electrode can include a high density metal situated adjacent to the piezoelectric layer and a high conductivity metal layer underlying the high density metal layer. | 02-19-2009 |
| 20090040671 | Power clamp for on-chip ESD protection - According to an exemplary embodiment, a power clamp for providing on-chip ESD and mistrigger event protection includes a clamping transistor coupled between a power bus and a ground. The power clamp further includes a number of inverter stages coupled in series, where a first inverter stage has an output coupled to the clamping transistor. The power clamp further includes a turn-off resistor coupled between the power bus and an input of the first inverter. The turn-off resistor is configured to cause the clamping transistor to automatically turn off after having been turned on. The turn-off resistor determines a period of time that the clamping transistor is turned on after an ESD or mistrigger event has occurred on the power bus. The power clamp further includes a timing circuit coupled to the inverter stages. The power clamp further includes a feedback transistor coupled between a second inverter stage and the power bus. | 02-12-2009 |
| 20090017326 | Method for forming an acoustic mirror with reduced metal layer roughness and related structure - According to an exemplary embodiment, a method of forming a metal layer having reduced roughness includes a step of forming a seed layer over a dielectric layer. The method further includes a step of forming the metal layer over the seed layer. The seed layer causes a top surface of the metal layer to have reduced roughness. The seed layer and the metal layer can be formed in a same process chamber or in different process chambers. The dielectric layer, the seed layer, and the metal layer having reduced roughness can be utilized in an acoustic mirror structure. | 01-15-2009 |
| 20090015323 | Balanced amplifier with protection circuit - According to an exemplary embodiment, a balanced amplifier includes an in-phase amplifier coupled to a first input port of an output coupler and a quadrature amplifier coupled to a second input port of the output coupler. The balanced amplifier further includes an impedance termination coupled to an isolated port of the output coupler. The balanced amplifier further includes a protection circuit coupled to the isolated port of the output coupler and configured to limit an amount of power applied across the impedance termination. The balanced amplifier further includes an input coupler having a first output port coupled to an input of the in-phase amplifier and a second output port coupled to an input of the quadrature amplifier. | 01-15-2009 |
| 20080315396 | Mold compound circuit structure for enhanced electrical and thermal performance - According to an exemplary embodiment, an overmolded semiconductor package includes at least one semiconductor die situated over a package substrate. The overmolded semiconductor package further includes a mold compound overlying the at least one semiconductor die and the package substrate and having a top surface. The overmolded semiconductor package further includes a first patterned conductive layer situated on the top surface of the mold compound. The overmolded semiconductor package can further include at least one conductive interconnect situated in the mold compound, where the at least one conductive interconnect is electrically connected to the first patterned conductive layer. The first patterned conductive layer can include at least one passive component. | 12-25-2008 |
| 20080315356 | Semiconductor die with backside passive device integration - According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the active surface. The semiconductor die further includes at least one through-wafer via, where the at least one through-wafer via electrically connects the at least one passive device to the interconnect region. The interconnect region can include a number of solder bump pads or a number of bond pads. | 12-25-2008 |
| 20080233994 | Digital Modulator and Method for Initiating Ramp Power Transitions in a Mobile Handset Transmitter - A digital modulator for a portable handset using 8PSK or EDGE modulation with a direct launch transmitter is used to controllably adjust the transmit power of the portable handset. The digital modulator includes a controller coupled between a memory and an accumulator. The controller is responsive to an indication that the transmit power should be transitioned. The controller temporarily alters the data transferred from the memory to the accumulator during transitions of the transmit power level. | 09-25-2008 |
| 20080232268 | LMS Adaptive Filter for Digital Cancellation of Second Order Inter-Modulation Due to Transmitter Leakage - A transmit signal second-order inter-modulation (IM | 09-25-2008 |
| 20080220826 | Controller and Method for Using a DC-DC Converter in a Mobile Handset - A controller enables the integration of a DC-DC converter in an amplitude modulation power control loop in a mobile handset. The controller includes an input conditioner and an event sensor. The input conditioner uses a peak detector to track the output of a regulator and responds to available baseband input signals. The event sensor controls a switch that connects the DC-DC converter to a battery in response to a bypass event. The controller bypasses the DC-DC-converter when a transmitter is not enabled. The DC-DC converter is enabled prior to a transmission burst. A target voltage is determined from a series of detected peak voltages from the output of the regulator. The controller commands the DC-DC converter to transition to the target voltage until the end of a transmission burst. | 09-11-2008 |
| 20080217727 | Radio frequency isolation for SOI transistors - According to an exemplary embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby minimizing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. | 09-11-2008 |
| 20080217708 | Integrated passive cap in a system-in-package - According to an exemplary embodiment, a system-in-package includes at least one semiconductor die situated over a package substrate. The system-in-package further includes a wall structure situated on the at least one semiconductor die. The system-in-package further includes an integrated passive cap situated over the wall structure, where the integrated passive cap includes at least one passive component. The wall structure and the integrated passive cap form an air cavity over the at least one semiconductor die. The system-in-package can further include at least one bond pad situated on a cap substrate. The at least one bond pad on the cap substrate of the integrated passive cap can be electrically connected to a substrate bond pad on the package substrate. | 09-11-2008 |
