| SKYMEDI CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120096280 | SECURED STORAGE DEVICE WITH TWO-STAGE SYMMETRIC-KEY ALGORITHM - A secured storage device uses a user key set by user to encrypt a primary key that is for encryption or decryption of user data, to produce a first encrypted data. In the secured storage device, neither the primary key nor the user key is stored, but the first encrypted data, and a secondary key and a second encrypted data produced from the secondary key encrypted with the user key for verifying the password inputted by user are stored. Therefore, even though a storage medium in the secured storage device is detached and read, the primary key and the user key cannot be obtained by a third party for reading out any encrypted user data from the secured storage device. | 04-19-2012 |
| 20120079289 | SECURE ERASE SYSTEM FOR A SOLID STATE NON-VOLATILE MEMORY DEVICE - A secure erase system for a solid state memory device is disclosed. A memory area provides a data block for storing data and a key block for storing at least one key. A translation unit maps a logical address to a physical address associated with the memory area. An encryption unit encrypts plaintext data to be written to the memory area with the associated key and decrypts the encrypted data to be read by a host with the associated key. The key associated with a logical erase group to be secure erased is deleted after receiving a command requesting to erase the data associated with the logical erase group. | 03-29-2012 |
| 20120008387 | METHOD OF TWICE PROGRAMMING A NON-VOLATILE FLASH MEMORY WITH A SEQUENCE - A method of twice programming a multi-bit per cell non-volatile memory with a sequence is disclosed. At least one page at a given word line is firstly programmed with program data by a controller of the non-volatile memory, and at least one page at a word line preceding the given word line is secondly programmed with the same program data by the controller. | 01-12-2012 |
| 20110283164 | CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS - A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter. | 11-17-2011 |
| 20110246855 | Method and Apparatus of Generating a Soft Value for a Memory Device - A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters. | 10-06-2011 |
| 20110131459 | Memory Device with Protection Capability and Method of Accessing Data Therein - The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password. | 06-02-2011 |
| 20110072191 | Uniform Coding System for a Flash Memory - A uniform coding system for a flash memory is disclosed. A statistic decision unit determines a coding word according to a plurality of inputs. An inverse unit controllably inverts input data to be encoded. The input data are then encoded into encoded data according to a statistic determined by the statistic decision unit. | 03-24-2011 |
| 20110055659 | Method and System of Dynamic Data Storage for Error Correction in a Memory Device - A method of dynamic data storage for error correction in a memory device is disclosed. Data for storage is received, and the received data is then encoded and associated error correction code (ECC) is generated. The encoded data is stored in a portion of a data partition of the memory device, wherein percentage of the stored data in the data partition is determined according to an amount of corrected errors associated with the data partition or is predetermined. | 03-03-2011 |
| 20110041040 | Error Correction Method for a Memory Device - An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding. | 02-17-2011 |
| 20110038209 | Method and System for Adaptively Finding Reference Voltages for Reading Data from a MLC Flash Memory - A method and system for adaptively finding reference voltages for reading data from a multi-level cell (MLC) flash memory is disclosed. According to one embodiment, a first total number of cells of the flash memory above a first threshold voltage in a shifted threshold voltage distribution is provided. Search to find a second threshold voltage such that a second total number of the cells above the second threshold voltage is approximate to the first total number. An initial reference voltage or voltages of the initial threshold voltage distribution are shifted with an amount approximate to a voltage difference between the second threshold voltage and the first threshold voltage, thereby resulting in a new reference voltage or voltages for reading the data from the MLC flash memory. | 02-17-2011 |
| 20110038205 | Method Of Reducing Bit Error Rate For A Flash Memory - A method of reducing coupling effect in a flash memory is disclosed. A neighboring page is read, and a flag is set active if the neighboring page is an interfering page. Data are read from the neighboring page at least two more times using at least two distinct read voltages respectively. The threshold-voltage distributions associated with an original page and the neighboring page are transferred according to the read data and the flag. | 02-17-2011 |
| 20100321997 | Method And System For Obtaining A Reference Block For A MLC Flash Memory - A method and system for obtaining a reference block on which reference voltages may be found for a MLC flash memory are disclosed. A first block and a second block are provided in the flash memory. A memory controller alternatively controls one of the first and the second blocks to act as the reference block and the other one as a cycle block in a respective period, during which the reference block stays idle and the cycle block is subjected to program/erase cycles. | 12-23-2010 |
| 20100115213 | MEMORY APPARATUS AND MEMORY MANAGEMENT METHOD OF THE SAME - A method of memory management for an apparatus having a non-volatile memory and a volatile memory includes the steps of forming a tree structure of entries in the volatile memory, in which the tree structure has a left branch and a right branch, and a difference of heights of the left branch and the right branch is equal to or less than one; and accessing an entry in the volatile memory through the tree structure. | 05-06-2010 |
| 20100088458 | OPERATION METHOD OF MEMORY - An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset. | 04-08-2010 |
| 20100030933 | NON-VOLATILE MEMORY STORAGE DEVICE AND OPERATION METHOD THEREOF - A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged. | 02-04-2010 |
| 20090287893 | METHOD FOR MANAGING MEMORY - A method is employed to manage a memory, e.g., a flash memory, including a plurality of paired pages. Each paired page includes a page and a respective risk zone. For each write command, at least one unwritten page is selected for writing new data. For each unwritten page whose risk zone includes at least one written page, each written page is copied or backed up, and the new data is written to the unwritten page. For each unwritten page whose risk zone lacks a written page, the new data is written to the unwritten page. In an embodiment, the written page is copied only if the unwritten page and the written page are operated by different write commands. | 11-19-2009 |
| 20090259819 | METHOD OF WEAR LEVELING FOR NON-VOLATILE MEMORY - A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone. | 10-15-2009 |
| 20090254729 | METHOD OF WEAR LEVELING FOR A NON-VOLATILE MEMORY - According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table is built in which the logical block addresses having frequently accessed data are allocated equally to the plurality of windows. The logical block addresses may store a File Allocation Table (FAT) or a directory table; therefore the windows they locate will be written or erased more frequently. In an embodiment, the logical block addresses having frequently accessed data are allocated on a one-to-one basis to the plurality of windows. For example, the plurality of windows may comprise Windows | 10-08-2009 |
| 20090249140 | METHOD FOR MANAGING DEFECT BLOCKS IN NON-VOLATILE MEMORY - A method for managing defect blocks in a non-volatile memory essentially comprises the steps of detecting defect blocks in the non-volatile memory, storing addresses of the defect blocks in a table block of the non-volatile memory, and setting the non-volatile memory to be read-only if the quantity of defect blocks in the non-volatile memory exceeds a threshold and no free blocks remain in the non-volatile memory. In a preferred embodiment, the free pages in the defect block continue to be programmed before setting the non-volatile memory to be read-only. | 10-01-2009 |
| 20090198944 | SEMICONDUCTOR MEMORY DEVICE - An adaptive semiconductor memory device is used for being inserted into a host for storage. The semiconductor memory device comprises a non-volatile memory and a switch. The switch can be a logical switch or a physical switch that controls the semiconductor memory device to be in compliance with either a first specification version or a second specification version of the semiconductor memory device. The second specification version in comparison with the first specification version is used for higher capacity applications. | 08-06-2009 |
| 20090198919 | A Non-Volatile Memory Device, and Method of Accessing a Non-Volatile Memory Device - A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power. | 08-06-2009 |
| 20090198882 | METHOD OF WEAR LEVELING FOR NON-VOLATILE MEMORY AND APPARATUS USING THE SAME - A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap. | 08-06-2009 |
| 20090043945 | Non-Volatile Memory System and Method for Reading Data Therefrom - A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced. | 02-12-2009 |
