| SILICON MOTION, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120105592 | 3D IMAGE CAPTURING DEVICE AND CONTROLLER CHIP THEREOF - A 3D image capturing device and a controller chip thereof. The controller chip includes a first and a second sensor interface, a pixel data synchronization module, a 3D image generator and an output interface. The first and second sensor interfaces are coupled to a first and a second 2D image capturing device, respectively, to receive a first and a second image. The pixel data synchronization module synchronizes the pixel data of the first and second images. Based on the synchronized first and second images, the 3D image generator generates a 3D-image. By the output interface, the 3D-image capturing device transmits the generated 3D image to be received by a host. | 05-03-2012 |
| 20120099786 | ELECTRONIC SYSTEMS AND METHODS FOR REPAIRING SCAR IMAGES - A method for repairing scar images is provided, in which a facial region of an image is detected, a first average skin tone value is subtracted from an original pixel value of at least one pixel to generate a first mask value, the first mask value is divided by a constant to generate a first modified mask value; and the first modified mask value is added to the first average skin tone value to generate a first pixel value to serve as a compensated scar pixel value of the pixel. | 04-26-2012 |
| 20120066437 | DATA PROGRAMMING CIRCUIT AND METHOD FOR OTP MEMORY - A data programming circuit is provided. A one-time-programmable (OTP) stores a first version of encoding data corresponding to a first version of a read-only memory (ROM) code. A control unit stores a second version of the ROM code into the OTP memory, wherein the control unit obtains a matching table according to the first version of the encoding data and the second version of the ROM code. The control unit obtains a first data segment of the first version of the encoding data and a second data segment of the second version of the ROM code that have the same content, according to the matching table. The control unit encodes the second data segment as a specific address, and the specific address points to the first data segment of the first version of the encoding data in the OTP memory. | 03-15-2012 |
| 20120033492 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method. In one embodiment, a data storage device comprises a flash memory. First, the flash memory is directed to read a plurality of programming voltage values for data programming. The programming voltage values are then adjusted to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values. The adjusted programming voltage values are then sent to the flash memory. The flash memory is then directed to perform data programming according to the adjusted programming voltage values, wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values. | 02-09-2012 |
| 20120023283 | Flash Memory Device and Method for Managing Flash memory Device - A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a first data bus and at least one single level cell flash memory. Each memory cell of the single level cell flash memory stores one bit of data. The multi level memory module includes a second data bus and at least one multi level cell flash memory. Each memory cell of the multi level cell flash memory stores more than one bit of data. The first data bus is coupled to the second data bus. During a write operation, the controller writes data to the single level memory module, and the single level memory module further transmits the data to the multi level memory module through the first and second data buses coupled therebetween without passing the data through the controller. | 01-26-2012 |
| 20110289255 | APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE - A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses. | 11-24-2011 |
| 20110280074 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a flash memory. First, a target block for storing write data is selected from a plurality of blocks of the flash memory. A target pair page is then selected from a plurality of pair pages of the target block according to a pair page record table, wherein the pair page comprises a strong page and a weak page. The flash memory is then directed to write a data page of the write data to the strong page of the target pair page. The flash memory is then also directed to write first predetermined data to the weak page of the target pair page, wherein the weak page storing the first predetermined data extends the data duration of the strong page of the target pair page. Selecting of the target pair page, writing of the data page, and writing of the first predetermined data are repeated until all of the write data are written to the target block. | 11-17-2011 |
| 20110264847 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the memory is received from a host. The spare blocks of the spare area are then sorted according to the erase counts of the spare blocks. A first spare block with the least erase counts is then selected from the spare blocks of the spare area. The write data is then written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block. | 10-27-2011 |
| 20110258369 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the flash memory is received from a host. A first spare block with the earliest erase time index is then selected from the spare area. Whether an erase count of the first spare block is less than a first threshold is then determined When the erase count of the first spare block is less than the first threshold, the write data is written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block. | 10-20-2011 |
| 20110197107 | NON-VOLATILE MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF - A data processing method for a non-volatile memory device is provided. The non-volatile memory device includes a controller and a NAND flash memory. First, a target command and a corresponding target address are serially transmitted from the controller to the NAND flash memory. Then, the NAND flash memory calculates a first value according to the target address. Moreover, a cyclic redundancy check code corresponding to the target address is transmitted from the controller transmits to the NAND flash memory. Next, the NAND flash memory determines whether a transmission error has occurred by performing a cyclic redundancy check according to the first value and the cyclic redundancy check code. When the transmission error has occurred, a status register is set to inform the controller to re-transmit the target command and the corresponding target address. | 08-11-2011 |
| 20110179306 | Data Read Method for Flash Memory - The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code. | 07-21-2011 |
| 20110179249 | Data Storage Device and Method for Handling Data Read Out from Memory - The invention provides a method for handling data read out from a memory. In one embodiment, a controller corresponding to the memory comprises a ping-pong buffer. First, a first sector read time period required by the memory to read and output a data sector to the ping-pong buffer is calculated. A second sector read time period required by a host to read a data sector from the ping-pong buffer is calculated. A page switch time period required by the memory to switch a target read page is obtained. A total sector number is determined according to the first sector read time period, the second sector read time period, and the page switch time period. When the memory outputs data to the ping-pong buffer, a first buffer and a second buffer of the ping-pong buffer are switched to receive the data output by the memory according to the total sector number. | 07-21-2011 |
| 20110179217 | Flash Storage Device and Data Access Method of Flash Memory - The invention provides a data access method of a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined from the flash memory. Whether a storage space corresponding to the write address in the target block has stored data therein is then determined When the storage space of the target block does not have stored data therein, the target data is written into the storage space of the target block. When the storage space of the target block does have stored data therein, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists in the flash memory, the target data is written into the child block. | 07-21-2011 |
| 20110179216 | Data Storage Device and Data Access Method - The invention provides a data access method for a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined. Whether a storage space with the write address in the target block stores data is then determined. When the storage space does not store data, the target data is written to the storage space of the target block. When the storage space stores data, whether a file allocation table (FAT) block mapped to the target block exists in the flash memory is then determined. When the FAT block exists, the target data is written to the FAT block. When the FAT block does not exist, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists, the target data is written to the child block. | 07-21-2011 |
| 20110164490 | FAST FOURIER TRANSFORM AND INVERSE FAST FOURIER TRANSFORM (FFT/IFFT) OPERATING CORE - An FFT/IFFT operating core capable of minimizing a required memory depth during operation is disclosed. The FFT/IFFT operating core includes an inputting buffer, a first multiplexer, an operating module, and a controlling module. The inputting buffer stores and outputs a first FFT input sequence. The first multiplexer is utilized to multiplex the first FFT input sequence and a third input sequence. The controlling module generates a process indicating signal and a bypass indicating signal. The operating module has a plurality of operating stages in series. The operating module transforms the first and third FFT input sequences into a first and third FFT output sequences, respectively, and it transforms a second IFFT input sequence into a second IFFT output sequence. | 07-07-2011 |
| 20110161566 | WRITE TIMEOUT CONTROL METHODS FOR FLASH MEMORY AND MEMORY DEVICES USING THE SAME - A write timeout control method for a flash memory having a plurality of spare blocks and data blocks including a plurality of mother blocks is disclosed. The method includes the steps of: receiving a write command and a starting logical block address; determining an update mode according to a target mother block linked to the starting logical block address; determining whether a pre-clean operation is performed on a first mother block; if so, performing a post-clean operation on the first mother block during a first time period; re-configuring the first mother block as a spare block; performing a programming process to write data on the target mother block; determining whether the number of mother blocks exceeds a first threshold; and if so, performing the pre-clean operation on a second mother block. The first and second mother blocks are configured as blocks to be cleaned. | 06-30-2011 |
| 20110153918 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method for a flash memory. First, a write command, a write address, and write data are received from a host. When a total number of block pairs in the flash memory is equal to a threshold value, and execution of the write command increases the total number of block pairs, the write data is written to a data buffer block of the flash memory, and the write address is stored in an address storage table. A target block pair comprising a target mother block and a target child block is then selected from the block pairs for integration. The target mother block and the target child block are integrated into an integrated block during receiving intervals of a plurality of subsequent write commands. Finally, the write command is executed according to the write data stored in the data buffer block and the write address stored in the address storage table. | 06-23-2011 |
| 20110141030 | Touch Control Apparatus and Touch Point Detection Method - A touch control apparatus, having a touch pad receiving contact from at least one object is provided. Four edges form a rectangle that encircles the touch pad. All the edges are surfaced with geometric textures. A first camera is deposited on a corner of the first edge and the fourth edge of the rectangle, having a field of view sufficient to collect a first image including the second edge and third edge of the rectangle. A second camera is deposited on a corner of the second edge and the fourth edge of the rectangle, having a field of view sufficient to collect a second image including the first edge and third edge of the rectangle. A calculation unit performs a characteristic extraction process on the geometric textures of the first and second images to determine whether an object has touched the touch pad, and if so, coordinates thereof are determined. | 06-16-2011 |
| 20110134281 | CAMERA DEVICE AND IMAGE PROCESSING METHOD - The invention provides a camera device. In one embodiment, the camera device comprises a sensor and a controller. The sensor detects an image to generate a first image signal with an RGB format. The controller comprises an image processor and a subsequent processor. The image processor converts the first image signal to a second image signal with a YUY2 format. The subsequent processor adjusts a plurality of luma components, a plurality of first chroma components, and a plurality of second chroma components of the second image signal to obtain a plurality of adjusted luma components, a plurality of first adjusted chroma components, and a plurality of second adjusted chroma components of a third image signal. A host receives the third image signal output by the camera, and uses a Direct Show module to convert the third image signal to a fourth image signal with an RGB format. | 06-09-2011 |
| 20110125955 | FLASH STORAGE DEVICE, DATA STORAGE SYSTEM, AND DATA WRITING METHOD - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of storage units for data storage, wherein the total capacity of each of the storage units is equal to a storage unit capacity. When the flash storage device receives a read capacity command from a host, the controller determines the size of a logical block to be a specific multiple of the storage unit capacity, and sends information about the logical block size to the host in response to the read capacity command, wherein the specific multiple is a natural number. After the host receives the information from the flash storage device, the host retrieves the logical block size from the information, and sends only write data with an amount equal to a multiple of the logical block size to the flash storage device. | 05-26-2011 |
| 20110119430 | METHODS FOR MEASURING USABLE LIFESPAN AND REPLACING AN IN-SYSTEM PROGRAMMING CODE OF A MEMORY DEVICE, AND DATA STORAGE SYSEM USING THE SAME - A data storage system comprises a host and a flash memory device having a non-non-volatile memory. A controller of the flash memory device calculates an average erase count of the flash memory to obtaining a remaining period of time indicating usable lifespan of the flash memory device. The host obtains an index by comparing the average erase count with a first threshold and determines a performance capability status for the flash memory device. The performance capability status is set to a first status when the average erase count exceeds the first threshold. The host generates an indication based on the performance capability status and performs a limp function responsive to the first status. The limp function loads a predetermined in-system programming code for replacing an original one to configure a minimum number of at least some spare blocks of the flash memory reserved and used for data update operations. | 05-19-2011 |
| 20110107141 | DATA STORAGE DEVICE, CONTROLLER, AND DATA ACCESS METHOD FOR A DOWNGRADE MEMORY - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses. | 05-05-2011 |
| 20110089535 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively. | 04-21-2011 |
| 20110087829 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address. | 04-14-2011 |
| 20110084938 | TOUCH DETECTION APPARATUS AND TOUCH POINT DETECTION METHOD - A touch detection apparatus is provided, in which a touch panel is implemented with four surrounding edges. Three of the edges are embedded with retro-reflection materials. Light sources and pinholes are deployed on both corners of the touch panel, allowing reflections from the three edges to be projected on light sensors through the pinhole. The images projected on the light sensors are analyzed to determine coordinates of one or more contact points on the touch panel. | 04-14-2011 |
| 20110078393 | MEMORY DEVICE AND DATA ACCESS METHOD - The invention provides a data access method. First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. Whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue is then determined. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to a memory to request that the memory executes the write commands. | 03-31-2011 |
| 20110078365 | DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. | 03-31-2011 |
| 20110035645 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a memory and a controller. The memory is for data storage. When the data storage device receives first source data to be written to the memory from a host, the controller generates at least one first input data according to the first source data, scrambles the first input data according to a plurality of pseudo random sequences to obtain a plurality of first scrambled signals, calculates a plurality of transmission powers of the first scrambled signals, and selects a target scrambled signal with a lowest transmission power to be stored in the memory from the first scrambled signals. | 02-10-2011 |
| 20110035636 | DATA STORAGE DEVICE AND METHOD FOR WRITING TEST DATA TO A MEMORY - The invention provides a method for writing test data to a memory. In one embodiment, the memory comprises a data register. First, test data is written to a memory space of the memory. A read-back command and a read-back address of the memory space are then sent to the memory to direct the memory to read the test data from the memory space to the data register. A copy-back command and a copy-back command in a test range of the memory are then sent to the memory to direct the memory to write the test data stored in the data register to the copy-back address. Finally, when the test range of the memory has not been filled with the test data, the step of sending the read-back command and the read-back address is repeated, and the step of sending the copy-back command and the copy-back address is repeated. | 02-10-2011 |
| 20110032418 | IMAGE PROCESSING DEVICE AND DEINTERLACING METHOD THEREOF - An image processing device and a deinterlacing process thereof are provided. The deinterlacing process reads a memory to retrieve ten pixels of an image field that are temporarily stored in the memory, wherein the ten pixels are located on a first column, a second column, a third column, a fourth column and a fifth column of a first row and a second row of the image filed. Then, the deinterlacing process estimates the data of an interpolated pixel according to the data of the ten pixels. The interpolated pixel is inserted between the first and second rows of the image field on the third column to form a deinterlaced image frame. | 02-10-2011 |
| 20110029741 | DATA MANAGEMENT METHOD AND MEMORY DEIVCE - The invention provides a data management method for a memory device. In one embodiment, the memory device comprises a plurality of memories for data storage. First, write data and a write logical address is received from a host. The write logical address is then converted to a write physical address. A target memory corresponding to the write physical address is then determined. Whether the target memory is in a busy state is then checked. When the target memory is in the busy state, the write data is written to a buffer area of a substitute memory of the target memory. | 02-03-2011 |
| 20110029720 | Flash Storage Device and Operation Method Thereof - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table. | 02-03-2011 |
| 20110022886 | DATA STORAGE DEVICE AND DATA READ METHOD - The invention provides a data read method. First, a training sequence stored in a storage unit of a memory is read according to at least one sense voltage to obtain a read-out training sequence. Whether the read-out training sequence is correct is then determined. When the read-out training sequence is not correct, the sense voltage is adjusted. | 01-27-2011 |
| 20110010603 | METHOD FOR PREVENTING DATA SHIFT ERRORS AND CONTROLLER USING THE SAME - A method for preventing a data storage device from data shift errors is provided. First, data is encoded into an error correction code. The error correction code is then scrambled to obtain a scrambled code to be stored in a memory. The scrambled code is then retrieved from the memory to obtain first read-out data. The first read-out data is then descrambled to obtain a first descrambled error correction code. The first descrambled error correction code is then decoded to determine whether the first descrambled error correction code has uncorrectable errors. When the first descrambled error correction code has uncorrectable errors, the scrambled code stored in the memory is read again to output second read-out data without shift errors. Following, the second read-out data is then descrambled to obtain a second descrambled error correction code, and the second descrambled error correction code is then decoded to recover the data. | 01-13-2011 |
| 20110004812 | CODER-DECODER AND METHOD FOR ENCODING AND DECODING AN ERROR CORRECTION CODE - The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data. | 01-06-2011 |
| 20100332731 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME AND DATA STORAGE SYSTEM - A flash memory apparatus is provided. In one embodiment, the flash memory apparatus with a plurality of operation states is coupled to a host and includes a controller having an engine and a register array. A state machine logic circuit of the engine is provided for transition of the operation states and the register array provides state transition information. When a command is received from the host, the engine obtains the state transition information from the register array according to a first operation state and determines whether the valid command is one of a plurality of valid commands corresponding to the first operation state. The state machine logic circuit determines transition to the operation states according to the state transition information. The transition of the first operation state to the second operation state is performed in response to the valid command. | 12-30-2010 |
| 20100318840 | MEMORY CARD, NONVOLATILE MEMORY, CONTROLLER, AND METHOD FOR MANAGING WRITING ERRORS FOR NONVOLATILE MEMORIES - The invention provides a method for managing writing errors for a nonvolatile memory. In one embodiment, the nonvolatile memory is coupled to a controller. First, data received from the controller is stored in a data register of the nonvolatile memory. The data stored in the data register is then written to a first memory space with a first write address according to instructions from the controller. The data stored in the data register is kept from being changed after the data is written to the first write address. When an error occurs in writing of the data to the first memory space, a rewrite command is sent from the controller to the nonvolatile memory. After the nonvolatile memory receives the rewrite command, the data stored in the data register is written to a second memory space with a second write address according to the rewrite command. | 12-16-2010 |
| 20100308789 | BAND GAP REFERENCE VOLTAGE GENERATOR - A band gap reference voltage generator with low working voltage is disclosed. The band gap reference voltage generator can stably operates that the unexpected balance status does not occur due to the manufacturing process inaccuracy or the offset voltage. The band gap reference voltage generator comprises a thermal voltage generation circuit, a voltage level optimizing circuit and a band gap reference voltage generating circuit. The thermal voltage generating circuit provides a first voltage and a second voltage. The first voltage is for generating a current component increased with temperature rising. The second voltage is for generating a current component decreased with temperature rising. The voltage level optimizing circuit optimizes the voltage level of the second voltage to generate a third voltage. The band gap reference voltage generating circuit generates the reference voltage with a specific voltage level corresponding to the first voltage and the third voltage irrelevant with the temperature. | 12-09-2010 |
| 20100308470 | SEMICONDUCTOR DEVICE AND INDUCTOR - A semiconductor device and an inductor are provided. The semiconductor device includes a top level interconnect metal layer (M | 12-09-2010 |
| 20100306619 | CONTROLLER AND DATA ACCESS METHOD FOR FLASH MEMORIES - The invention provides a controller. In one embodiment, the controller is coupled to a flash memory and a host, and comprises a selective mapper and an error correction code encoder. The selective mapper receives first source data, processes the first source data according to a plurality of pseudo random sequences to obtain a plurality of first mapped data segments, calculates a plurality of cross correlation values between prior data and the first mapped data segments, selects an optimal mapped data segment from the first mapped data segments according to the cross correlation values, and generates output mapped data according to the optimal mapped data segment. The error correction code encoder encodes a first error correction code to be stored in the flash memory according to the output mapped data. | 12-02-2010 |
| 20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 12-02-2010 |
| 20100289481 | APPARATUS AND METHOD FOR DC VOLTAGE MEASUREMENT - The invention provides a method for DC voltage measurement. First, an input DC voltage is received. A temporary disturbance signal is then added to the input DC voltage to obtain a disturbed signal, wherein an amplitude of the temporary disturbance signal is greater than precision level of an analog-to-digital converter. The disturbed signal is then converted from analog to digital with the analog-to-digital converter to obtain a plurality of samples with different values. An average value is then derived from the samples. Finally, the average value is output as a measurement value of the input DC voltage. | 11-18-2010 |
| 20100268868 | FLASH STORAGE DEVICE AND OPERATING METHOD THEREOF - The invention also provides a flash storage device. In one embodiment, the flash storage device is coupled to a host, and comprises a random access memory and a controller. The random access memory stores a plurality of link tables therein, wherein each of the link tables corresponds to one of a plurality of management units of at least one flash memory, and the link tables store corresponding relationships between logical addresses and physical addresses of the corresponding management units. The controller receives an access logical address from the host, determines an access physical address corresponding to the access logical address according to the link tables stored in the random access memory, and accesses data from the flash memory according to the access physical address. | 10-21-2010 |
| 20100217918 | DATA STORAGE DEVICE AND METHOD FOR ACCESSING FLASH MEMORY - The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an address link table records a mapping relationship between a plurality of logical addresses and a plurality of physical addresses. First, first data to be written to a first logical address is received from a host. Whether the first data is predetermined data is the determined. Whether the first logical address is mapped to a null physical address is then determined according to the address link table. When the first data is the predetermined data and the first logical address is not mapped to the null physical address according to the address link table, the address link table is modified to map the first logical address to the null physical address. | 08-26-2010 |
| 20100211722 | METHOD FOR TRANSMITTING SPECIAL COMMANDS TO FLASH STORAGE DEVICE - The invention provides a data storage system. In one embodiment, the data storage system comprises a host and a flash storage device. The host sends a series of first access commands for accessing a plurality of special files to the flash storage device. The flash storage device having the stored plurality of special files and a command-symbol mapping table, sequentially generates a plurality of first digits respectively corresponding to the special files accessed by the first access commands to obtain a first data stream, converts the first data stream to a plurality of first special commands according to the command-symbol mapping table, and performs operations according to the first special commands. Each of the special files corresponds to a digit, the command-symbol mapping table records a corresponding relationship between a plurality of symbols and a plurality of special commands, and each of the symbols comprises a plurality of digits. | 08-19-2010 |
| 20100199156 | Method And Circuit For Encoding An Error Correction Code - The invention provides a method for decoding an error correction code. First, an error syndrome of the error correction code is calculated. A plurality of coefficients of an error locator polynomial of the error correction code is then sequentially determined according to the error syndrome. When a new coefficient of the error locator polynomial is determined, it is also determined whether the new determined coefficient is equal to zero. When the new determined coefficient is equal to zero, a speculated error locator polynomial is built according to a plurality of low-order-term coefficients of the error locator polynomial, wherein the orders of the low-order-term coefficients are lower than that of the new determined coefficient. A Chien search is then performed to determine a plurality of roots of the speculated error locator polynomial. The error correction code is then corrected according to the roots of the speculated error locator polynomial. | 08-05-2010 |
| 20100174852 | METHOD FOR OPERATING NON-VOLATILE MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks haing a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations. | 07-08-2010 |
| 20100169547 | METHOD FOR PREVENTING DATA LOSS DURING SOLDER REFLOW PROCESS AND MEMORY DEVICE USING THE SAME - The invention provides a method for preventing data loss in a flash memory during a solder reflow process. The flash memory includes a plurality of memory blocks and each memory block includes a plurality of strong pages and weak pages. Preloading data is first received and stored into the strong pages of at least one of first memory block within the flash memory. Then, the flash memory is heated for the solder reflow process. Next, the preloading data is reorganized according to a trigger signal and the strong pages and weak pages of at least one of second memory block within the flash memory are provided for storing the reorganized preloading data. | 07-01-2010 |
| 20100153624 | DATA MANAGING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A data managing method for non-volatile memory which comprises a step for receiving a first logical block address and updated data, and a step for merging data in a plurality of physical blocks which have lowest usage rates according to usage parameters in a reference table when the first logical address doesn't exist in the reference table in a buffer memory and a number of pair blocks reaches a determined number. | 06-17-2010 |
| 20100153623 | Data Managing Method for Flash Memory and Flash Memory Device Using the Same - A data management method for a flash memory apparatus, entailing a step for handling a plurality of flash chips, a step for enabling the flash chips in sequence, and a step for updating the first data in the first block on the first flash chip among the flash chips. Additionally there is a step for updating f writing of the first new data corresponding to the first data into a second block in a second flash chip among the flash chips, and a step merging the first block and the second block, wherein both of the first new data and the first data are corresponding to a first logical block address. | 06-17-2010 |
| 20100106892 | Access Methods For Memory Devices And Memory Devices Thereof - An access method for use in a memory device is provided. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host. | 04-29-2010 |
| 20100100665 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - The invention discloses a flash memory apparatus, including a plurality of blocks and a memory controller. The blocks include a first block, wherein the first block includes a first page. The memory controller receives a first data to be written into the first page of the first block. When the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records the number of the first block and the number of the first page into the first cache page. The memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page when receiving an update command. | 04-22-2010 |
| 20100095148 | LINK TABLE RECOVERY METHOD - A link table recovery method for a flash memory having a plurality of blocks is provided. The method includes: selecting one block from the blocks; selecting a last page containing data of the selected block; checking the last page to determine whether the last page has errors; moving the correct data in the selected block to one of the spare blocks when the last page of the selected block detects errors; and updating a link table of the flash memory. | 04-15-2010 |
| 20100091132 | IMAGE CAPTURING DEVICE AND IMAGE PREPROCESSING METHOD THEREOF - An image capturing device and the image preprocessing method thereof. The image preprocessing technique receives digital image consisting of luma data and chrominance data, integrates the chrominance data of adjacent rows to generate integrated chrominance data, buffers the luma data and the integrated chrominance data in a group of line buffers, and generates pre-processed chrominance data by making adjacent rows share the same integrated chrominance data. The luma data from the line buffer group form an image with the pre-processed chrominance. The image may be displayed on a display. | 04-15-2010 |
| 20100088462 | METHODS FOR HANDLING DATA UPDATING OF FLASH MEMORY AND RELATED MEMORY CARDS - A method for handling data updating of a flash memory is disclosed, in which the flash memory comprises a mother block with a plurality of pages to be updated, and each page comprises a plurality of sectors. In such method, a first data for updating a target page in the mother block is obtained, and then whether the first data comprises data for updating an ending sector in the target page is determined. The first data is written into a replacing page in a first FAT block when the first data does not comprise data for updating the ending sector in the target page. The first data is written into a corresponding page in a second FAT block when the first data comprises the data for updating the ending sector, in which the corresponding page in the second FAT block and the target page in the mother block have the same page indexes. | 04-08-2010 |
| 20100085450 | Cameras And Defective Pixel Compensation Methods For Image Sensors Thereof - A camera with defective pixel compensation is provided. The camera comprises a register and a compensating unit. The compensating unit receives an image datum and a plurality of adjacent image data relating to the image datum and, according to the value installed in the register, the compensator selects a reference datum from the plurality of adjacent image data. When the image datum is greater than the reference datum by a threshold value, the compensating unit modifies the image datum according to the reference datum. | 04-08-2010 |
| 20100077132 | MEMORY DEVICES AND ACCESS METHODS THEREOF - Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable. | 03-25-2010 |
| 20100070688 | FLASH MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, and writes the data to the strong pages of the first blocks of the turbo area when the data is important data. | 03-18-2010 |
| 20100067811 | IMAGE DECODING APPARATUS AND METHOD - An image decoding apparatus is provided, including a parser and an AC decoder. The parser is provided for parsing a bit stream to acquire a first unit. The first unit includes a DC code and a plurality of AC codes respectively corresponding to a DC coefficient and AC coefficients for a first block of the image. The AC decoder generates a plurality of first AC coefficients for the first block by decoding the plurality of AC codes of the first unit, and determines whether the number of the plurality of first AC coefficients exceeds a predetermined parameter. If so, the AC decoder obtains a second unit of the bit stream corresponding to a second block following the first block by performing an AC bypassing process on the first unit. Each AC code comprises a Huffman code and a VLI code. | 03-18-2010 |
| 20100066848 | IMAGE PROCESSING DEVICE AND METHOD - An image processing device including a camera, a discrete signal processor (DSP) and an output device is disclosed. The camera provides image data for the DSP to process. The DSP samples sub-image data to generate a first image processing signal, discrete cosine transforms the first image processing signal to generate a second image processing signal, uses a quantization table to quantize the second image processing signal to generate a third image processing signal, zig-zag scans the third image processing signal to generate a fourth image processing signal, and Huffman codes the fourth image processing signal to generate an output image signal. The DSP adjusts a cut point of a next fourth image processing signal according to the size of the fourth image processing signal so as to control the size of a next output image signal. The output device outputs the output image signal. | 03-18-2010 |
| 20100011173 | Downgrade Memory Apparatus, and Method for Accessing a Downgrade Memory - A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information. | 01-14-2010 |
| 20100011152 | DATA PROGRAMMING METHODS AND DEVICES - A data programming device is provided and comprises a non-volatile memory, a volatile memory, and a memory control unit. The non-volatile memory is arranged for programming data. The volatile memory is arranged for temporarily storing data. The memory control unit is arranged for receiving data and determining whether the data is programmed into the non-volatile memory or stored into the volatile memory. If the data exceeds one page, the memory control unit programs a first portion of the data into the non-volatile memory and stores a second portion of the data, which is insufficient for one page, into the volatile memory. | 01-14-2010 |
| 20100005230 | DATA STORING METHODS AND APPARATUS THEREOF - A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether the writing data is larger than one page. The writing data is divided into a plurality of page data according to the memory size of the page when the writing data is larger than one page. Next, a first storing page for each page data is determined according to a starting writing page according to the logic block writing command. And, the page data are sequentially written into the first storing pages. Note that each first storing page is a strong page within the memory block. | 01-07-2010 |
| 20100005229 | FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE - A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last weak page is then determined. A plurality of strong pages between the first strong page and the last weak page are then determined. Data of the plurality of strong pages is the coped to a backup area of the flash memory for data recovery. | 01-07-2010 |
| 20090327586 | MEMORY DEVICE AND DATA STORING METHOD - A memory device is provided, comprising a single-level memory unit, a multi-level memory unit and a control unit. The single-level memory unit comprises a first link table and stores data according to the first link table. The multi-level memory unit comprises a second link table and stores data according to the second link table. The control unit directs data which normally belongs to the single-level memory unit to the multi-level memory unit or directs data which normally belongs to the multi-level memory unit to the single-level memory unit according to a control signal. | 12-31-2009 |
| 20090327550 | EMBEDDED SYSTEM AND HARDWARE SETTING METHOD - An embedded system is provided, comprising a non-volatile memory, at least one slave unit and a master controller. The non-volatile memory comprises at least one hardware setting value and at least one identification number. All of the non-volatile memory, slave unit and the master controller are coupled to a bus. The master controller broadcasts an identification number through the bus to identify the non-volatile memory. Then, the master controller retrieves the slave identification numbers and the hardware setting values through the bus from the non-volatile memory. | 12-31-2009 |
| 20090319721 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - The invention provides a method for operating a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a single-level-cell memory and a multiple-level-cell memory. First, new data for updating a logical block address is received from a host. An update count corresponding to the logical block address is then compared with a threshold value. When the update count is greater than the threshold value, it is determined whether a first physical block address corresponding to the logical block address is pointing to a multiple-level-cell block of the multiple-level-cell memory. When the first physical block address is pointing to the multiple-level-cell block, a target single-level-cell block is then selected from the single-level-cell memory. A corresponding relationship between the logical block address and a second physical block address of the target single-level-cell block is then built. The new data is then written to the target single-level-cell block with the second physical block address. | 12-24-2009 |
| 20090313512 | APPARATUS AND METHOD FOR MEMORY CARD TESTING - The invention provides a memory card testing apparatus for performing automated operations on memory cards. The memory card testing apparatus comprises a host device, a database, a processing unit and an interface. The host device is provided for accessing a memory card. The database maintains a plurality of test script files to be processed. The processing unit is coupled to the database for selecting a test item from one of the plurality of test script files according to a device identification number corresponding to a target device to be tested and a communication protocol associated with the memory card. The interface is connected to the processing unit and the host device for enabling the host device to execute at least one card command on the memory card according to the test item. | 12-17-2009 |
| 20090300753 | METHOD FOR PREVENTING DATA IN A COMPUTER SYSTEM FROM BEING ACCESSED BY UNAUTHORIZED USER - A computer system is provided comprising a non-volatile storage medium and a processor. The processor acquires authentication information from a first removable storage device, stores the authentication information into the non-volatile storage medium, and forbids data access of the computer system when detecting that a second removable storage device has been inserted and identification data of the second removable storage device is different from the authentication information. | 12-03-2009 |
| 20090287875 | MEMORY MODULE AND METHOD FOR PERFORMING WEAR-LEVELING OF MEMORY MODULE - The invention comprises a memory module capable of wear-leveling. In one embodiment, the memory module comprises a flash memory and a controller. The flash memory comprises a plurality of management units, wherein each of the management units comprises a plurality of blocks. The controller receives new data with a logical address managed by a first management unit selected from the management units, pops a first spare block from a spare area of the first management unit, determines whether an erase count of the first spare block is greater than a first threshold value, searches a second management unit selected from the management units for a replacing block with an erase count lower than a second threshold value when the erase count of the first spare block is greater than the first threshold value, and directs the first management unit and the second management unit to exchange the first spare block with the replacing block. | 11-19-2009 |
| 20090285507 | METHOD AND DEVICE FOR SCALING-UP OR SCALING-DOWN IMAGES WITH THE SAME HARDWARE - An image processing device is provided, which scales-up or scales-down images with the same hardware. The device of this invention comprises a line buffer, a first variable, a second variable and a scaler. The scaler practices a scaling-down procedure to scale-down images or scaling-up procedure to scale-up images. | 11-19-2009 |
| 20090283918 | SEMICONDUCTOR CHIP PACKAGE STRUCTURE - A semiconductor chip package structure is described. The semiconductor chip package structure comprises a first chip, which is operated through a first power connection, having a central region and a marginal region. The first chip comprises a plurality of first and second power bonding pads disposed in a marginal region on the top of the first chip. A first power ring and a second power ring are disposed on the first chip, wherein the first and second power rings are respectively electrically connected to the first and second power bonding pads. A second chip, which is operated through a second power connection, is mounted on the central region of the first chip, wherein the second chip comprises a plurality of power bonding pads thereon. A plurality of second bonding wires are electrically connected to the power bonding pads and the second power bonding pads, respectively. | 11-19-2009 |
| 20090265503 | Non-Volatile Memory Apparatus and Method for Accessing a Non-Volatile Memory Apparatus - A non-volatile memory apparatus and a method for accessing the non-volatile memory apparatus are provided. The non-volatile memory apparatus comprises a management unit, a look-up table and a controller. The management unit comprises a plurality of data blocks and a plurality of spare blocks. The look-up table is adapted to record the read status of the management unit. The controller is configured to read the management unit and then generate the read status denoting the times that the management unit has been read to the look-up table, and to replace one of the data blocks by one of the spare blocks in response to the read status when the times that the management unit has been read exceeds a reference value. | 10-22-2009 |
| 20090214087 | METHOD AND COMPUTER SYSTEM USING A WEBCAM FOR PROTECING DIGITAL DATA - A method and computer system for digital data protection by using a webcam, comprising: generating a user's biometric feature image; comparing the biometric feature image with identification data; concealing specific data in the computer when the biometric feature image does not conform to the identification data. | 08-27-2009 |
| 20090209221 | RECEIVER WITH LOW POWER CONSUMPTION - The present invention provides a receiver with low power consumption. The receiver with low power consumption adjusts the gain of the programmable gain amplifier based on the automatic gain controller and further optimizes the gain bandwidth product by current-adjusting unit. The current-adjusting unit thus adjusts the current provided for the programmable gain amplifier, e.g. operational amplifier. Therefore, the gain bandwidth product of the programmable gain amplifier is optimized and the power consumption of the receiver is effectively decreased. | 08-20-2009 |
| 20090209220 | RECEIVER HAVING LOW POWER CONSUMPTION AND METHOD THEREOF - The present invention provides a receiver having low power consumption and method thereof. The receiver with low power consumption adjusts the gain based on the automatic gain control information. The receiver acquires the signal peaks both after and before a channel selection filter and further analyzes the wanted signal and interference signal with respect to the signal peaks. The receiver determines the magnitude of the wanted signal and determines whether the interference signal exists. The receiver provides the signals with optimal current correspondingly in order to effectively decrease the power consumption of the receiver. | 08-20-2009 |
| 20090195316 | RE-CONFIGURABLE LOW NOISE AMPLIFIER UTILIZING FEEDBACK CAPACITORS - A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure. | 08-06-2009 |
| 20090157947 | Memory Apparatus and Method of Evenly Using the Blocks of a Flash Memory - A memory apparatus and a method of evenly using the blocks of a flash memory are provided. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. The controller is configured to receive data corresponding to the first data block, select a spare block, program data into the spare block when the erase count corresponding to the spare block is less than the predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value. As a result, the blocks of the flash memory are used evenly. | 06-18-2009 |
| 20090144488 | MEMORY CARD AND METHOD FOR HANDLING DATA UPDATING OF A FLASH MEMORY - The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block. | 06-04-2009 |
| 20090119448 | Memory Apparatus, and Method of Averagely Using Blocks of a Flash Memory - A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of erasion of blocks. | 05-07-2009 |
| 20090113154 | Non-Volatile Memory Apparatus and Method of Accessing the Same - A non-volatile memory apparatus and an accessing method thereof are provided. A host accesses the non-volatile memory apparatus and gets the accessing result according to the predetermined protocol. Therefore, the host can identify whether the non-volatile memory apparatus has a data area or not and switch to access the data area. The host can then access the non-volatile memory apparatus with high capacity without changing the hardware of the host. | 04-30-2009 |
| 20090106519 | Storage Device and Method of Accessing a Status Thereof - A storage device and a method of accessing a status thereof are provided. The storage device is disposed in a host. The device data structure field of the storage device is adapted to record the status of the non-volatile memory. The control module is adapted to access the status according to a control signal from the host. Therefore, the operating system or the application of the host is capable of getting the status of the non-volatile memory to ensure the safety of the stored data. | 04-23-2009 |
| 20090070655 | Method for Generating an ECC Code for a Memory Device - A method for generating an ECC for a flash memory device is provided. The flash memory device only supports flash memories with low-level ECC technology, such as SLC (single-level cell) flash memories. By using a controller with an ECC engine, the flash memory device can directly generate a correct ECC for itself when it reads data from flash memories with high-level ECC technology, such as MLC (multi-layer cell) flash memories. Thus the flash memory device can also support flash memories with high-level ECC technology and reduce the time of reading data. | 03-12-2009 |
| 20090049233 | Flash Memory, and Method for Operating a Flash Memory - A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained. | 02-19-2009 |
| 20080315854 | Input/Output Regulating Circuitry with Self-Electrostatic-Discharge Protection - An I/O regulating circuitry is provided. The I/O regulating circuitry omits the ESD device in a CMOS process with a minimized critical dimension to reduce chip size while still maintaining electrostatic discharge immunity. The I/O regulating circuitry is applied in MLC flash memory applications and the flash controller thereof. | 12-25-2008 |
| 20080313390 | Method and System for Presenting an Executing Status of a Memory Card - A system and a method for presenting an executing status of a memory card are provided. The system comprises a processing apparatus and an access device. The processing apparatus stores an application program having a plurality of icons. The access device connects the memory card and the processing apparatus. The processing apparatus sends a reading command to the memory card via the access device. The memory card sends executing information in reply after receiving the reading command. Finally, the processing apparatus analyzes the executing information of the memory card and presents a corresponding icon through the application program in association with the analytic result. | 12-18-2008 |
| 20080301497 | Testing Apparatus, System, and Method for Testing at Least One Device with a Connection Interface - A system, a testing apparatus, and a method for testing at least one device with a connection interface are provided. The system comprises a host, a testing apparatus, and a power supply. The testing apparatus further comprises a microprocessor and at least one current limit module. The host sending a test signal. The power supply provides a voltage to the testing apparatus. The at least one current limit module of the testing apparatus, which is electrically connected to the microprocessor, the at least one device, and the power supply, provides the voltage to the at least one device. When the current passing through the at least one device is greater than the predetermined value, the at least one current limit module of the testing apparatus stops providing the voltage to the at least one device and sends an over current signal to the host via the microprocessor. | 12-04-2008 |
| 20080256629 | Management Apparatus, System, and Method for Protecting a Memory Storage Card - A management apparatus, system, and method for protecting a memory storage card are provided. The management apparatus comprises an access unit and a check unit. The access unit is configured to read a first security message, and a second security message of the memory storage card. The check unit is configured to check the first and second security messages to generate a check result. The management apparatus makes the memory storage card available according to the check result and efficiently prevents the memory storage card from theft. | 10-16-2008 |
