| SILICON LABORATORIES, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120001862 | CAPACITIVE TOUCH SWITCH DISPLAY CONTROL SYSTEM AND METHOD - A capacitive touch switch display control system includes multiple capacitive touch switches and respective LED displays that light to indicate the status of the system. A microcontroller unit (MCU) interface includes a shared function pin for each touch switch-LED pair. The MCU configures the shared function pin as an analog pin for very brief first time periods during which the MCU disables the LED displays and conducts capacitive sensing of the touch switches connected thereto to determine their status. After the first time period, the MCU enables the LED displays for potential lighting during a second time period. During the second time period, the MCU configures the shared function pin as a digital I/O LED control pin to either light or not light the LED display to indicate the status of the system. The first time period during which the MCU conducts capacitive sensing of the touch switches is sufficiently brief that it does not interfere with LED lighting function. | 01-05-2012 |
| 20120001659 | Voltage-to-Current Converter with Feedback - A voltage-to-current converter includes a transconductance stage including an input configured to receive a scaled voltage signal, a first output to carry a first current based on the scaled voltage signal, and a second output to carry a second current that is proportional to the first current. The voltage-to-current converter further includes a digital feedback loop coupled to the second output of the transconductance stage and configured to adjust the scaled voltage signal based on an error between an external reference voltage and a sense voltage derived from the second current to compensate for changes in the scaled voltage signal. | 01-05-2012 |
| 20110316631 | LNA CIRCUIT FOR USE IN A LOW-COST RECEIVER CIRCUIT - A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal. | 12-29-2011 |
| 20110298509 | TIME-SHARED LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT - In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs. | 12-08-2011 |
| 20110298505 | LATENCY LOCKED LOOP CIRCUIT FOR DRIVING A BUFFER CIRCUIT - In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal. | 12-08-2011 |
| 20110266128 | Keypad System and Keypad with Enhanced Secutiry - In one form, a keypad includes a substrate and a flexible membrane disposed above a top surface of the substrate. The substrate has the top surface, a first conductor below the top surface, an insulator layer separating the first conductor from the top surface, and a second conductor disposed in proximity to the first conductor and to the top surface and coupled to a voltage terminal. The flexible membrane is disposed above the top surface of the substrate and has a third conductor forming a key. The third conductor is movable relative to the top surface. In another form, a keypad system includes such a keypad and a capacitive sensing circuit coupled to the first conductor for sensing a change in capacitance between the first conductor and the voltage terminal when the third conductor moves relative to the top surface. | 11-03-2011 |
| 20110258464 | Circuit and Method for Detecting a Legacy Powered Device in a Power over Ethernet System - In an embodiment, a power source equipment (PSE) device includes a network port configurable to couple to a network cable and a detection circuit coupled to the network port. The detection circuit is configured to apply a powered device (PD) detection voltage signal including first and second voltages to the network port and to sample a line current of the network port in response to the first and second voltages to detect a complex impedance indicating that a legacy PD is coupled to the network port. | 10-20-2011 |
| 20110254720 | Mismatch-Immune Digital-to-Analog Converter - In an embodiment, a digital-to-analog converter (DAC) includes inputs for receiving first and second signals encoded as a digital signal pair including overlapping low value portions that are substantially equal in duration to overlapping high value portions, within a frame. The DAC further includes an output terminal for providing an analog signal and includes first and second switches responsive to the first and second signals alter a level of the analog signal based on values of the first and second signals to provide a mismatch-immune DAC functionality. In one instance, the switches couple current sources to a common node. In another instance, the switches configure a resistive network to alter a resistance at an input to an amplifier. | 10-20-2011 |
| 20110248865 | SENSOR DEVICE WITH FLEXIBLE INTERFACE AND UPDATABLE INFORMATION STORE - A sensor device includes an interface that receives a request. The sensor device includes an updatable information store that responds to the request if the request is directed to the updatable information store, the updatable information store being in a first power domain of the sensor device. The sensor device also includes a power manager that activates a sensor element in the sensor device in response to receiving the request if the request is a request for measurement of a parameter by the sensor element. The sensor element is in a second power domain of the sensor device. The sensor element communicates measured parameter information to the updatable information store. | 10-13-2011 |
| 20110248152 | Apparatus and Circuit with a Multi-Directional Arrangement of Optical Elements - An apparatus includes a housing having a front surface, a rear surface, and at least one sidewall therebetween and a plurality of optical windows formed in the housing to allow light to pass through from multiple directions. The apparatus further includes a plurality of photo detectors to generate electrical signals based on received light, where each of the plurality of photo detectors is disposed within a respective one of the plurality of optical windows. The apparatus also includes a control circuit coupled to the plurality of photo detectors to receive the electrical signals, determine light variations from the electrical signals, and determine a change in position of an object based on variation ratios of the light variations received by at least one pair of photo detectors within the plurality of photo detectors in response to determining the light variations. | 10-13-2011 |
| 20110235758 | Mixed-Mode Receiver Circuit Including Digital Gain Control - A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages. | 09-29-2011 |
| 20110215848 | FREQUENCY SYNTHESIZER - A frequency synthesizer includes a controlled oscillator configured to extend a temperature range and phase noise of the synthesizer without compromising the frequency coverage of the synthesizer. The frequency synthesizer also includes bias generation circuitry that sets a bias current of a charge pump to reduce bandwidth variations of the synthesizer. The frequency synthesizer further includes switching circuitry to dynamically turn a charge pump on and off to reduce effects of current leakage in the charge pump. | 09-08-2011 |
| 20110181325 | CIRCUIT AND METHOD OF CLOCKING MULITIPLE DIGITAL CIRCUITS IN MULTIPLE PHASES - A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits. | 07-28-2011 |
| 20110158357 | ANTENNA DIVERSITY SYSTEM WITH FRAME SYNCHRONIZATION - In an embodiment, a tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor is to synchronize the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset, the digital signal processor configured to perform a selected antenna diversity operation on the first and second DSP frames to produce an output signal. | 06-30-2011 |
| 20110158339 | ANTENNA DIVERSITY SYSTEM WITH MULTIPLE TUNER CIRCUITS HAVING MULTIPLE OPERATING MODES AND METHODS - In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode. | 06-30-2011 |
| 20110158298 | TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME - A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link. | 06-30-2011 |
| 20110157140 | VOLTAGE CONTROL ON N-WELLS IN MULTI-VOLTAGE ENVIRONMENTS - An output pad control logic comprises an output buffer including a plurality of transistors connected to drive signals for an output pad. Each of the plurality of transistors includes an n-well. An n-well generator connects a first voltage to the n-wells of the plurality of transistors of the output buffer in a first mode of operation when a system rail voltage exceeds a pad voltage applied to the output pad. The n-well generator connects the pad voltage to the n-wells of the plurality of transistors of the output buffer in a second mode of operation when the pad voltage applied to the output buffer exceeds the system rail voltage. A switching circuit is responsive to at least one control signal to connect the system rail voltage as the first voltage when the output pad is not driving an LCD display and to connect a larger of the system rail voltage and an LCD drive voltage as the first voltage when the output pad is driving the LCD display. | 06-30-2011 |
| 20110157109 | HIGH-VOLTAGE CONSTANT-CURRENT LED DRIVER FOR OPTICAL PROCESSOR - An LED driver comprises a first transistor for setting an output current level at an output of the LED driver that is responsive to a programmable current and an input signal. A second transistor in series with the first transistor provides voltage protection for the first transistor. The first transistor and the second transistor support an output voltage higher than a maximum operating voltage of either of the first or the second transistor alone. Biasing circuitry generates an adaptive bias voltage for the second transistor to protect the first transistor and the second transistor from high voltage levels at the output of the LED driver. | 06-30-2011 |
| 20110157070 | SYSTEM AND METHOD FOR CONFIGURING CAPACITIVE SENSING SPEED - A system and method for configuring capacitive sensing speed are provided. In one example, a circuit includes first and second circuitry and control logic. The first circuitry controls a first current provided to a reference capacitor having a known capacitance. The second circuitry controls a second current to an external capacitor having an unknown capacitance. The control logic is configured to receive input defining a period of time at which to set the charge time of the reference capacitor, control the first circuitry to provide a minimum amount of the first current needed to charge the reference capacitor within the defined period of time, and control the second circuitry to provide an amount of the second current needed to normalize the charge time of the external capacitor with the charge time of the reference capacitor. | 06-30-2011 |
| 20110157068 | TOUCH SCREEN POWER-SAVING SCREEN SCANNING ALGORITHM - A method for detecting touch locations on a capacitive array includes the steps of scanning for at least one touch location on an entire capacitive array using a first sensing circuitry and detecting the at least one touch location with the first sensing circuitry. A smaller portion of the capacitive array is determined responsive to the detection of the at least one touch location. The at least one touch location is scanned only within smaller portion of the capacitive array using a second sensing circuitry. The at least one touch location is detected with the second sensing circuitry and output for use. | 06-30-2011 |
| 20110156839 | CAPACITIVE SENSOR WITH VARIABLE CORNER FREQUENCY FILTER - A system and method for configuring a variable filter in a capacitive sensing circuit are provided. In one example, the circuit includes first and second circuitry and control logic. The first circuitry is configured to provide a variable resistance path that is coupled to an external capacitor that is to be sensed by the capacitive sensing circuit. The second circuitry controls actuation of the first circuitry and is responsive to a voltage change that occurs when a charge level of the external capacitor is altered. The second circuitry actuates the first circuitry when the voltage change causes a voltage supplied to the second circuitry to pass a predefined threshold. The control logic receives input identifying a desired corner frequency, determines a resistance setting for the first circuitry corresponding to the corner frequency, and applies the resistance setting to the first circuitry to configure the first circuitry at the corner frequency. | 06-30-2011 |
| 20110156802 | CHARGE PUMP WITH LOW POWER, HIGH VOLTAGE PROTECTION CIRCUITRY - A charge pump circuitry for generating a charging voltage for programming a one time programmable (OTP) memory includes a charge pump sub-circuit for generating the charging voltage in a second voltage range when the charging voltage exceeds a threshold level. A precharge circuit generates the charging voltage in a first voltage range when the charging voltage is below the threshold level. A voltage measurement circuit determines the charging voltage. A first control circuit enables the precharge circuit and disables the charge pump sub-circuit in a first mode of operation responsive to the charging voltage being determined to be below the threshold level and disables the precharge circuit and enables the charge pump sub-circuit in a second mode of operation responsive to the charging voltage being determined to exceed the threshold level. A second control circuit provides an indication that the charging voltage has reached a charging level for programming the OTP memory responsive to the determined charging voltage. | 06-30-2011 |
| 20110151819 | Radio Frequency (RF) Receiver with Dynamic Frequency Planning and Method Therefor - A radio frequency (RF) receiver comprises an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal. The digital processor controls a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the digital processor on the analog receiver. | 06-23-2011 |
| 20110151816 | Radio Frequency (RF) Receiver with Frequency Planning and Method Therefor - A radio frequency (RF) receiver with frequency planning includes an analog receiver, a digital processor, and a clock synthesizer. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, a signal output for providing an IF output signal, and a control output for providing a clock control signal. The clock synthesizer has an input for receiving the clock control signal, and an output for providing the clock signal, and is controllable to adjust a frequency of the clock signal to a selected one of a predetermined number of frequencies within a predetermined frequency range in response to the clock control signal. | 06-23-2011 |
| 20110150135 | ELECTROSTATIC DISCHARGE CIRCUITRY WITH DAMPING RESISTOR - An apparatus formed on a substrate includes a pad, electrostatic discharge circuitry, and a metal damping resistor connected between the pad and the electrostatic discharge circuitry. | 06-23-2011 |
| 20110115556 | CIRCUIT DEVICES AND METHODS OF PROVIDING A REGULATED POWER SUPPLY - In an embodiment, a circuit includes a regulated power supply terminal, a processing circuit coupled to the regulated power supply terminal, and a low frequency responsive circuit having a first transistor adapted to be coupled to a power source and having first circuitry configured to control current flow from the power source through the first transistor to supply a low frequency current to the regulated power supply terminal. The circuit device further includes a high frequency responsive circuit having a second transistor coupled to the regulated power supply terminal and having second circuitry configured to control the second transistor to selectively modulate high frequency current components at the regulated power supply terminal to reduce voltage variations on the regulated power supply. | 05-19-2011 |
| 20110115537 | CIRCUIT DEVICES AND METHODS FOR RE-CLOCKING AN INPUT SIGNAL - Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate. | 05-19-2011 |
| 20110102047 | Radio Frequency (RF) Power Detector Suitable for Use in Automatic Gain Control (AGC) - In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators. | 05-05-2011 |
| 20110076979 | SHIELDED DIFFERENTIAL INDUCTOR - A shielded differential inductor forms a high quality factor (high-Q) inductor that is configured to attenuate frequency spurs and/or noise from magnetic coupling generated by electrical structures on or off of a substrate as well as interference received by other components from magnetic coupling generated by the inductor. The shielded differential inductor includes a differential inductor and a shield that substantially isolates the electrical field between the inductor and the substrate to reduce substrate current loss. The shield includes sets of finger structures that extend beyond the width of the inductor and a hub and spoke configuration of ground conductors that connect the sets of finger structures to ground. | 03-31-2011 |
| 20110076977 | Signal Processor Suitable for Low Intermediate Frequency (LIF) or Zero Intermediate Frequency (ZIF) Operation - A signal processor for a radio frequency (RF) receiver includes a plurality of distributed signal processing elements, in which a first one receives an input signal and a last one provides an output signal, and a plurality of gain elements interspersed between pairs of said plurality of distributed signal processing elements. The signal processor also includes a like plurality of peak detectors coupled to outputs of corresponding ones of said plurality of gain elements, and an automatic gain controller having inputs coupled to outputs of each of the peak detectors, and outputs coupled to each of the plurality of gain elements. The automatic gain controller independently controls each of the plurality of gain elements to form a like plurality of independent automatic gain control (AGC) loops. | 03-31-2011 |
| 20110075775 | ANALOG TO DIGITAL CONVERTER WITH LOW OUT OF BAND PEAKING - An analog to digital converter includes a delta sigma modulator with a modified distributed feed-forward (DFF) topology. The modulator includes low pass filter circuitry that provides a first path to a first integrator and a second, feed-forward path to a second integrator that significantly reduce the out of band signal transfer function (STF) peaking of the modulator. | 03-31-2011 |
| 20110075720 | Radio Receiver Having a Multipath Equalizer - A radio receiver has a multipath equalizer that includes a filter and a coefficient estimator. The filter provides a reconstructed signal by applying a transfer function including a reflection coefficient and a delay coefficient to a multipath radio signal. The coefficient estimator adapts the reflection coefficient and the delay coefficient in response to a deviation in magnitude of the reconstructed signal from a normalized value. In one form, the coefficient estimator adapts at least one of the reflection coefficient and the delay coefficient by estimating a partial derivative using a predetermined number of terms. In another form, the coefficient estimator acquires an initial value of the delay coefficient by determining a global minimum as a lowest one of a plurality of local minimums, each determined using a plurality of values of the delay coefficient, and selecting the initial value of the delay coefficient as its value at the global minimum. | 03-31-2011 |
| 20110075719 | Radio Receiver Having a Multipath Equalizer - A radio receiver has a multipath equalizer that includes a filter and a coefficient estimator. The filter provides a reconstructed signal by applying a transfer function including a reflection coefficient and a delay coefficient to a multipath radio signal. The coefficient estimator adapts the reflection coefficient and the delay coefficient in response to a deviation in magnitude of the reconstructed signal from a normalized value. In one form, the filter evaluates the transfer function by truncating it to eight terms. In another form, the filter includes a delay line having delay elements for storing samples of the multipath radio signal received both before and after a current sample. In yet another form, the multipath equalizer further includes a normalizer that receives the multipath radio signal and provides a normalized multipath radio signal having a normalized magnitude to an input of the filter. | 03-31-2011 |
| 20110073996 | MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INTO A SINGLE DIE - A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die. | 03-31-2011 |
| 20110065399 | SYSTEM AND METHOD FOR DYNAMICALLY REGULATING VOLTAGE TO MINIMIZE POWER CONSUMPTION - A system includes a voltage regulator connected to a voltage source for providing a regulated voltage at a first level in a first mode of operation and at least one second level in a second mode of operation. The second voltage level is higher than the first voltage level. A control processor provides control signals to select between the first and the second modes of operation. A component associated with the voltage regulator. The component is disabled in the first mode of operation and enabled in the second mode of operation. The control processor generates control signals to configure the voltage regulator to generate the voltage at the first level in the first mode of operation when the component is disabled and to configure the voltage regulator to generate the voltage at the at least one second level in the second mode of operation when the component is enabled. | 03-17-2011 |
| 20110062785 | SYSTEM AND METHOD FOR SUPPORTING HIGH BURST CURRENT IN A CURRENT LIMITED SYSTEM - A current limited system for providing a burst current capability comprises a variable load having a first mode of operation requiring a first current level and a burst current mode of operation requiring a second current level. The second current level is greater than the first current level. A control processor provides control signals for the current limited system. A voltage source is connected to the variable load to provide a source current. The source current provides the variable load the first current level in the first mode of operation. A burst mode circuit provides the second current level to the variable load in the burst current mode of operation, responsive to the control signals from the control processor and the voltage source. | 03-17-2011 |
| 20110019728 | SYSTEM AND METHOD OF ALTERING A PWM CARRIER POWER SPECTRUM - In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal. | 01-27-2011 |
| 20110019205 | Apparatus and method for implementing a touchless slider - A method for gesture recognition in an optical system using a touchless slider is shown. The touchless slider has first and second reference points positioned along an axis in an optical system. The method includes obtaining a plurality of first and second reflectance values by measuring an amplitude of light reflected from an object relative to the first and second reference points, respectively, wherein each first and second reflectance value corresponds to a different point in time. The plurality of first and second reflectance values are compared to identify a plurality of ratio values between the first and second reflectance values, wherein each of the plurality of ratio values corresponds to one of the points in time. At least one of a position and a direction of movement of the object relative to the first and second reference points is determined based on the identified plurality of ratio values. | 01-27-2011 |
| 20100328542 | Low-Noise Amplifier Suitable for Use in a Television Receiver - A low-noise amplifier includes a first resistor that receives a first signal of a differential input signal, and a second resistor that receives a second signal of the differential input signal. The amplifier includes a first transconductance device coupled to the first resistor that provides a first signal of a differential output signal, and a second transconductance device coupled to the second resistor, that provides a second signal of the differential output signal. The receiver also includes a first capacitor coupled between the first resistor input and a control electrode on the second transconductance device, and a second capacitor coupled between the second resistor input and a control electrode on the first transconductance device. The low-noise amplifier can include additional gain stages. | 12-30-2010 |
| 20100328295 | SYSTEM AND METHOD FOR LCD LOOP CONTROL - An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator. | 12-30-2010 |
| 20100328286 | LCD CONTROLLER WITH OSCILLATOR PREBIAS CONTROL - An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage. | 12-30-2010 |
| 20100328199 | LCD CONTROLLER WITH BYPASS MODE - An LCD controller includes a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal. An oscillator generates the clock signal responsive to at least one bias voltage. The oscillator has a high power mode of operation and a low power mode of operation. Bias circuitry for applies the at least one bias voltage to the oscillator. The at least one bias voltage is applied to the oscillator from an external source in the high power mode of operation and the at least one bias voltage is applied to the oscillator from a source within the oscillator in the low power mode of operation. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage. | 12-30-2010 |
| 20100327930 | SCHMITT TRIGGER WITH GATED TRANSITION LEVEL CONTROL - A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level. | 12-30-2010 |
| 20100321129 | CIRCUIT DEVICE AND METHOD OF COUPLING TO AN ANTENNA - In an embodiment, a circuit device for coupling to an antenna includes a first impedance matching circuit configured to couple to the antenna and a second impedance matching circuit configured to couple to the antenna. The circuit device further includes a power amplifier coupled to the first impedance matching circuit and includes a low-noise amplifier coupled to the second impedance matching circuit. Additionally, the circuit device includes a selectable impedance adjustment circuit coupled between the low-noise amplifier and the second impedance matching circuit, which selectable impedance adjustment circuit is configured to selectively adjust an impedance associated with the low-noise amplifier when the power amplifier is transmitting a signal through the antenna. | 12-23-2010 |
| 20100314939 | POWER SOURCING EQUIPMENT DEVICE INCLUDING A SERIAL INTERFACE - In a particular embodiment, a circuit device is disclosed that includes a power sourcing equipment (PSE) circuit having a plurality of high-voltage line circuits adapted to communicate with a respective plurality of powered devices via network cables. The PSE circuit includes a serial interface circuit and includes a common controller coupled to the serial interface circuit and to the plurality of high-voltage line circuits. The circuit device also includes a low-voltage circuit having a programmable controller adapted to transmit control signals to the common controller via the serial interface circuit to control operation of the plurality of high-voltage line circuits. | 12-16-2010 |
| 20100296671 | System and Method of Changing a PWM Power Spectrum - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 11-25-2010 |
| 20100293399 | SYSTEM AND METHOD OF CLASSIFICATION IN POWER OVER ETHERNET SYSTEMS - A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number. | 11-18-2010 |
| 20100283760 | METHOD AND APPARATUS FOR SCANNING A TOUCHSCREEN WITH MULTI-TOUCH DETECTION USING MASTER/SLAVE DEVICES - A touch panel scan system is disclosed for detecting a change in mutual capacitance on the surface of a touch panel. A first touch detect device is provided having a transmitter for transmitting a transmit signal to a select one of a plurality of first lines on a first edge of a touch panel to facilitate a single line scan operation. A second touch detect device is interfaced with a select one or ones of second lines on a second edge of the touch panel having a receiver for receiving therefrom and processing thereof transmit signals coupled thereto from the select one or ones of the first lines to detect changes in a mutual capacitance associated with the select one or ones of the second lines and the first line. At least one of the first or second touch detect devices functions as a master and the other functions as a slave, with the master coupled to the slave and generating a SYNC signal to initiate a single scan operation of a select one of the first lines. | 11-11-2010 |
| 20100271742 | Electrical Over-Stress Detection Circuit - In an embodiment, an electrical over-stress (EOS) circuit includes a detection circuit coupled between first and second supply terminals and configured to detect a perturbation in a supply voltage potential between the first and second supply terminals or between a supply voltage potential and a pad voltage of a bond pad. The EOS circuit further includes an alert generation circuit configured to store data indicating an EOS event in response to detecting the perturbation. | 10-28-2010 |
| 20100267350 | TUNING CIRCUITRY IN A COMMUNICATIONS DEVICE - A communications device is provided. The communications device includes a first antenna port coupled to a signal line, transmitter circuitry coupled to the signal line and configured to broadcast a radio frequency (RF) output signal across the first antenna port, tuning circuitry coupled to the signal line, and a controller configured to adjust a tuning of the tuning circuitry. The first antenna port, the transmitter circuitry, the tuning circuitry, and the controller are at least partially integrated on the same integrated circuit. | 10-21-2010 |
| 20100250875 | EEPROM EMULATION USING FLASH MEMORY - A device is provided wherein a traditional EEPROM device is emulated by using two or more pages of block-erasable memory and mapping each traditional EEPROM write instruction to an incremented active data sector in a first page of the block-erasable memory while a second page of the block-erasable memory is being partially or fully erased. Then, when the first page of block-erasable memory has had its plurality of data sectors written, changing the active page to the second block-erasable memory and mapping traditional EEPROM writes to incremented data sectors therein while the previously written block-erasable memory is being partially or fully erased. | 09-30-2010 |
| 20100246995 | Method for Performing Dual Mode Image Rejection Calibration in a Receiver - A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired using a first known signal associated with a first signal band during a startup mode. The first image correction factor has a plurality of bits including most significant bits (MSBs) and least significant bits (LSBs). The LSBs of the first image correction factor are adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode. | 09-30-2010 |
| 20100246649 | Circuit device including peak and average detectors - In a particular embodiment, a circuit device includes a peak detector to receive a signal and to generate peak output data related to the received signal and an average detector to generate average output data related to the received signal. The circuit device further includes a logic circuit to generate a data output related to the received signal based on the generated peak output data and the generated average output data. | 09-30-2010 |
| 20100238036 | Use of optical reflectance proximity detector for nuisance mitigation in smoke alarms - A smoke alarm comprises smoke detection circuitry for detecting smoke and generating a detection signal responsive thereto. Proximity detection circuitry generates a proximity detection signal responsive to detection of an object within in a selected distance of the smoke alarm. Alarm generation circuitry generates an audible alarm responsive to the detection signal. The audible alarm may be deactivated for a predetermined period of time responsive to at least one proximity detection signal. | 09-23-2010 |
| 20100225638 | SYSTEM AND METHOD FOR PROVIDING BIAS VOLTAGES TO PAD LOGIC OF AN LCD CONTROLLER - An LCD controller includes at least one I/O pad for providing an LCD drive voltage in an LCD mode of operation. I/O pad logic drives the at least one I/O pad responsive to a provided bias voltage. Voltage selection logic selects a higher voltage between an LCD drive voltage and an externally provided system voltage as a first voltage. Bias voltage logic selects one of the system voltage or the first voltage as the bias voltage for the I/O pad logic. The system voltage is selected as the bias voltage for the I/O pad logic in a non-LCD mode of operation for the I/O pad and the first voltage is selected for the bias voltage for the I/O pad logic in the LCD mode of operation for the I/O pad. | 09-09-2010 |
| 20100207699 | System and Method of Shaping a Power Spectrum in PWM Amplifiers - In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape. | 08-19-2010 |
| 20100201382 | SYSTEM AND METHOD FOR DETERMINING CAPACITANCE VALUE - A circuit for determining a value of a variable capacitor comprises first circuitry for generating a first indication when a variable voltage across the variable capacitor exceeds a threshold voltage. Second circuitry generates a second indication when a reference voltage across a reference capacitor exceeds the threshold voltage. Control logic responsive to the first and second indications generate a control signal indicating whether the first indication or the second indication occurs first. A successive approximation engine generates an N-bit control value responsive to the control signal. A variable current source is responsive to the N-bit control value for generating a variable current to the first circuitry. A reference current source generates a reference current to the second circuitry. | 08-12-2010 |
| 20100171540 | System and Method of Changing a PWM Power Spectrum - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 07-08-2010 |
| 20100156839 | METHOD AND APPARATUS FOR IMPLEMENTING A CAPACITIVE TOUCH SLIDER - A capacitive touch slider array comprises a first conductive trace associated with a first sensing node. The first conductive trace includes a first conductive line and a plurality of first conductive fingers extending from the first conductive line. The plurality of first conductive fingers have lengths that increase from a first end of the capacitive touch slider array to a second end of the capacitive touch slider array. A second conductive trace associated with a second sensing node includes a second conductive line and a plurality of second conductive fingers extending from the second conductive line. The plurality of second conductive fingers have lengths that increase from the second end of the capacitive touch slider array to the first end of the capacitive touch slider array. | 06-24-2010 |
| 20100156685 | SAR ANALOG-TO-DIGITAL CONVERTER HAVING VARIABLE CURRENTS FOR LOW POWER MODE OF OPERATION - A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC. | 06-24-2010 |
| 20100156684 | SAR ANALOG-TO-DIGITAL CONVERTER HAVING DIFFERING BIT MODES OF OPERATION - A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC. | 06-24-2010 |
| 20100156493 | Circuit device to produce an output signal including dither - In a particular embodiment, a circuit device includes a count zero circuit having a first counter to receive a clock signal and to produce a count zero signal based on the clock signal and having a second counter to generate a reset control signal to control a reset of the count zero circuit. The circuit device further includes a turnoff circuit to receive the clock signal and to produce a turn off signal based on the clock signal. Further, the circuit device includes a pulse width modulated (PWM) latch circuit adapted to produce a gate drive signal based on the count zero signal and the turn off signal, where timing of an edge of the gate drive signal varies based on the reset control signal. | 06-24-2010 |
| 20100156175 | DC/DC BOOST CONVERTER WITH BYPASS FEATURE - An integrated circuit package includes a DC/DC boost converter for providing an output voltage at a program level to associated components of the integrated circuit package. The DC/DC boost converter includes a first mode of operation wherein the DC/DC boost converter is enabled responsive to an input battery voltage falling below a programmed level of the output voltage. The DC/DC boost converter also includes a second mode of operation wherein the DC/DC boost converter is disabled responsive to the input battery voltage being above the programmed level of the output voltage. | 06-24-2010 |
| 20100150338 | Circuit device with serial bus isolation - In a particular embodiment, a circuit device includes a first circuit having a first plurality of serial terminals including a first data receive terminal and a first data transmit terminal. The first plurality of serial terminals is communicatively coupled to a particular circuit via isolation circuitry to communicate first serial data. The circuit device further includes a second circuit having a second plurality of serial terminals including a second data receive terminal coupled to the first data transmit terminal and including a second data transmit terminal coupled to the first data receive terminal to communicate second serial data to the particular circuit via the first data receive and transmit terminals. | 06-17-2010 |
| 20100130158 | Low-Cost Receiver Using Tracking Filter - A receiver ( | 05-27-2010 |
| 20100130155 | Low-Cost Receiver Using Tracking Bandpass Filter and Lowpass Filter - A receiver ( | 05-27-2010 |
| 20100130153 | Low-Cost Receiver Using Automatic Gain Control - A receiver ( | 05-27-2010 |
| 20100125776 | Multi-syndrome error correction circuit - In a particular embodiment, a forward error correction (FEC) decoder is disclosed that includes an input responsive to a communication channel to receive sampled bits from a continuous bit stream. The circuit device further includes a logic circuit to alternately provide sets of the received sampled bits from the continuous bit stream to one of a first syndrome generator and a second syndrome generator to correct errors in the sets of sampled bits to produce a decoded output related to the continuous bit stream. | 05-20-2010 |
| 20100118918 | SPREAD SPECTRUM ISOLATOR - An apparatus comprising a functional circuitry on a first die. Said function circuitry configured to drive an RF voltage isolation link with an RF signal responsive to receipt of a logic signal at a first logic state. Control circuitry modifies the frequency of the RF signal to spread harmonics to other than a fundamental frequency. | 05-13-2010 |
| 20100080336 | CIRCUIT DEVICE TO GENERATE A HIGH PRECISION CONTROL SIGNAL - In an embodiment, a circuit device includes a first counter responsive to a clock signal and to a first control word having a first precision. The counter produces a first control signal related to the first control word at a first output. The circuit device farther includes a second counter responsive to the clock signal and to a second control word having the first precision. The second counter produces a second control signal related to the second control word at a second output. The circuit device also includes a filtering circuit responsive to the first output and the second output to receive the first and second control words. The filtering circuit is adapted to produce an output control signal related to the first and second control words, where the output control signal has a second precision that is greater than the first precision. | 04-01-2010 |
| 20100080326 | RDS/RBDS DECODER WITH RELIABLE VALUES - A method is provided that contemplates including filtered decode values in an RDS/RBDS output signal. The filtered decode values are generated from reliable values. The reliable values are generated from corresponding received values from each of at least two groups of RDS/RBDS data in an RDS/RBDS input signal. The method also comprises preventing an error correction code (ECC) unit from modifying the filtered decode values in the RDS/RBDS output signal. | 04-01-2010 |
| 20100079439 | METHOD AND APPARATUS TO SUPPORT VARIOUS SPEEDS OF LCD DRIVER - Charge pump circuitry comprises a voltage for generating a first regulated voltage. A low drop out regulator generates a second regulated voltage responsive to the first regulated voltage. A charge pump voltage generation circuit generates a voltage. First and second resistor strings are responsive to the generated voltage. The first resistor string provides a first plurality of bias voltages to an LCD responsive to the voltage in a first mode of operation and the second resistor string provides faster charging and discharging of the connected LCD elements responsive to a second mode of operation. | 04-01-2010 |
| 20100078992 | CIRCUIT DEVICE AND METHOD OF CURRENT LIMIT-BASED DISCONNECT DETECTION - In a particular embodiment, a power sourcing equipment (PSE) device includes at least one network port adapted to couple to a powered device to provide power and optionally data to the powered device via a network cable. The PSE device further includes a current limiter circuit coupled to the at least one network port and having an adjustable threshold. The PSE device also includes a logic circuit coupled to the current limiter circuit and adapted to reduce the adjustable threshold of the current limiter circuit to have a threshold level that is below a nominal operating current level. After a period of time has elapsed during which the current limiter circuit is not activated, the logic circuit is adapted to determine that the powered device is disconnected from the at least one network port. | 04-01-2010 |
| 20100077245 | SYSTEM AND METHOD OF CLASSIFICATION IN POWER OVER ETHERNET SYSTEMS - A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number. | 03-25-2010 |
| 20100066169 | CIRCUIT DEVICE INCLUDING MULTIPLE PARAMETERIZED POWER REGULATORS - In a particular embodiment, a circuit device includes a plurality of programmable voltage regulator circuits adapted to produce one or more unique power supplies. Each programmable voltage regulator circuit includes a power supply output terminal and a base regulator circuit module that has multiple configurable parameters to support a plurality of regulator configurations. The base regulator circuit module includes a plurality of leads. Each programmable voltage regulator circuit further includes selected circuitry coupled to the plurality of leads and to the power supply output terminal. The selected circuitry is adapted to cooperate with the base regulator circuit module to provide a selected type of regulator circuit and to apply a power supply to the power supply output terminal. | 03-18-2010 |
| 20100052826 | ISOLATOR WITH COMPLEMENTARY CONFIGURABLE MEMORY - An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary. | 03-04-2010 |
| 20100007334 | POWER SOURCING EQUIPMENT DEVICE AND METHOD OF PROVIDING A POWER SUPPLY TO A POWERED DEVICE - In a particular embodiment, a power sourcing equipment (PSE) device includes a plurality of network ports adapted to communicate data and to selectively provide power to one or more powered devices via a plurality of channels. The PSE device further includes a plurality of sense elements, where each sense element is coupled to a respective network port of the plurality of network ports. The PSE also includes a power sensing circuit having an analog-to-digital converter (ADC) adapted to be selectively coupled to a selected network port of the plurality of network ports. The power sensing circuit selectively measures at least one electrical parameter associated with the selected network port. | 01-14-2010 |
| 20090327558 | SYSTEM AND METHOD OF PROVIDING ELECTRICAL ISOLATION - In a particular embodiment, a power sourcing equipment (PSE) device is disclosed that includes a plurality of network input/output (I/O) interfaces adapted to physically and electrically connect to a respective plurality of cables. The PSE device further includes a plurality of driver circuits. Each driver circuit of the plurality of driver circuits is coupled to a respective network I/O interface of the plurality of network I/O interfaces to send and receive data via a respective cable of the respective plurality of cables. Further, the PSE device includes a shared isolation barrier to electrically isolate control circuitry from the plurality of driver circuits. | 12-31-2009 |
| 20090323717 | SYSTEM AND METHOD OF PROVIDING ELECTRICAL ISOLATION - In a particular embodiment, a system includes an input/output (I/O) interface adapted to couple to a network cable to receive power and data and includes a physical transport layer (PHY) circuit including multiple channels coupled to the I/O interface. The PHY circuit is adapted to send data to and receive data from a network device via the multiple channels. The system further includes a multiplexer circuit coupled to the PHY circuit to multiplex data from the multiple channels into a multiplexed data stream and includes an isolation barrier circuit coupled to the multiplexer circuit and to a particular circuit. The isolation barrier is adapted to electrically isolate a particular circuit from the multiplexer circuit, the PHY circuit, and the I/O interface. | 12-31-2009 |
| 20090322725 | LCD CONTROLLER WITH LOW POWER MODE - An LCD controller comprises a host interface control block for providing a connection between the LCD controller and a master controller. The master controller initiates a low power mode of operation for the LCD controller through the host interface control block. At least a portion of a plurality of input/output pins provide a connection to at least one LCD display for the LCD controller. An LCD static display controller within the LCD controller drives the at least one LCD display in a static display mode responsive to entry of the LCD controller into the low power mode of operation. A real time clock provides a clock signal to the LCD static display controller in the low power mode of operation. Power circuitry within the LCD controller selectively disables a regulated voltage provided to circuitry in the LCD controller that is not required to operate the LCD static display controller and the real time clock circuit in the low power mode of operation. | 12-31-2009 |
| 20090322711 | LCD CONTROLLER CHIP - An integrated circuit comprises a host interface control block for providing a connection between the integrated circuit and a master controller device. The integrated circuit further includes a plurality of I/O pins. A capacitive touch sense circuitry enables detection of actuation of at least one capacitor switch of a capacitive sensor array connected to at least a portion of the plurality of I/O pins. An LCD controller drives at least one LCD connected to at least a portion of the plurality of I/O pins. The integrated circuit, responsive to signals received from the master controller device over the host interface control block, may be configured to monitor outputs from the capacitive sensor array in a first mode of operation. In a second mode of operation, the capacitive sensor array may be configured to drive at least one LCD. Finally, in a third mode of operation, the integrated circuit may be configured to both monitor outputs of the capacitive sensor array and drive the at least one LCD. | 12-31-2009 |
| 20090322410 | SYSTEM AND METHOD FOR MONITORING A CAPACITIVE SENSOR ARRAY - A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes. | 12-31-2009 |
| 20090319814 | MEMORY POWER CONTROLLER - A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock. | 12-24-2009 |
| 20090309654 | SYSTEM AND METHOD OF ALTERING A PWM CARRIER POWER SPECTRUM - In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal. | 12-17-2009 |
| 20090273238 | POWER SOURCING EQUIPMENT DEVICE INCLUDING A SERIAL INTERFACE - In a particular embodiment, a circuit device is disclosed that includes a power sourcing equipment (PSE) circuit having a plurality of high-voltage line circuits adapted to communicate with a respective plurality of powered devices via network cables. The PSE circuit includes a serial interface circuit and includes a common controller coupled to the serial interface circuit and to the plurality of high-voltage line circuits. The circuit device also includes a low-voltage circuit having a programmable controller adapted to transmit control signals to the common controller via the serial interface circuit to control operation of the plurality of high-voltage line circuits. | 11-05-2009 |
| 20090267224 | CIRCUIT DEVICE INCLUDING ROTATED STACKED DIE - In a particular embodiment, a circuit device includes a first die coupled to a circuit substrate and having a substantially planar surface. The first die includes electrical contacts distributed on the substantially planar surface adjacent to at least three edges of the first die. The circuit device further includes a second die attached to the substantially planar surface of the first die. The second die is rotated by an offset angle about an axis relative to the first die. The offset angle is selected to allow horizontal and vertical access to the electrical contacts. | 10-29-2009 |
| 20090248930 | USB TRANSCEIVER CIRCUITRY INCLUDING 5 VOLT TOLERANCE PROTECTION - An integrated circuit includes USB communication circuitry for communicating via a USB interface. The USB transceiver circuitry transmits data to and from the integrated circuit over the USB interface. The USB transceiver circuitry further provides protection to internal circuitry of the integrated circuit from a 5 volt short circuit on the USB interface. | 10-01-2009 |
| 20090243903 | SYSTEM AND METHOD OF ALTERING A PWM CARRIER POWER SPECTRUM - In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal. | 10-01-2009 |
| 20090243745 | SYSTEM AND METHOD OF SHAPING A POWER SPECTRUM IN PWM AMPLIFIERS - In a particular embodiment, a circuit device is disclosed that includes a data generator adapted to output a random pulse sequence having a particular spectral shape. The circuit device further includes a pulse edge control circuit to selectively apply a carrier suppression operation to at least one pulse-width modulated (PWM) signal in response to the random pulse sequence to produce at least one modulated PWM output signal. The spectral energy associated with a PWM carrier of the modulated PWM output signal at a carrier frequency and associated harmonics is changed such that the modulated PWM output signal has a spectral shape defined by the particular spectral shape. | 10-01-2009 |
| 20090243744 | SYSTEM AND METHOD OF CHANGING A PWM POWER SPECTRUM - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 10-01-2009 |
| 20090243688 | SYSTEM AND METHOD OF CHANGING A PWM POWER SPECTRUM - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 10-01-2009 |
| 20090243570 | 5 VOLT TOLERANT VOLTAGE REGULATOR - A voltage regulator circuit comprises an error amplifier for generating an error signal responsive to a reference voltage in a feedback signal. A feedback circuit provides the feedback voltage signal to the error amplifier and a driver circuit provides regulated output voltage responsive to the input voltage in the error signal. Short circuit protection circuitry selectively protects transistors within the error amplifier, the feedback amplifier and the driver circuit responsive to a short circuit protection enablement signal. | 10-01-2009 |
| 20090243028 | CAPACITIVE ISOLATION CIRCUITRY WITH IMPROVED COMMON MODE DETECTOR - An integrated circuit having voltage isolation capabilities comprising a first galvanically isolated area of the integrated circuit containing a first group of functional circuitry for processing a data stream. The first group of functional circuitry located in a substrate of the integrated circuit. Capacitive isolation circuitry located in conductive layers of the integrated circuit provides a high voltage isolation link between the first group of functional circuitry and a second group of functional circuitry connected to the integrated circuit through the capacitive isolation circuitry. The capacitive isolation circuitry includes a differential transmitter for transmitting data in a differential signal to the second group of functional circuitry via the capacitive isolation circuitry. A differential receiver receives data within the differential signal from the second group of functional circuitry via the capacitive isolation circuitry. A detector circuit within the differential receiver detects the received data. The detector circuit monitors the differential signal and generates a first logical output when a voltage generated responsive to the differential signal exceeds a programmable voltage threshold level and generates a second logical output when the voltage generated responsive to the differential signal falls below the programmable voltage threshold level. | 10-01-2009 |
| 20090213914 | CAPACITIVE ISOLATION CIRCUITRY - An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link. A differential transmitter on each of the plurality of communications channels transmits the data on the first link at a selected one of a first phase and a second phase and for transmitting the data on the second link at the selected one of the first phase and the second phase. The second phase is 180 degrees out of phase with the first phase. Each of the differential transmitters controls the selection of the first phase and the second phase on each of the first link and the second link such that only the first phase or the second phase is cross coupled onto a selected communications channel from adjacent communications channels. | 08-27-2009 |
| 20090187773 | MCU WITH POWER SAVING MODE - A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level. | 07-23-2009 |
| 20090172656 | CIRCUIT DEVICE AND METHOD OF PROVIDING A PROGRAMMABLE POWER SUPPLY - In a particular embodiment, a circuit device includes a plurality of network ports, power regulator circuitry coupled to the plurality of network ports, and a control input adapted to receive software updates. The circuit device further includes a memory adapted to store a plurality of instructions, including processor operating system instructions and an upgrade routine. The circuit device further includes a programmable processor that is coupled to the memory and to the control input. The programmable processor is adapted to receive software updates via the control input and to execute the upgrade routine to upgrade the processor operating system instructions to reprogram the programmable processor. Further, the programmable processor is adapted to control the power regulator circuitry to selectively provide a power supply to a network device via a selected network port of the plurality of network ports. | 07-02-2009 |
| 20090172242 | SYSTEM AND METHOD FOR CONNECTING A MASTER DEVICE WITH MULTIPLE GROUPINGS OF SLAVE DEVICES VIA A LINBUS NETWORK - A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware. | 07-02-2009 |
| 20090168939 | HARDWARE SYNCHRONIZER FOR 802.15.4 RADIO TO MINIMIZE PROCESSING POWER CONSUMPTION - A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred. The MCU in at least one mode of operation thereof is operable to initiate the operation of the hardware controller and then convert to a low power mode of operation to await notification. | 07-02-2009 |
| 20090168849 | METHOD AND APPARATUS FOR SYMBOL SYNCHRONIZATION FOR AN 802.15.4 RADIO PLATFORM - A single chip radio platform is disclosed for communicating with an RF channel. An RF front end is provided having a receive/transmit capability to receive an RF carrier modulated with digital data and convert the data to analog baseband data, and modulate an RF carrier with baseband data. A digital signal processor (DSP) engine is provided for interfacing with the RF front end to form in conjunction therewith the PHY layer, and interfacing with the MAC layer to demodulate the baseband data and in the transmit mode to generate the baseband data for modulation and transmission by the RF front end. A microcontroller unit (MCU) is provided for performing the functionality of the MAC, network and application layers and interfacing with the DSP. Clock circuitry is provided including a stable reference clock for generating a first fixed clock for providing MCU clocks for the operation of the MCU, and for providing a reference for a local oscillator at substantially the channel frequency for use by the RF front end and a DSP clock for use by the DSP, both the MCU clocks, the local oscillator and the DSP clock having the stability of the first fixed clock. Periodic power management circuitry is provided for controlling the operation of the radio platform to operate in a sleep. | 07-02-2009 |
| 20090168848 | SINGLE CHIP LOW POWER FULLY INTEGRATED 802.15.4 RADIO PLATFORM - A single chip radio platform is disclosed for communicating with an RE channel. An RF front end is provided having a receive/transmit capability to receive an RF carrier modulated with digital data and convert the data to analog baseband data, and modulate an RF carrier with baseband data. A digital signal processor (DSP) engine is provided for interfacing with the RF front end to form in conjunction therewith the PHY layer, and interfacing with the MAC layer to demodulate the baseband data and in the transmit mode to generate the baseband data for modulation and transmission by the RF front end. A microcontroller unit (MCU) is provided for performing the functionality of the MAC, network and application layers and interfacing with the DSP. Clock circuitry is provided including a stable reference clock for generating a first fixed clock for providing MCU clocks for the operation of the MCU, and for providing a reference for a local oscillator at substantially the channel frequency for use by the RF front end and a DSP clock for use by the DSP, both the MCU clocks, the local oscillator and the DSP clock having the stability of the first fixed clock. Periodic power management circuitry is provided for controlling the operation of the radio platform to operate in a sleep. | 07-02-2009 |
| 20090168462 | CIRCUIT DEVICE AND METHOD OF PROVIDING FEEDBACK ACROSS AN ISOLATION BARRIER - In an embodiment, a circuit device includes a network interface responsive to a powered network to receive a power supply and data and includes an electrical isolation barrier adapted to define a non-isolated power domain and an isolated power domain. The circuit device further includes a first control circuit associated with the non-isolated power domain. The first control circuit is coupled to a primary winding of a transformer to control current flow via the primary winding. The circuit device also includes a second control circuit associated with the isolated power domain. The second control circuit is coupled to a secondary winding of the transformer and is adapted to detect a power error associated with the secondary winding. The second control circuit transfers a command across the electrical isolation barrier to the first control circuit to adjust a current at the primary winding in response to detecting the power error. | 07-02-2009 |
| 20090168278 | CIRCUIT DEVICE AND METHOD OF SUPRESSING A POWER EVENT - A circuit device includes a diode bridge having a first power input and a second power input and having a first output terminal and a second output terminal. The diode bridge includes a plurality of diodes and a respective plurality of diode bypass elements associated with the plurality of diodes. The circuit device further includes a logic circuit to detect a power event at the first and second power inputs and to selectively activate one or more of the respective plurality of diode bypass elements in response to detecting the power event to limit a rectified power supply at the first and second output terminals. | 07-02-2009 |
| 20090166754 | CIRCUIT DEVICE AND METHOD OF FORMING A CIRCUIT DEVICE HAVING A REDUCED PEAK CURRENT DENSITY - In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a body terminal. The method further includes depositing a plurality of metal contacts along a width of a gate terminal of the FET device and forming a wire trace to contact each of the plurality of metal contacts to reduce a gate resistance along the width of the gate terminal. | 07-02-2009 |
| 20090089605 | POWER SUPPLY VOLTAGE MONITORS - The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. A power management unit controls power operations of the processing unit, the analog circuitry and the digital circuitry. Power monitoring circuitry provides power control signals to the power management unit. The power monitoring circuitry further includes a system voltage monitoring circuit for generating a system voltage control signal responsive to a system voltage level with respect to a predetermined level. The power monitoring circuitry also includes a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level. | 04-02-2009 |
| 20090089599 | POWER SUPPLY SYSTEM FOR LOW POWER MCU - A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors. | 04-02-2009 |
| 20090086517 | DC/DC BOOST CONVERTER WITH RESISTORLESS CURRENT SENSING - A DC to DC boost converter circuit receives a DC input voltage and converts it to a DC output voltage at a different voltage level than the DC input voltage. The DC to DC boost converter includes a switching power converter for receiving the input voltage on an input and converting the input voltage to an output as the DC output voltage in response to pulse control signals. A switching controller generates the pulse control signals during a switching cycle. Current sensing circuitry limits a current passing through the switching power converter. The current sensing circuitry generates an overload signal when the current exceeds a reference value. The current sensing circuitry sensing the current with a current sensing resistor having a size of at least approximately 500 ohms. | 04-02-2009 |
| 20090085685 | SYSTEM AND METHOD FOR CALIBRATING BIAS CURRENT FOR LOW POWER RTC OSCILLATOR - The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A real time clock circuit provides a system clock for the processing core. The real time clock further comprises an internal oscillator that generates the system clock for the integrated circuit package. The internal oscillator has a factory calibrated bias current. An internal oscillator control register controls the operation of the internal oscillator responsive to control bits of the programmable load capacitor array controlled by the processing core. | 04-02-2009 |
| 20090085684 | LOW POWER RTC OSCILLATOR - The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. An internal oscillator provides a system clock for the integrated circuit package. A programmable load capacitor array provides a programmable load to tune an oscillation frequency of the internal oscillator. An internal oscillator control register for controlling the operation of the programmable load capacitor array responsive to control bits of the programmable load capacitor array controlled by the processing core. | 04-02-2009 |
| 20090085651 | SYSTEM FOR ADJUSTING OUTPUT VOLTAGE OF BAND GAP VOLTAGE GENERATOR - An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current. | 04-02-2009 |
| 20090085619 | POWER SUPPLY VOLTAGE MONITORS - The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. Monitoring circuitry determines if a chip supply voltage level exceeds a threshold level necessary to maintain operation of the digital circuitry. | 04-02-2009 |
| 20090085610 | GENERAL PURPOSE COMPARATOR WITH MULTIPLEXER INPUTS - A circuitry comprises a comparator for comparing a signal received on a first input to a signal received on a second input. A control register associated with the first multiplexer stores control values enabling connection of one input of the first multiplexer to the output of the first multiplexer. | 04-02-2009 |
| 20090085535 | DC/DC BOOST CONVERTER WITH PULSE SKIPPING CIRCUITRY - A DC to DC boost converter circuit receives a DC input voltage and converts it to a DC output voltage at a different voltage level than the DC input voltage. The DC to DC boost converter includes a switching power converter for receiving the input voltage on an input and converting the input voltage to an output as the DC output voltage in response to pulse control signals. A switching controller generates the pulse control signals during a switching cycle. The switching controller further includes pulse skipping circuitry for generating a pulse width modulated signal to the switching power converter. A pulse width of the pulse width modulated signal is decreased responsive to a voltage level of an output voltage of the DC to DC boost converter being less than a control saw tooth waveform and the pulses width of the pulse width modulated signal is increased responsive to the voltage level of the output voltage of the DC to DC boost converter being greater than the control saw tooth waveform. | 04-02-2009 |
| 20090027243 | MCU WITH INTEGRATED VOLTAGE ISOLATOR TO PROVIDE A GALVANIC ISOLATION BETWEEN INPUT AND OUTPUT - An integrated circuit comprises a first microcontroller unit located on a first die. The first microcontroller unit includes a first processing core for providing a parallel stream of data. A second microcontroller unit is located on a second die and includes a second processing core for receiving the parallel stream of data. Voltage isolation circuitry transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream and provides galvanic isolation between the first microcontroller unit and the second microcontroller unit. | 01-29-2009 |
| 20090017773 | CAPACITIVE ISOLATOR - An integrated circuit provides high voltage isolation capabilities. The circuit includes a first area containing a first group of functional circuitry located in a substrate of the integrated circuit. This circuit also includes a second area containing a second group of functional circuitry also contained within the substrate of the integrated circuit. Capacitive isolation circuitry located in the conductive layers in the integrated circuit provide a high voltage isolation link between the first group of functional circuitry and the second group of functional circuitry. The capacitive isolation circuitry distributes a first portion of the high voltage isolation signal across the first group of capacitors in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation circuitry across the second group of capacitors in the capacitive isolation circuitry. | 01-15-2009 |
| 20090013199 | DIGITAL POWER SUPPLY CONTROLLER WITH INTEGRATED MICROCONTROLLER - A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine. | 01-08-2009 |
| 20090001956 | POWERED DEVICE INCLUDING A MULTI-USE DETECTION RESISTOR - In a particular embodiment, a method includes receiving a powered device (PD) detection signal at a PD from a powered network and applying the PD detection signal to an external resistor to provide a detection signature to the powered network. Further, the method includes receiving a PD classification mark signal at the PD, applying the received PD classification mark signal to the external resistor, and selectively activating a classification mark current path in parallel with the external resistor to produce a classification mark signature. | 01-01-2009 |
| 20080317106 | MCU WITH INTEGRATED VOLTAGE ISOLATOR AND INTEGRATED GALVANICALLY ISOLATED ASYNCHRONOUS SERIAL DATA LINK - An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units. The capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributes a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit. The capacitive isolation circuitry further transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency. | 12-25-2008 |
| 20080267301 | BIDIRECTIONAL MULTIPLEXED RF ISOLATOR - An integrated circuit single chip isolator provides bidirectional data transfer for a plurality of communications channels. A first and second dies are located on a first and second sides of a voltage isolation barrier in the chip and have a first and second plurality of digital data input/output pins associated therewith. First circuitry located on the first die on a first side of the voltage isolation barrier and third circuitry located on the second die on a second side of the voltage isolation barrier serializes a plurality of parallel digital data inputs from the associated plurality of digital data input/output pins onto a one link across the voltage isolation barrier and transmits synchronization clock signals associated with the plurality of digital data inputs over a another link across the voltage isolation barrier. Second circuitry located on the second die on a second side of the voltage isolation barrier and fourth circuitry located on the first die on a first side of the voltage isolation barrier de-serializes the first plurality of digital data inputs from the first link onto the second plurality of digital data input/output pins and receives the first synchronization clock signal associated with the plurality of digital data inputs on the second link. Switches associated with each of the plurality of input/output pins between transmit and receive circuitry. | 10-30-2008 |
| 20080260050 | ON CHIP TRANSFORMER ISOLATOR - An integrated circuit having voltage isolation capabilities includes a first area of the integrated circuit containing functional circuitry that is located in the substrate of the integrated circuit. A second area of the integrated circuit contains an integrated RF isolation circuitry for voltage isolating the functional circuitry. The RF isolation circuitry is located in the metal layers of the integrated circuit. | 10-23-2008 |
| 20080246526 | PROGRAMMABLE I/O CELL CAPABLE OF HOLDING ITS STATE IN POWER-DOWN MODE - The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell. The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state. | 10-09-2008 |
| 20080244151 | METHOD AND APPARATUS FOR EMULATING REWRITABLE MEMORY WITH NON-REWRITABLE MEMORY IN AN MCU - An integrated circuit having an embedded multiple time programmable memory includes a processing core for executing stored instructions with a data memory and a non volatile memory. The non-volatile memory block provides for storage of program instructions and includes a plurality of blocks of non-volatile memory, each of which can be written to once and read from many times and each having a size that is equal to or less than a program memory address space addressable by the processing core for output of data there from. It also includes a reserve storage location for storing a status word defining the one of the plurality of blocks addressable by the processing core, the status word operable to be changed in response to external signals when another of the plurality of blocks is to be selected, such that once another of the plurality of blocks is selected, the status word cannot indicate as addressable by the processing core a prior one of the plurality of blocks that was defined by the status word as being previously addressable by the processing core. | 10-02-2008 |
