| SigmaTel, Inc. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110213617 | AUDIO SOURCE SYSTEM AND METHOD - A system includes a computer having a device driver. The device driver includes a detection module to detect an audio input. The device driver includes a selection module to send the audio input to audio hardware after detection of the audio input. The device driver also includes an emulation module to send hardware emulation information to an operating system audio application to replace feedback data received at the device driver from the audio hardware and sent from the device driver to the operating system audio application. | 09-01-2011 |
| 20110194661 | DIGITAL AUDIO PROCESSING SYSTEM AND METHOD - A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic determines a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The prior nearest predetermined phase value corresponds to a prior sample of the phase component of the signal. The offset value is based on a detected error of the prior sample of the phase component of the signal. The digital audio processing system also includes an output to provide a second signal that indicates the symbol. | 08-11-2011 |
| 20110141791 | SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY - A device includes a one-time-programmable memory including multiple random accessible input/output pins. Each random accessible I/O pin corresponds to a unique memory address in the one-time-programmable memory. The device also includes a multiplexing circuit with multiple inputs. Each of the multiple inputs is coupled to one of the multiple random accessible I/O pins. An output of the multiplexing circuit has a bit width that is less than the number of the multiple random accessible I/O pins. | 06-16-2011 |
| 20110060783 | DECIMATION FILTER - A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module. | 03-10-2011 |
| 20110022649 | DIGITAL AUDIO PROCESSING SYSTEM AND METHOD - A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value. | 01-27-2011 |
| 20100272265 | SYSTEM AND METHOD TO CONTROL ONE TIME PROGRAMMABLE MEMORY - Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data. | 10-28-2010 |
| 20100079206 | Digital Adaptive Feedforward Harmonic Distortion Compensation for Digitally Controlled Power Stage - Systems and method to compress digital video based on human factors expressed as a desirability score are provided. A particular method includes passing a digital input signal through a pulse-width modulator and passing an output of the pulse-width modulator through a power switching device. An output of the power switching device has a plurality of pulses. The method includes receiving the output of the power switching device at a first input of a comparator and receiving a reference voltage at a second input of the comparator. The method includes determining a net signal based on an output of the comparator and determining a timing error signal based on the net signal and the digital input signal. The method also includes adjusting the digital input signal to compensate for harmonic distortion based at least in part on the timing error signal. | 04-01-2010 |
| 20090212739 | Charging A Secondary Battery - A method of charging a battery includes applying a charging current from a semiconductor device to the battery during a first battery charging time period. The method also includes measuring a charging voltage level at the battery during the first battery charging time period. During a non-charging voltage measurement time interval, the method includes temporarily stopping application of the charging current from the semiconductor device to the battery and measuring a non-charging voltage level at the battery while the charging current is not being applied to the battery. | 08-27-2009 |
| 20090015714 | System and method of demodulating audio signals - A system and method for demodulating signals are disclosed. In a particular embodiment, the method includes receiving a signal at an input and determining a first noise estimate of the signal. The method also includes providing a first output indicating a second noise estimate of the signal at a primary carrier frequency and providing a second output indicating a third noise estimate of the signal at a secondary carrier frequency. | 01-15-2009 |
| 20080233978 | Wireless handset and wireless headset with wireless transceiver - A wireless handset or wireless headset includes a Bluetooth transceiver that is coupleable to an external Bluetooth compatible device, that sends the first audio data to the external Bluetooth compatible device and that receives the second audio data from the external Bluetooth compatible device. The Bluetooth transceiver includes a first integrated circuit that includes a memory module that stores a plurality of operational instructions for implementing a plurality of protocol layers of a Bluetooth protocol, a processing module that executes the plurality of operational instructions, and a first interface module. A second integrated circuit includes a second interface module that couples data to and from the first interface module, an RF transceiver that modulates a first baseband signal to produce a transmitted RF signal, and that demodulates a received RF signal to produce a second baseband signal, and a baseband module that generates the first baseband signal based on data received from the first interface module via the second interface module, and that generates data based on the second baseband signal to send to the first interface module via the second interface module. | 09-25-2008 |
| 20080232151 | System and method to control one time programmable memory - Systems and methods to control one time programmable (OTP) memory are disclosed. A method may include determining a functionality for a hardware capability bus in an integrated circuit. The method may also include storing data in a first register of the integrated circuit based on the functionality. The method may also include disabling the functionality in the integrated circuit by setting at least one bit in a one time programmable memory bank in the integrated circuit based on the data. | 09-25-2008 |
| 20080201625 | ERROR CORRECTION SYSTEM AND METHOD - A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data. | 08-21-2008 |
