| SIERRA MONOLITHICS, INC. Patent applications |
| Patent application number | Title | Published |
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| 20110140260 | CHIP ASSEMBLY WITH CHIP-SCALE PACKAGING - A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism. | 06-16-2011 |
| 20110133783 | SIGNAL INTERPOLATION METHODS AND CIRCUITS - An interpolation circuit for comparing an input voltage signal with an interpolated reference signal derived from a first reference voltage signal and a second reference voltage signal may include a transconductive circuit configured to generate a first differential current signal proportional to a difference between the first reference voltage signal and the input voltage signal and a second differential current signal proportional to a difference between the second reference voltage signal and the input voltage signal, an intermediate circuit configured to generate a third differential current signal, and a transinductive circuit configured to generate an output voltage signal having a first polarity if a value of the input voltage signal is greater than a value of the interpolated reference signal and a second polarity if the value of the input signal is less than the value of the interpolated reference signal. | 06-09-2011 |
| 20100066578 | BANDPASS MULTI-BIT SIGMA-DELTA ANALOG TO DIGITAL CONVERSION - Examples of a system and method for sigma-delta analog-to-digital conversion of an electrical input signal are disclosed. A bandpass-filtered signal based on an electrical input signal and an analog feedback signal may be provided. A multi-bit digital representation of the bandpass-filtered signal may be provided. An analog representation of the multi-bit digital representation may be provided. A return-to-zero (RTZ) carving operation may be performed on the analog representation to obtain the analog feedback signal. | 03-18-2010 |
| 20100022208 | APPARATUS AND METHOD FOR CALIBRATION OF GAIN AND/OR PHASE IMBALANCE AND/OR DC OFFSET IN A COMMUNICATION SYSTEM - An example of a radio frequency (RF) transmitter system for communication may include a transmit pre-distortion module configured to provide a second transmit calibration signal during a transmit calibration mode based on a first transmit calibration signal and one or more transmit calibration adjustment signals. The one or more transmit calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. The system may include a transmit channel frequency converter coupled to the transmit pre-distortion module. The transmit channel frequency converter may be configured to provide a fourth transmit calibration signal during the transmit calibration mode based on a third transmit calibration signal and a transmit reference signal. | 01-28-2010 |
| 20100022200 | APPARATUS AND METHOD FOR CALIBRATION OF GAIN AND/OR PHASE IMBALANCE AND/OR DC OFFSET IN A COMMUNICATION SYSTEM - An example of a method for off-line calibration of a radio frequency (RF) communication system may include one or more of the following: enabling an off-line calibration mode for an RF communication system; generating an off-line calibration signal; applying to a frequency converter a first off-line calibration signal corresponding to the generated off-line calibration signal; translating the first off-line calibration signal into a second off-line calibration signal; evaluating one or more calibration adjustment signals associated with the calibration signal to reduce error in the communication system, wherein the one or more calibration adjustment signals may include an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances; storing one or more calibration adjustment signals; disabling the off-line calibration mode; applying a communication signal; and adjusting the communication signal based on the stored one or more calibration adjustment signals. | 01-28-2010 |
| 20100022199 | APPARATUS AND METHOD FOR CALIBRATION OF GAIN AND/OR PHASE IMBALANCE AND/OR DC OFFSET IN A COMMUNICATION SYSTEM - An example of a radio frequency (RF) receiver system for communication may include a receive channel frequency converter configured to provide a second receive calibration signal during a receive calibration mode based on a first receive calibration signal and a receive reference signal. The system may include a receive pre-distortion module coupled to the receive channel frequency converter. The receive pre-distortion module may be configured to provide a fourth receive calibration signal during the receive calibration mode based on a third receive calibration signal and one or more receive calibration adjustment signals. The one or more receive calibration adjustment signals may comprise an offset parameter associated with DC offset and an imbalance parameter associated with at least one of gain and phase imbalances. | 01-28-2010 |
| 20090256266 | APPARATUS AND METHOD FOR A CHIP ASSEMBLY INCLUDING A FREQUENCY EXTENDING DEVICE - A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands. | 10-15-2009 |
| 20090074407 | HIGH-SPEED SERIALIZER, RELATED COMPONENTS, SYSTEMS AND METHODS - A communication system includes a multiplexer configured to multiplex a first set of data channels into a first data channel and to multiplex a second set of data channels into a second data channel, and a delay adjuster configured to adjustably delay the first data channel based on a delay adjust command. The communication system also includes a first amplifier configured to amplify the delayed first channel into a first output data channel, and a second amplifier configured to amplify the second data channel into a second output data channel. The communication system further includes a first driver configured to convert the first output data channel into a first drive signal to drive an optical modulator, and a second driver configured to convert the second output data channel into a second drive signal to drive the optical modulator. | 03-19-2009 |
| 20080284531 | FRACTIONAL-N SYNTHESIZED CHIRP GENERATOR - A fractional-N synthesized chirp generator includes a fractional-N synthesizer and a digital ramp synthesizer. The fractional-N synthesizer has a frequency synthesizer and a sigma-delta modulator module. The fractional-N synthesizer is configured to receive a reference frequency input signal and a frequency control value. The fractional-N synthesizer is configured to transform the reference frequency signal and the frequency control value to a chirped radio frequency (RF) output signal in a deterministic manner. The digital ramp synthesizer is configured to receive the reference frequency input signal and configured to generate the frequency control value utilizing the reference frequency input signal. The digital ramp synthesizer is further configured to provide the frequency control value to the fractional-N synthesizer. The frequency control value varies with time. | 11-20-2008 |
