| Sicronic Remote KG, LLC Patent applications |
| Patent application number | Title | Published |
|---|
| 20080295042 | SYSTEM FOR DELAY REDUCTION DURING TECHNOLOGY MAPPING IN FPGA - The present invention relates to a system for reducing the delay during technology mapping in FPGA that comprises locating and replicating the critical fan-in nodes in the mapping logic. Parallel computation is performed on the replicated nodes followed by selection of the output. The delay reduction approach in the present invention gives a highly efficient logic implementation when delay is the prime concern and area can be afforded to be expanded. The technique relies on replicating logic and performing parallel computation on delay critical LUT's. | 11-27-2008 |
| 20080258764 | Interconnect Structure Enabling Indirect Routing in Programmable Logic - An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains. | 10-23-2008 |
| 20080252334 | ADDING OR SUBTRACTING INPUTS USING A CARRY SIGNAL WITH A FIXED VALUE OF LOGIC 0 - A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed value of logic 0. The device is further configured to provide an output that has a value of the sum or the difference of the received inputs. | 10-16-2008 |
