| Shanghai IC R&D Center Co., Ltd. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110039405 | METHOD FOR FABRICATING A SONOS MEMORY - The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices. | 02-17-2011 |
| 20100311244 | DOUBLE-EXPOSURE METHOD - The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) material on the first photoresist pattern, promote thermal crosslinking reaction at the interface between the RELACS materials and the first photoresist pattern; afterwards, remove the RELACS material which does not crosslink with the first photoresist pattern. This method not only realizes higher lithography resolution, but also avoids the adverse effects of the second exposure on the first photoresist pattern in double-exposure technology. | 12-09-2010 |
