SEMTECH CORPORATION Patent applications |
Patent application number | Title | Published |
20160127523 | Method and Device for Capacitive Near-Field Communication in Mobile Devices - A mobile device includes a conductive element and a ground node. The conductive element is configured to be detected by a proximity sensor. A switch is coupled between the conductive element and ground node. The conductive element is coupled to the ground node by closing the switch. A first memory element is configured to control the switch. The first memory element includes a register bit coupled to a control terminal of the switch. A data output is configured to control the switch. A FIFO is configured to provide data to the data output. The first memory element includes a FIFO. A capacitive touch controller is configured to measure a capacitance of the conductive element. A digital processing unit is configured to convert the capacitance of the conductive element to a bit of data. A second memory element is configured to store the bit of data. | 05-05-2016 |
20160124574 | Method and Device for Reducing Radio Frequency Interference of Proximity and Touch Detection in Mobile Devices - A proximity sensor has a sensing node. A radio frequency signal is received at the sensing node. The radio frequency signal is coupled to an intermediate node through a first capacitor. The radio frequency signal is coupled from the intermediate node to a ground node through a second capacitor. An RF amplifier is coupled to the sensing node. The radio frequency signal is generated using the RF amplifier. A third capacitor is coupled between the RF amplifier and the sensing node. An antenna is coupled to the sensing node. The radio frequency signal is transmitted using the antenna. A capacitance of the antenna is measured using the proximity sensor. The capacitance of the antenna is compared to a threshold to determine proximity of a conductive object. An inductor is coupled between the sensing node and the antenna. A shielding area is coupled to the intermediate node. | 05-05-2016 |
20160124573 | Method and Device for Improved Accuracy of Proximity and Touch Detection in Mobile Devices - A mobile device has a proximity sensor. A compensation value of the proximity sensor is determined. The compensation value is compared to a reference compensation value to determine validity of the compensation value. A capacitance of the proximity sensor is measured. A value of the capacitance of the proximity sensor is adjusted based on the compensation value. A coefficient defining a relationship between a capacitance of the proximity sensor and a temperature of the mobile device is calculated. A temperature sensor is coupled to the proximity sensor. The temperature of the mobile device is measured. A value of the capacitance of the proximity sensor is adjusted based on the coefficient and the temperature of the mobile device. The adjusted capacitance value is compared to a threshold capacitance value to determine proximity of an object to the mobile device. A radio frequency signal is adjusted by detecting proximity. | 05-05-2016 |
20150312022 | LOW-POWER, LOW-LATENCY ARCHITECTURE FOR TELECOM AND DATACOM MULTIPLEXERS AND DEMULTIPLEXERS - Described herein are systems and methods for reducing power consumption, latency, and chip complexity in a datacom/telecom multiplexer and demultiplexer. Adding a high frequency analog domain data path around or in place of a standard digital core data path allows the elimination of the demultiplexing and multiplexing stages required to drop the data rate of data streams down to that required for a standard digital core. Latency is also reduced due to the higher operating frequency of sequential elements required for data operations. The digital core can be powered down when not in use, and can be activated when necessary. | 10-29-2015 |
20150054561 | Semiconductor Device and Method of Cascading Matched Frequency Window Tuned LC Tank Buffers - A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength. | 02-26-2015 |
20140266251 | Semiconductor Device and Method of Direct Measurement and Acquisition of MEMS Employing Sigma-Delta Loop - A semiconductor device measures a state of a MEMS as a first voltage variation at a sensing node. The state of the MEMS includes a capacitance. A first capacitor is coupled between the sensing node and an input of an integrator for transferring the first voltage variation to a second node as a first signal. A second voltage variation is routed through a second capacitor to the second node as a second signal. The integrator integrates the first signal and second signal to provide an integrated signal. An ADC has an input coupled to an output of the integrator and converts the integrated signal to a digital signal representative of the capacitance of the MEMS. A DAC has an input coupled to the output of the ADC. A second capacitor is coupled between an output of the DAC and the sensing node. | 09-18-2014 |
20140255037 | OPTICAL TRANSMISSION FOR BINARY AND DUOBINARY MODULATION FORMATS - A transceiver includes a transmitter and a receiver. The transmitter includes a precoder stage, an encoder stage and a first converter stage. The precoder stage receives an input binary signal and a previously processed binary signal. The encoder stage is electrically coupled to the precoder stage and the first converter stage and includes a feed forward equalizer (FFE). The first converter stage generates a modulated signal. The receiver includes a second converter stage, an amplifier stage, a first equalizer stage and a second equalizer stage. The second converter stage receives the modulated signal. The first equalizer stage is electrically coupled to the amplifier stage. The second equalizer stage is electrically coupled to the first equalizer stage. The second equalizer stage includes a decision feedback equalizer (DFE) that converts the modulated signal into an output binary signal. | 09-11-2014 |
20140210441 | ADAPTIVE SWITCHING FREQUENCY ADJUSTMENT FOR A POWER SUPPLY - Described herein are systems and methods for providing a variable switching frequency for a power supply. The system includes a controller and a filter. The controller generates a switching frequency for a power supply. The switching frequency is modified as a function of an input voltage and an output voltage. The filter provides the output voltage to a load based at least in part on the switching frequency generated by the controller. In one example, the controller adaptively modifies the switching frequency as a function of the input voltage and the output voltage in order to maintain a peak to peak current for an inductor. | 07-31-2014 |
20140184248 | CAPACITANCE MEASUREMENT OF HIGH VOLTAGE DEVICE - Described herein are systems and methods that facilitate the measurement of the capacitance of high voltage devices while shielding an active device involved in the measurement from the high voltage. The systems and methods employ capacitors to store the high voltage such that the active device does not experience the high voltage. Placement of a reset device ensures that the active device is shielded from the high voltage. | 07-03-2014 |
20140133524 | HYBRID RESISTIVE DIGITAL-TO-ANALOG DEVICES - A differential resistor-based digital-to-analog converter (RDAC) can include a positive digital-to-analog converter (PDAC) stage and a negative digital-to-analog converter (NDAC) stage. A first network of resistors of the PDAC stage can be electrically coupled to a second network of resistors of the NDAC stage utilizing an intermediary network of resistors. Further, a differential receiver can include a first input and a second input. The first input can be electrically coupled to a first resistor of the intermediary network of resistors, and the second input can be electrically coupled to a second resistor of the intermediary network of resistors. Furthermore, a portion of the first network of resistors can be electrically coupled to a positive output of the RDAC, and another portion of the second network of resistors can be electrically coupled to a negative output of the RDAC. | 05-15-2014 |
20140125413 | INSTRUMENTATION AMPLIFIER WITH RAIL-TO-RAIL INPUT RANGE - A system and method for adjusting a common mode output voltage in an instrumentation amplifier is provided. In one aspect, the common mode output voltage is increased or decreased with respect to the common mode input voltage to enable high amplification of the signal input to the instrumentation amplifier. Moreover, the common mode output voltage can be driven to (or approximately to) a target voltage value such as, but not limited to, half the supply, even if the common mode input voltage is close to supply or ground rail voltage. Thus, a high amplification of the differential input voltage can be obtained and utilized for various applications requiring rail to rail input. | 05-08-2014 |
20140104903 | REDUCTION OF ELECTROSTATIC DISCHARGE EFFECTS IN CHARGE-PUMP ELEVATOR LADDER - The final cell or cells in a cascade or ladder of voltage elevator cells may be exposed to significant overvoltages from electrostatic discharge originating in off-chip loads. In such conditions, the final cell or cells may be damaged or destroyed by such overvoltages. Protective circuitry may be added to one or more of the final voltage elevator cells to reduce or eliminate such damage or destruction by distributing the overvoltage among two or more cells. Such protective circuitry may include a capacitor coupled in parallel with the input and output node of one or more of the final voltage elevator cells. The protective circuitry may also include a resistor coupled in series between the final voltage elevator cell and the load. | 04-17-2014 |
20140103415 | Semiconductor Device and Method of Preventing Latch-Up in a Charge Pump Circuit - A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell. | 04-17-2014 |
20140097887 | REDUCTION OR ELIMINATION OF IRREGULAR VOLTAGE DISTRIBUTION IN A LADDER OF VOLTAGE ELEVATORS - The voltage distribution in a cascade or ladder of voltage elevator cells may become irregular in certain conditions. In such conditions, one or more cells may become overstressed. Corrective circuitry may be added to one or more of the voltage elevator cells to reduce or eliminate such stresses. Such corrective circuitry may include a capacitor, a long-channel PMOS transistor, both a capacitor and a long-channel PMOS transistor in parallel, or other electrically equivalent components coupled in parallel with the input and output node of one or more of the voltage elevator cells. | 04-10-2014 |
20140084958 | LOW-VOLTAGE, HIGH-SPEED, CURRENT-MODE LATCH WITH INDUCTOR TAIL AND COMMON-MODE FEEDBACK FOR AMPLITUDE AND CURRENT CONTROL - Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively. | 03-27-2014 |
20140015595 | CAPACITIVE BODY PROXIMITY SENSOR SYSTEM - Described herein are systems, methods and apparatuses that can detect the proximity of an object and differentiate between a human body and a non-human object. The detection and differentiation are facilitated by a first capacitive sensor of a first shape and a second capacitive sensor of a second shape. The detection and determination can be made based on a comparison between a first capacitance from the first sensor and a second capacitance from the second sensor. | 01-16-2014 |
20130278329 | ANALOG LOOP FILTER SYSTEMS, APPARATUS, AND METHODS - Described herein is a distributed analog loop filter that can be employed in a phase locked loop or a delay locked loop. A circuit block of the distributed analog loop filter includes at least two parallel equivalent circuit elements. The parallel equivalent circuit elements each have an input line. The input lines for each of the parallel equivalent circuit elements are activated sequentially, one after the other. The parallel equivalent circuit elements have sequentially produced outputs that are also activated sequentially, one after another. The parallel equivalent circuit elements extend the tuning range of distributed analog filter while reducing noise associated with the distributed analog filter. | 10-24-2013 |
20130249623 | LOW VOLTAGE MULTI-STAGE INTERLEAVER SYSTEMS, APPARATUS AND METHODS - Described herein is a low-voltage multi-stage interleaver. The interleaver includes at least a first interleaver stage and a second interleaver stage. The first interleaver stage is either blocked or operating in a saturation region. The first interleaver stage facilitates cancellation of DC current, including a biasing current, so that the second interleaver stage receives no DC current input. The second interleaver stage is either blocked or operating in a linear region to allow the second interleaver stage to act as a passive current switch. | 09-26-2013 |
20130201043 | SERIAL-RIPPLE ANALOG-TO-DIGITAL CONVERSION - Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage. | 08-08-2013 |
20130130441 | CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD - A method of packaging one or more semiconductor dies includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame; attaching a lid to the chip-scale frame to form a substantially airtight chamber around the first die. | 05-23-2013 |
20130120176 | RESISTIVE DIGITAL-TO-ANALOG CONVERSION - Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal. | 05-16-2013 |
20130106629 | MULTI-BIT SUCCESSIVE APPROXIMATION ADC | 05-02-2013 |
20130033248 | Methods to Reduce Output Voltage Ripple in Constant On-Time DC-DC Converters - According to one aspect of the teachings herein, a DC-to-DC converter operates according to an advantageous constant on-time topology that reduces output voltage ripple during light load conditions. The converter produces an output voltage by driving high-side and low-side switches in an inductor-based switching circuit, and regulates the output voltage by varying the on-time of a low-side switch, while holding the on-time of the high-side switch constant. Advantageously, the converter shortens the on-time of the high-side switch during light load conditions, which reduces the output voltage ripple. Thus, the converter may be understood as using a first, constant on-time for the high-side switch during “normal” operations and a second, shorter on-time for the high-side switch during light load conditions. | 02-07-2013 |
20120168928 | CHIP ASSEMBLY WITH FREQUENCY EXTENDING DEVICE - A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands. | 07-05-2012 |
20120115279 | CHIP-SCALE SEMICONDUCTOR DIE PACKAGING METHOD - A method of packaging one or more semiconductor dies is provided. The method includes: providing a first die having a circuit surface and a connecting surface; providing a chip-scale frame having an inside surface and an outside surface, the chip-scale frame having a well region having an opening in the inside surface; coupling the first die to a wall of the well region using a first coupling mechanism for electrical and mechanical coupling; providing a substrate having a top surface and a bottom surface; coupling the inside surface of the chip-scale frame with the top surface of the substrate by a second coupling mechanism, wherein a gap is provided between the circuit surface of the first die and the top surface of the substrate; coupling a heat sink to the outside surface of the chip-scale frame using a third coupling mechanism. | 05-10-2012 |
20110241125 | Power Semiconductor Device with Low Parasitic Metal and Package Resistance - A power semiconductor device includes a semiconductor die with a power transistor on a semiconductor substrate, a plurality of wiring layers vertically spaced apart from one another and the transistor, and a plurality of conductive bumps on each wire of the wiring layer spaced farthest from the substrate. Each wire of the layer closest to the substrate is electrically connected to a terminal of the transistor. The wires of the layer spaced farthest from the substrate extend in generally parallel lines and are electrically connected to a terminal of the transistor through each underlying layer. An additional metal layer having a thickness of at least 50 μm is connected to the die so that contact regions of the additional metal layer are electrically connected to the bumps of the die. | 10-06-2011 |
20090184687 | Method and Apparatus for Battery Charging Based on Battery Capacity and Charging Source Constraints - A battery charging circuit sets charging current according to either the capacity of the battery under charge or a constraint of the charging source, depending on the properties of the charging source. The battery charging circuit sets termination current, however, according to the capacity of the battery under charge, regardless of the properties of the charging source. For example, the termination current may be set as a fixed fraction of the recommended C rate of the battery even if the charging current supplied by the charging source is below this C rate. Always setting the termination current in proportion to the battery's capacity permits detection of the current at which charging should terminate even when the charging current is constrained by the charging source and no longer depends on the battery's capacity. | 07-23-2009 |
20090066308 | Switched Mode Power Supply Having Variable Minimum Switching Frequency - In a switched mode power supply (SMPS) that regulates an output voltage in response to load conditions by switching an inductor circuit between a supply voltage and ground at a switching frequency, under light loading conditions, the switching frequency of the SMPS is reduced down to a variable minimum switching frequency sufficiently high to avoid audible noise generation. | 03-12-2009 |
20090016085 | Method and Apparatus for a Charge Pump DC-to-DC Converter Having Parallel Operating Modes - According to one or more aspects of DC-to-DC voltage conversion as taught herein, a DC-to-DC converter selectively operates in a first mode wherein an included linear pass output circuit supplies the output power from the DC-to-DC converter, in a second mode wherein an included charge pump output circuit supplies the output power, and in a third mode wherein the linear pass and charge pump output circuits operate in parallel to supply the output power. With this third mode, also referred to as a “dual” mode, wherein the linear pass and charge pump output circuits operate in parallel, the DC-to-DC converter keeps the more efficient output circuit on after it has begun switching to operation with the less efficient output circuit. Such switchover may be performed dynamically in response to changing operating conditions. Detected operating conditions may include input voltages, output voltages, and output load conditions. | 01-15-2009 |