| Semiconductor Technology Academic Research Center Patent applications |
| Patent application number | Title | Published |
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| 20110189849 | SEMICONDUCTOR DEVICE WITH A BARRIER FILM - A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film. | 08-04-2011 |
| 20110187469 | WIDEBAND OSCILLATION CIRCUIT - A wideband oscillation circuit outputting oscillation signals (divided signals) of continuous frequencies is disclosed and the wideband oscillation circuit includes an oscillator that outputs an oscillation signal, a filter that filters the oscillation signal output from the oscillator and outputs an injection locked signal, and an injection locked frequency divider that performs a free-run operation and outputs a divided signal of the oscillation signal while its oscillating operation is regulated by the injection locked signal, the division ratio of which varies in accordance with a control signal, wherein the filter generates the injection locked signal by controlling the passing characteristic that caused the oscillation signal to pass with respect to time in accordance with a filter control signal locked with the divided signal. | 08-04-2011 |
| 20110133971 | ANALOG-TO-DIGITAL CONVERTER - An SAR ADC includes a digital-to-analog converter, a first comparator that compares an input analog signal with a reference analog signal, a second comparator that compares an input analog signal with a reference analog signal, a selection circuit that selects one of comparison results of the first comparator and the second comparator, and a control circuit that changes the multibit digital signal sequentially based on the selected comparison result in a plurality of steps so that the reference analog signal becomes closer to the input analog signal, and the control circuit controls the selection circuit to select the comparison result of the first comparator up to an intermediate step on the way of the plurality of steps and to select the comparison result of the second comparator after the intermediate step, and changes the bit value of the multibit digital signal according to the non-binary algorithm. | 06-09-2011 |
| 20110127486 | Phase-change memory device, phase-change channel transistor and memory cell array - A phase-change channel transistor includes a first electrode; a second electrode; a memory layer provided between the first and second electrodes; and a third electrode provided for the memory layer with an insulating film interposed therebetween, wherein the memory layer includes at least a first layer formed from a phase-change material which is stable in either an amorphous phase or a crystalline phase at room temperature and a second layer formed from a resistive material, and wherein the resistance value of the second layer is smaller than the resistance value of the first layer in the amorphous phase, but is larger than the resistance value of the first layer in the crystalline phase. | 06-02-2011 |
| 20110090103 | ANALOG-TO-DIGITAL CONVERTER - A sequential comparison-type analog-to-digital converter (ADC) that has improved precision and which is capable of high-speed operation is disclosed, the analog-to-digital converter comprising a digital-to-analog converter that outputs a plurality of different reference analog signals according to a multibit digital signal, a plurality of comparators that compare an input analog signal with the plurality of reference analog signals, and a sequential comparison control circuit that changes bit values of the multibit digital signal in order from higher bits so that at least one of the plurality of reference analog signals becomes closer to the input analog signal and decides the bit values in order from higher bits based on the comparison results and at the same time, correcting the decided higher bit values, wherein the sequential comparison control circuit decides the bit values of the multibit digital signal down to a predetermined bit based on the comparison results of the plurality of comparators and at the same time, correcting the bit values, and decides the bits lower than the predetermined bit based on the comparison result of one of the plurality of comparators. | 04-21-2011 |
| 20110037502 | DIGITAL HIGH-FREQUENCY GENERATOR CIRCUIT - A high-frequency generator circuit comprises a signal generating circuit, a delay unit, a selector, a synthesizer circuit, and a controller. The signal generating circuit generates a signal having the same frequency as an output signal. The delay unit includes a plurality of delay circuits, and delays the signal generated by the signal generating circuit. The selector selects an output signal of the delay circuits. The synthesizer circuit synthesizes the signal selected by the selector, and outputs the output signal. The controller controls the selector based on data for setting a waveform of the output signal and a control signal for setting at least amplitude, phase and frequency of the output signal. | 02-17-2011 |
| 20100295627 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator that can achieve low phase noise while ensuring stable oscillation startup and stable oscillation maintenance even under low supply voltage conditions. The voltage-controlled oscillator includes an LC parallel resonant circuit, whose impedance varies with a control input voltage and a negative resistance circuit for introducing negative resistance into the LC parallel resonant circuit, wherein the negative resistance circuit includes at least: a first amplifier circuit, provided in parallel with the LC parallel resonant circuit and having a first pair of transistors cross-coupled via a capacitor, that achieves class-C amplifier operation by biasing the gate of each transistor in the first transistor pair with a first bias voltage; and a similarly configured second amplifier circuit that achieves class-C amplifier operation by biasing the gate of each transistor with a second bias voltage which is different from the first bias voltage. | 11-25-2010 |
| 20100283027 | MULTI-VALUE RECORDING PHASE-CHANGE MEMORY DEVICE, MULTI-VALUE RECORDING PHASE-CHANGE CHANNEL TRANSISTOR, AND MEMORY CELL ARRAY - A multi-value recording phase-change memory device that can stably record multi-value information, and that can reproduce information with high reliability, comprises a first electrode layer | 11-11-2010 |
| 20100128823 | DOPPLER FREQUENCY ESTIMATING DEVICE, RECEIVING DEVICE, RECORDING MEDIUM AND DOPPLER FREQUENCY ESTIMATING METHOD - A device of an example of the invention comprises a first section which performs IFFT for a channel estimation value obtained by channel estimation to obtain a channel impulse response, a second section which selects paths that belong to a group having a large element based on elements of paths for the channel impulse response, a third section which calculates autocorrelation values by time averaging for each of the paths selected by the second section, a fourth section which obtains an ensemble average value of the autocorrelation values by time averaging obtained by the third section, and a fifth section which obtains a Doppler frequency associated with the ensemble average value based on a characteristic of a relationship between an autocorrelation value and an Doppler frequency and the ensemble average value. | 05-27-2010 |
| 20100112776 | APPARATUS FOR FORMING CONDUCTOR, METHOD FOR FORMING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device. | 05-06-2010 |
| 20100083379 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE RECORDING MEDIUM - An example of a device comprises a storage which stores data which is input from outside and to which tracking information is added, a section which detects a first reading event of first data from the storage to which the tracking information is added, a section which detects, after the first reading event, a first writing event to part of character string data to the storage, a section which detects, after the first writing event, a second reading event of second data from the storage to which the tracking information is added, a section which detects, after the second reading event, a second writing event to part of the character string data to the storage, and a section which adds, when the first reading/writing event, second reading/writing event are detected, the tracking information to data to be written to the storage by the first and second writing event. | 04-01-2010 |
| 20090325328 | Plasma processing apparatus and plasma processing method - A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer. | 12-31-2009 |
| 20090236747 | Semiconductor device and method for fabricating the same - A multilevel interconnect structure in a semiconductor device comprises a first insulating layer ( | 09-24-2009 |
| 20090106720 | TIMING ANALYSIS APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT IN CONSIDERATION OF POWER SUPPLY AND GROUND NOISES - In a timing analysis apparatus for use in a semiconductor integrated circuit, which analyzes operation timing of a semiconductor integrated circuit having a logic gate circuit including a plurality of logic gates, a controller detects at least one of a power supply voltage and a ground voltage of a power supply, decomposes the noise waveform into frequency components, classifies the frequency components into low-frequency components lower than a predetermined threshold frequency and high-frequency components higher than the threshold frequency, calculates a static delay time of each of the logic gates due to the low-frequency components, calculates a dynamic delay time of each of the logic gates due to the high-frequency components, and determines a delay time of each of the logic gates by synthesizing the calculated respective delay times. | 04-23-2009 |
| 20080297203 | CURRENT MIRROR CIRCUIT - A current mirror circuit including: a first resistance element having one terminal connected to a first potential, and the other terminal connected to a second potential lower than the first potential; an operational amplifier having a high-potential input terminal connected to the first potential and the one terminal of the first resistance element; a second resistance element having one terminal connected to a low-potential input terminal of the operational amplifier, and the other terminal connected to the second potential; and a transistor having a first electrode connected to an output terminal of the operational amplifier, a second electrode connected to the low-potential input terminal of the operational amplifier and the one terminal of the second resistance element, and a third electrode used as an output terminal, wherein the first and second resistance elements both start to operate from a linear area having lower voltage than a saturation area. | 12-04-2008 |
| 20080288796 | MULTI-PROCESSOR CONTROL DEVICE AND METHOD - A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit. | 11-20-2008 |
| 20080238752 | Analog-to-digital (AD) converter and analog-to-digital conversion method - An AD converter that operates at high speed and precision of which is disclosed. The AD converter includes an analog-to-digital (AD) conversion part that samples an analog signal according to a sampling clock and converts it into a digital signal, a jitter measuring circuit that measures the jitter of the sampling clock, and a correction circuit that corrects a digital signal output from the AD conversion part. The AD converter further comprises a clock source and a sampling generating circuit that generates a sampling clock by dividing the clock generated by the clock source, wherein the jitter measuring circuit measures the jitter of the sampling clock with respect to the click on the basis of a clock CK. | 10-02-2008 |
| 20080238566 | High frequency oscillator circuit with feedback circuit of fet and short-stub transmission line - In a high frequency oscillator circuit including first and second field effect transistors, the first field effect transistor has a gate connected to a short-stub transmission line and a drain connected to an oscillation output terminal, and the second field effect transistor has a drain connected to a source of the first field effect transistor and a grounded source. The high frequency oscillator circuit oscillates by using a feedback circuit including the short-stub transmission line and the second field effect transistor. A feedback capacitor is further provided which is connected between a gate of the second field effect transistor and the drain of the first field effect transistor. | 10-02-2008 |
| 20080233705 | METHOD FOR SELECTIVELY FORMING ELECTRIC CONDUCTOR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for selectively forming an electric conductor, the method including disposing a processing target and a metal compound in an atmosphere including a supercritical fluid, the processing target having formed thereon at least one recess for providing an electric conductor, the metal compound including a metal serving as a main component of the electric conductor, and dissolving at least part of the metal compound in the supercritical fluid, selectively introducing the metal compound dissolved in the supercritical fluid into the recess in contact with a surface of the processing target, and coagulating in the recess the metal compound introduced into the recess to precipitate the metal from the metal compound, and coagulating the metal precipitated in the recess, thereby providing the electric conductor in the recess. | 09-25-2008 |
| 20080222360 | MULTI-PORT INTEGRATED CACHE - A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port. | 09-11-2008 |
| 20080206949 | APPARATUS FOR FORMING CONDUCTOR, METHOD FOR FORMING CONDUCTOR, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conductor forming apparatus includes a reaction container having housed therein a processing target on a surface of which a recess in which a conductor is to be provided is formed, and a process for providing the conductor in the recess being carried out inside the container after a supercritical fluid dissolved with a metal compound is supplied into the container, a supply device which supplies the fluid from an outside to the inside of the container, and a discharge device which discharges the fluid that is not submitted for the process from the inside to the outside of the container, wherein while an amount of the fluid in the container is adjusted by continuously supplying the fluid into the container by the supply device and continuously discharging the fluid that is not submitted for the process to the outside of the container by the discharge device. | 08-28-2008 |
