| Semiconductor Manufacturing International (Shanghai) Corporation Patent applications |
| Patent application number | Title | Published |
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| 20120129314 | METHOD AND RESULTING STRUCTURE FOR DEEP TRENCH POLYSILICON HARD MASK REMOVAL - A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth. | 05-24-2012 |
| 20120115328 | ELECTROFORMING TECHNIQUE FOR MASK FORMATION - A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer. | 05-10-2012 |
| 20120115282 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions. | 05-10-2012 |
| 20120112315 | METHOD AND SYSTEM FOR MANUFACTURING COPPER-BASED CAPACITOR - Embodiments of the present invention provide a method and system for manufacturing copper-based capacitor on an integrated circuit. For example, the integrated circuit is associated with a channel length of less than 0.13 um. It is to be appreciated that, depending upon application, the present invention provides a more improved method for manufacturing capacitors and thus allow MIM capacitors to be manufactured at smaller dimensions. The method includes a step for providing a substrate. The method also includes a step for providing a layer of inter-metal dielectric overlaying the substrate. The method additionally includes a step for providing a bottom layer. The bottom layer includes a first portion and a second portion. The first portion can be characterized as electrically conductive. In addition, the method includes a step for providing a first insulating layer overlaying the bottom layer. | 05-10-2012 |
| 20120108054 | Dual Damascene Copper Process Using a Selected Mask - A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure. | 05-03-2012 |
| 20120092604 | METHOD AND STRUCTURE FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DEVICES - The present invention provides an LCOS device having improved bonding pad features. The device has a substrate, a transistor layer overlying the substrate and an interlayer dielectric layer overlying the transistor layer. A first conductive layer is overlying the interlayer dielectric layer and a second interlayer dielectric layer is overlying the first conductive layer. An enlarged opening for a bonding pad structure is in a first portion of the second interlayer dielectric layer. A barrier metal layer is formed within the enlarged opening to form a liner that covers exposed regions of the enlarged opening. A metal material is overlying the liner to fill the enlarged opening. A thickness of an aluminum material is overlying the metal material. The device has a bonding pad structure formed from a first portion of the thickness of the aluminum material and is coupled to the metal material in the enlarged opening. | 04-19-2012 |
| 20120091462 | TFT MONOS OR SONOS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N | 04-19-2012 |
| 20120091458 | SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MAS MEMORY CELL STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally. | 04-19-2012 |
| 20120088363 | METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION - A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a gold material. The gold material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the gold material. Additionally, the method includes conductively connecting the gold material with the substrate. | 04-12-2012 |
| 20120081649 | METHOD AND RESULTING CAPACITOR STRUCTURE FOR LIQUID CRYSTAL ON SILICON DISPLAY DEVICES - A liquid crystal on silicon display device (LCOS) has a semiconductor substrate comprising a surface region and a gate dielectric layer overlying the surface region. The device also has a word line formed overlying the gate dielectric layer and a first source/drain region coupled to the word line. The device has a bottom electrode structure formed overlying an interlayer dielectric. A capacitor dielectric is formed overlying the bottom electrode. A top electrode structure is formed overlying the capacitor dielectric to form a capacitor structure including the bottom electrode structure, the capacitor dielectric, and the top electrode structure. The device has a mirror surface formed overlying the top electrode structure to form a pixel electrode structure and a liquid crystal material provided overlying the mirror surface. In an embodiment, the LCOS described above is in an integrated circuit chip that also includes a DRAM device. | 04-05-2012 |
| 20120074539 | DEVICE AND METHODS FOR ELECTROSTATIC DISCHARGE PROTECTION - An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss. | 03-29-2012 |
| 20120070915 | METHOD FOR COPPER HILLOCK REDUCTION - A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an inner-metal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic. | 03-22-2012 |
| 20120069682 | WORD LINE BOOSTER FOR FLASH MEMORY DEVICE - A nonvolatile memory device includes an array of rows and columns of memory cells and a plurality of word lines and bit lines associated with the memory cells. The memory device further includes a word line booster circuit coupled with the word lines for supplying a selected word line with the specific voltage as a drive voltage during an operation of the memory device, wherein the word line booster circuit includes a first boosting capacitor and a second boosting capacitor connected in parallel each other adapted to generate a boosting voltage and a first precharge circuit for precharging the first boosting capacitor and the second boosting capacitor. the word line booster circuit further includes a third boosting capacitor operatively connected to the first boosting capacitor and the second boosting capacitor via a charge-sharing transistor, the third boosting capacitor being connected to one end of a load resistor to generate an output signal at the other end of the load resistor when the charge sharing transistor is enabled. In addition, the word line booster circuit includes a high voltage detector to generate a detecting signal in response to a control signal from an address transition detector and the output signal generated by the third boosting capacitor and load resistor and a clock control circuit adapted to enable the charge sharing transistor and to disable one of the first boosting capacitor and the second boosting capacitor upon receiving the control signal from the address transition detector and the detecting signal from the voltage detector. The word line booster circuit further includes a discharge circuit to discharge the boosting voltage at a node connected to the third boosting capacitor. | 03-22-2012 |
| 20120061765 | ANTI-FUSE BASED PROGRAMMABLE SERIAL NUMBER GENERATOR - An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage. | 03-15-2012 |
| 20120034771 | BOND PAD FOR LOW K DIELECTRIC MATERIALS AND METHOD FOR MANUFACTURE FOR SEMICONDUCTOR DEVICES - A method for manufacturing a semiconductor device having improved contact structure includes providing a semiconductor substrate, forming a plurality of gate structures formed on a portion of the substrate, forming an interlayer dielectric layer overlying the gate structures, and forming a first copper interconnect layer overlying the substantially flat surface region of the interlayer dielectric layer. The method further includes forming a dielectric layer overlying the first copper interconnect layer, forming a second copper interconnect layer overlying the dielectric layer, and providing a copper ring structure enclosing an entirety of an inner region of the dielectric layer, the copper ring structure being provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the dielectric layer. In addition, the method includes forming a bonding pad structure overlying a region within the inner region of the dielectric layer. | 02-09-2012 |
| 20120032732 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions. | 02-09-2012 |
| 20120023464 | AUTOMATIC IDENTIFICATION OF SYSTEMATIC REPEATING DEFECTS IN SEMICONDUCTOR PRODUCTION - A method includes capturing an image of the pattern using one or more scans across a surface of the partially completed wafer. The method includes processing information associated with the captured image of the pattern in a first format (e.g., pixel domain) into a second format, e.g., transform domain. The method includes determining defect information associated with the image of the pattern in the second format and processing the defect information (e.g., wafer identification, product identification, layer information, x-y die scanned) to identify at least one defect associated with a spatial location of a repeating pattern on the partially completed wafer provided by a reticle. The method includes identifying the reticle associated with the defect and a stepper associated with the reticle having the defect and ceasing operation of the stepper. The damaged reticle is replaced, and the process resumes using a replaced reticle. | 01-26-2012 |
| 20120014021 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage. | 01-19-2012 |
| 20120012960 | METHOD AND SYSTEM OF EMBEDDED MICROLENS - A method of making an embedded microlens includes providing a substrate having a photo-sensing region, forming a dielectric film overlying the substrate, forming a mask having a circular opening over the dielectric film, the opening being center-aligned over the photo-sensing region, and etching the dielectric film to form a cavity under the mask by introducing an isotropic etchant through the opening, the cavity being characterized by a truncated plano-convex shape having a flat circular bottom and curved peripheral sides convex towards the dielectric film. The method further includes removing the mask, depositing a lens material with a higher refractive index than that of the dielectric film to fill the cavity, planarizing the lens material to form the embedded microlens in the cavity having a smooth top surface, and forming a color filter layer overlying the microlens. The dielectric film includes silicon dioxide having a refractive index of 1.5 or less. | 01-19-2012 |
| 20120001261 | SYSTEM AND METHOD FOR INPUT PIN ESD PROTECTION WITH FLOATING AND/OR BIASED POLYSILICON REGIONS - A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain. | 01-05-2012 |
| 20110318673 | SYSTEM AND METHOD FOR TEST PATTERN FOR LITHOGRAPHY PROCESS - A method for performing a photolithography process includes providing a reticle on a projection apparatus, the reticle having a test pattern defined thereon, the test pattern including a plurality of one-dimensional structures and a plurality of two-dimensional structures. The test pattern defined on the reticle is transferred to at least one area on a wafer. The projection apparatus is focused on the test pattern transferred on the wafer during a photolithography process to perform a process monitoring. | 12-29-2011 |
| 20110304013 | INTEGRATED INDUCTOR - A method of fabricating an integrated inductor device includes providing a silicon substrate and forming a thickness of an insulating layer overlying the silicon substrate. The insulating layer includes a dummy structure within a portion of the thickness. The method includes forming an inductor having a first portion and a second portion. The first portion includes a spiral coil of conductor lines. The method also includes exposing the dummy structure by forming an opening in the insulating layer and removing the dummy structure to form a cavity underlying the inductor to reduce a dielectric constant and to increase a Q value of the inductor. The method includes using aluminum or copper for the dummy structures. The method includes dry etching the insulator and wet etching the dummy structure. The method also includes forming the inductors using aluminum or copper. | 12-15-2011 |
| 20110300698 | METHODS FOR FORMING A GATE AND A SHALLOW TRENCH ISOLATION REGION AND FOR PLANARIZING AN ETCHED SURFACE OF SILICON SUBSTRATE - A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate. | 12-08-2011 |
| 20110300688 | METHODS FOR FORMING A GATE AND A SHALLOW TRENCH ISOLATION REGION AND FOR PLANARIZING AN ETCHED SURFACE OF SILICON SUBSTRATE - A method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, includes the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. The present invention further provides a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region, and a method for planarizing an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate. | 12-08-2011 |
| 20110298032 | ARRAY ARCHITECTURE FOR EMBEDDED FLASH MEMORY DEVICES - A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant. The select device is activated by applying voltage to the second portion of first polysilicon layer. | 12-08-2011 |
| 20110291190 | System and method for integrated circuits with cylindrical gate structures - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 12-01-2011 |
| 20110279797 | APPARATUS AND METHOD FOR CALIBRATING LITHOGRAPHY PROCESS - A calibration wafer may bear one or more different mark types to facilitate inspection of a lithography process. A first mark type may be located on the outer peripheral portion of the wafer to indicate the desired boundary of an edge bead removal (EBR) region. A second mark type may be located on an outer peripheral portion of the wafer to indicate the desired boundary of a wafer edge expose region (WEE). A third mark type may indicate the border of a portion of the wafer expected to bear a wafer identification mark. A fourth mark type may be located at the center of the wafer to allow for precise and uniform application of liquid photoresist material to the calibration wafer. The calibration wafer may be employed in methods of rapidly and easily assessing the accuracy of various phases of photolithography processes. | 11-17-2011 |
| 20110254127 | METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO - A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided. | 10-20-2011 |
| 20110237009 | LCOS DISPLAY UNIT AND METHOD FOR FORMING THE SAME - An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit. | 09-29-2011 |
| 20110227553 | LOW POWER HIGH VOLTAGE REGULATOR FOR NON-VOLATILE MEMORY DEVICE - A high-voltage regulator includes a charge pump for generating a high voltage, a voltage regulator for generating a regulated voltage, and an oscillator having an oscillation frequency. The voltage regulator includes an operational amplifier having the high voltage as power supply, a first input, a second input coupled to a voltage reference, and an output. The voltage regulator further includes a first transistor having gate coupled to the output of the operational amplifier, a first terminal coupled to the high voltage and a second terminal coupled to a first voltage divider. The first voltage divider generates a first divided voltage that is coupled to the first input of the operational amplifier. The voltage regulator also includes a second voltage divider for providing a second divided voltage, wherein the second divided voltage controls the oscillator frequency. | 09-22-2011 |
| 20110217660 | SYSTEM AND METHOD OF SELECTIVE OPTICAL PATTERN ENHANCEMENT FOR SEMICONDUCTOR MANUFACTURING - System and method of selective optical pattern enhancement for semiconductor manufacturing. A method for performing a photolithography process includes providing a reticle pattern for a photomask, the reticle pattern including one or more active areas, the photomask including at least a first active area and a first insulation area. The method also includes identifying a first structure pattern defined by the reticle pattern. Additionally, the method includes defining a block area covering the first structure, the block area being positioned within the active area. The method further includes applying at least a first optical proximity correction to the reticle pattern to form a corrected pattern, the first optical proximity correction being restricted to the block area. Also, the method includes transferring the corrected pattern to a wafer. | 09-08-2011 |
| 20110215393 | ON-CHIP PLASMA CHARGING SENSOR - A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage. | 09-08-2011 |
| 20110215389 | DRAM CELL TRANSISTOR DEVICE AND METHOD - A semiconductor integrated circuit device includes a substrate, a well structure within the substrate, a first region, a second region, and multiple isolation regions within the well structure. The device further includes a channel region within the first region, a gate dielectric layer overlying the channel region, and a gate stack overlying the gate dielectric layer, the gate stack includes a silicide layer overlying a polysilicon layer. The device additionally includes LDD structures on sides of the channel region and spacers on sides of the gate stack. Furthermore, the device includes a source region and a drain region and a contact structure over the source region, and a junction between the contact structure and the source region being within the second region. | 09-08-2011 |
| 20110207033 | METHOD AND STRUCTURE FOR FABRICATING DARK-PERIPHERY MASK FOR THE MANUFACTURE OF SEMICONDUCTOR WAFERS - A photo mask blank structure for transferring a mask to an integrated circuit includes a transparent substrate, which has a surface region. The photo mask structure further includes an opaque film overlying the surface region, a negative photoresist material overlying the opaque film, a stop layer overlying the negative photoresist material, and a positive photoresist material overlying the stop layer. The positive photoresist material includes a first opening pattern, and the stop layer includes a second opening pattern that is associated with the first opening pattern of the positive photoresist material. The negative photoresist material includes a third opening pattern that is associated with the first and second opening patterns. The stop layer provides a separation between the negative photoresist material and the positive photoresist material. | 08-25-2011 |
| 20110204425 | METHOD AND DEVICE FOR CMOS IMAGE SENSING WITH MULTIPLE GATE OXIDE THICKNESSES - A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer with at least a first part and a second part on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first part of the gate oxide layer is associated with a first thickness, and the second part of the gate oxide layer is associated with a second thickness. The first thickness and the second thickness are different. The first gate region is located on the first part of the gate oxide layer associated with the first thickness, while the second gate region is located on both the first part of the gate oxide layer associated with the first thickness and the second part of the gate oxide layer associated with the second thickness. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well. | 08-25-2011 |
| 20110204363 | AMORPHOUS SILICON MONOS OR MAS MEMORY CELL STRUCTURE WITH OTP FUNCTION - A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally. | 08-25-2011 |
| 20110198734 | METHOD OF IMPROVING A SHALLOW TRENCH ISOLATION GAPFILL PROCESS - A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench. In addition, the method includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth. Also, the method includes removing the second portion of the dielectric layer from the trench. | 08-18-2011 |
| 20110187909 | METHOD AND SYSTEM FOR CMOS IMAGE SENSING DEVICE - Method and system for manufacturing CMOS image sensing device with reduced blooming. The method includes a step for providing a substrate material. The substrate material can be characterized by a first dimension and a second dimension. In addition, the method includes a step for defining an active region on the substrate material. The active region is characterized by a third dimension and a fourth dimension. The method further includes a step for defining a non-active region on the substrate material. The non-active region is different from the active region. The non-active region is characterized by a fifth dimension and a sixth dimension, the non-active region including a silicon material. The method includes a step for defining a depletion region within the active region. In addition, the method includes a step for forming an n-type region positioned above the depletion region. | 08-04-2011 |
| 20110171585 | Photolithography Method - A photolithography method is provided which includes: arranging a layout topography in a first mask and a second mask in such a way that at least a layout pattern of the layout topography is defined by an overlap area. The overlap area is formed when at least a first pattern of the first mask and at least a second pattern of the second mask are projected on a common surface and are overlapped to each other. Critical dimensions of the first mask and the second mask are larger than a resolution of a photolithography machine for preventing from bridging. | 07-14-2011 |
| 20110168554 | APPARATUS FOR TREATMENT OF SAMPLES FOR AUGER ELECTRONIC SPECTROMETER (AES) IN THE MANUFACTURE OF INTEGRATED CIRCUITS - An apparatus for treatment of a sample for the manufacture of integrated circuits includes a holder apparatus and a stage which is coupled to the holder apparatus. The stage is capable of holding a portion of a sample to be analyzed. The apparatus also includes a shield that is operably coupled to the stage to block a portion of the sample. The shield is capable of movement relative to the sample to block one or more portions of the sample. The shield is provided on a track member and is movable from a first spatial location to a second spatial location on the track member. The apparatus further includes an enclosure surrounding an entirety of the sample and the shield. | 07-14-2011 |
| 20110163369 | SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE - Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode. | 07-07-2011 |
| 20110161030 | Method And Device For Monitoring Measurement Data In Semiconductor Process - An embodiment of the present invention discloses a method for monitoring measurement data in a semiconductor process, which includes: updating measurement data of wafer performance parameters periodically from a real time system into an analysis database; retrieving from the analysis database the measurement data of a predetermined performance parameter for analysis covered in a time range required in a selected analysis rule according to information on the performance parameter for analysis and information on the selected analysis rule; determining whether the measurement data of the performance parameter retrieved from the analysis database violates a control range of the selected analysis rule, and if so, then transmitting alarm information for the performance parameter violating the control range of the selected analysis rule. The method and device according to the embodiments of the invention can automatically monitor measurement data of wafer performance parameters and discover an abnormal performance parameter. | 06-30-2011 |
| 20110156129 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE AND NANO-CRYSTALLINE SILICON LAYER - A method and system for forming a non-volatile memory structure. The method provides a semiconductor substrate and forms a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of a second silicon oxide layer overlying a surface region of the substrate. A hafnium oxide material is formed overlying the first and second silicon oxide layers and filling the undercut region. The hafnium oxide material has a nanocrystalline silicon material sandwiched between a first hafnium oxide layer and a second hafnium oxide layer. The hafnium oxide material is selectively etched while a portion of it is maintained in an insert region in a portion of the undercut region. | 06-30-2011 |
| 20110156123 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE LAYER - A method for manufacturing a twin bit cell structure of with a hafnium oxide material includes providing a semiconductor substrate having a surface region and forming a gate dielectric layer overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer and subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure. The method forms an undercut region underneath the polysilicon gate structure and subjects the polysilicon gate structure to an oxidization environment. Thereafter, the method forms a hafnium oxide material overlying the polysilicon gate structure including the undercut region and exposed portions of the gate dielectric layer. The hafnium oxide material is then selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed hafnium oxide material. | 06-30-2011 |
| 20110149085 | SYSTEM AND METHOD FOR CMOS IMAGE SENSING - A method is provided for determining a color using a CMOS image sensor. The CMOS image sensor includes an n-type substrate and a p-type epitaxy layer overlying the n-type substrate. The method includes applying a first voltage on the n-type substrate and obtaining a first output, which is associated with the first voltage. The method further includes applying a second voltage on the n-type substrate and obtaining a second output, which is associated with the second voltage. The method additionally includes applying a third voltage on the n-type substrate and obtaining a third output, which is associated with the third voltage. The method also includes providing a plurality of weighting factors and determining the color based on the plurality of weighting factors, the first output, the second output, and the third output. | 06-23-2011 |
| 20110143512 | METHOD FOR DUAL ENERGY IMPLANTATION FOR ULTRA-SHALLOW JUNCTION FORMATION OF MOS DEVICES - A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb). | 06-16-2011 |
| 20110140192 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH FLOATING POLYSILICON LAYER - A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material. | 06-16-2011 |
| 20110140191 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH SILICON NITRIDE LAYER - A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure. | 06-16-2011 |
| 20110140190 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH ALUMINUM OXIDE LAYER - A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure. | 06-16-2011 |
| 20110133264 | SYSTEM AND METHOD FOR EEPROM ARCHITECTURE - A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap. | 06-09-2011 |
| 20110115012 | METHOD FOR FABRICATING AN ENLARGED OXIDE-NITRIDE-OXIDE STRUCTURE FOR NAND FLASH MEMORY SEMICONDUCTOR DEVICES - A method of processing a flash memory device provides a semiconductor substrate including a surface region and forming a gate dielectric layer overlying the surface region. The method forms a floating gate layer having a thickness and including a first floating gate structure overlying a first portion of the gate dielectric layer and a second floating gate structure overlying a second portion of the gate dielectric layer. The method forms a trench region interposed between the first and second floating gate structures and extending through the entire thickness and through a portion of the surface region into a depth of the substrate. The method fills the entire depth of the trench region in the substrate and a portion of the trench region over the substrate using a dielectric fill material. The method forms an oxide on nitride on oxide (ONO) layer overlying the first and second floating gate structures and the dielectric material and a control gate overlying the ONO layer. | 05-19-2011 |
| 20110109856 | METHOD AND STRUCTURE FOR ELECTRO-PLATING ALUMINUM SPECIES FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DISPLAYS - Method and structure for electro-plating aluminum species for top metal formation of liquid crystal on silicon displays. In a specific embodiment, the invention provides a method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., semiconductor wafer, silicon wafer, silicon on insulator. The method includes forming a transistor layer (e.g., MOS transistors) overlying the substrate. The method includes forming an interlayer dielectric layer (e.g., PSG, BPSG, FSG) overlying the transistor layer. The method includes forming a first conductive layer overlying the interlayer dielectric layer and forming a second interlayer dielectric layer overlying the first conductive layer. A dual damascene via structure is formed within the second interlayer dielectric layer. The method deposits a barrier metal layer (e.g., TiN, Ti/TiN) within the dual damascene via structure to form a liner that covers exposed regions of the dual damascene via structure. | 05-12-2011 |
| 20110109340 | Interface Adapter For Connecting With A Test Probe - A interface adapter comprising a connecting board having the first ports and the second ports, the first ports being electrically connected with the second ports; a pin header having the first pins and the second pins, the first pins passing through the first ports, the second pins being connected with the second ports; a female header having openings for receiving the first pins, the connecting board being located between the pin header and the female header. The second pin is designed to O-shape or U-shape for providing enough position to connecting the test probe, preventing from disengagement of the chip from the test card. | 05-12-2011 |
| 20110108889 | SEMICONDUCTOR DEVICE WITH A 7F2 CELL STRUCTURE - A semiconductor device with a 7F | 05-12-2011 |
| 20110101464 | METHOD AND RESULTING STRUCTURE DRAM CELL WITH SELECTED INVERSE NARROW WIDTH EFFECT - A shallow trench isolation structure for integrated circuits includes a semiconductor substrate having a trench and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed around a perimeter of the trench. The trench has a bottom width of less than 0.13 microns and an upper width of less than 0.13 microns. A rounded edge is surrounding a periphery of the trench. The rounded edge has a radius of curvature greater than about 0.02 um. A planarized high density plasma fill material is formed within the trench. The structure has a P-well region within the semiconductor substrate and bordering a vicinity of the trench region. A channel region is within the P-well region within the semiconductor substrate. The implanted region has an impurity concentration of more than double an amount of impurities in the channel region. | 05-05-2011 |
| 20110095396 | METHOD AND STRUCTURE FOR SILICON NANOCRYSTAL CAPACITOR DEVICES FOR INTEGRATED CIRCUITS - An improved semiconductor device, including a capacitor structure. The device has a first electrode member, which has a first length and a first width. The device also has a second electrode member, which has a second length and a second width. Additionally, the device includes a capacitor dielectric material provided between the first electrode member and the second electrode member according to a specific embodiment. Depending upon the embodiment, the capacitor dielectric material is made of a suitable material or materials such as Al | 04-28-2011 |
| 20110090731 | GREEN TRANSISTOR FOR NANO-SI FERRO-ELECTRIC RAM AND METHOD OF OPERATING THE SAME - The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO | 04-21-2011 |
| 20110089479 | SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE - A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas. | 04-21-2011 |
| 20110084718 | Burn-In Testing System - The present invention discloses a burn-in testing system including a burn-in board and a burn-in testing apparatus, the burn-in board including: a first interface component, adapted to connect with the burn-in testing apparatus for signal input and/or output between the burn-in board and the burn-in testing apparatus; and a second interface component, adapted to connect with a device under test for signal input and/or output between the burn-in board and the device, wherein the burn-in testing system further includes a pin matching unit flexibly connected with the burn-in board and adapted to adjust signal connection relationship between the first interface component and the second interface component according to a pin description of the device. By using the invention, burn-in tests of various devices having the same number of pins and different pin descriptions can be performed using the same burn-in board, which is compatible with existing burn-in boards, thereby improving production efficiency and reducing production costs. | 04-14-2011 |
| 20110084327 | 3-D ELECTRICALLY PROGRAMMABLE AND ERASABLE SINGLE-TRANSISTOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate. | 04-14-2011 |
| 20110078647 | Design Method for Circuit Layout and Rapid Thermal Annealing Method for Semiconductor Apparatus - The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference. As compared with a traditional design method, the design method for circuit layout provided by the invention does not need adding dummy structure patterns, thereby avoiding negative influence to normal electric performance of the semiconductor apparatus by adding dummy structures. | 03-31-2011 |
| 20110074459 | STRUCTURE AND METHOD FOR SEMICONDUCTOR TESTING - An embodiment of a test structure in accordance with the present invention comprises a pair of interdigitated comb portions of a metallization layer present in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element. A third portion of the metallization layer comprises a serpentine metal line interposed between the comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (V | 03-31-2011 |
| 20110074036 | VIA CONTACT STRUCTURES AND METHODS FOR INTEGRATED CIRCUITS - A method for fabricating an integrated circuit device includes providing a semiconductor substrate having a first region and a second region, e.g., peripheral region. The method forms a stop layer overlying the first and second regions and a low k dielectric layer (e.g., k<2.9) overlying the stop layer in the first and second regions. The method forms a cap layer overlying the low k dielectric layer. In an embodiment, the method initiates formation of a plurality of via structures within a first portion of the low k dielectric layer overlying the first region and simultaneously initiates formation of an isolated via structure for in the second region of the semiconductor substrate, using one or more etching processes. The method includes ceasing formation of the plurality of via structures within the first portion and ceasing formation of the isolated via structure in the second region when one or more portions of stop layer have been exposed. | 03-31-2011 |
| 20110070711 | METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FROM CHLORIDE CHEMISTRIES FOR THE SEMICONDUCTOR INTEGRATED CIRCUITS - A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers. | 03-24-2011 |
| 20110070701 | INTEGRATION SCHEME FOR STRAINED SOURCE/DRAIN CMOS USING OXIDE HARD MASK - A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate, the first well region and the second well region, and forming a polysilicon gate layer (e.g., doped polysilicon) overlying the dielectric layer. The polysilicon gate layer is overlying a first channel region in the first well region and a second channel region in the second well region. The method includes forming a hard mask (e.g., silicon dioxide) overlying the polysilicon gate layer and patterning the polysilicon gate layer and the hard mask layer to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region. Next, the method separately forms strained regions in the first and second well regions. | 03-24-2011 |
| 20110070677 | SYSTEM AND METHOD FOR CMOS IMAGE SENSING - A method for forming a CMOS image sensing pixel, which is configured to determine a color, includes providing an n-type substrate that includes a first thickness and a first width. The method also includes forming a p-type layer, the p-type layer overlaying the n-type substrate. The p-type layer includes a second thickness and a second width. The second thickness and the second width are associated with a light characteristic. The method additionally includes forming an n-type layer, the n-type layer overlaying the p-type layer. The n-type layer includes a third thickness and a third width. In addition, the method includes forming a pn junction between the p-type layer and the n-type layer. The pn junction includes a fourth width. The method also includes providing a control circuit. The control circuit is electrically coupled to the n-type substrate. | 03-24-2011 |
| 20110069261 | METHOD AND RESULTING STRUCTURE USING SILVER FOR LCOS DEVICES - An LCOS device includes a semiconductor substrate and a plurality of MOS transistors that is formed on a portion of the semiconductor substrate. The LCOS device includes a first dielectric layer overlying the plurality of MOS transistors and a patterned metal layer overlying the first dielectric layer. The patterned metal layer exposes portions of the first dielectric layer that form borders surrounding the patterned metal layer, wherein the patterned metal layer includes a plurality of electrodes. The LCOS device further includes a second dielectric layer overlying the exposed portions of the first dielectric layer. In an embodiment, the patterned metal layer comprises a silver bearing material. Each of the plurality of electrodes has an upper surface having a surface roughness of less than 5 Angstrom and a surface reflectivity of greater than 97% for a light having a wavelength of 500 nanometers and greater. | 03-24-2011 |
| 20110069197 | SYSTEM AND METHOD FOR CMOS IMAGE SENSING - A system is provided for determining a color using a CMOS image sensor. The system includes an input port for receiving a user command. The system further includes an image sensor, an optical device that forms an image on the image sensor, and a processor. The image sensor includes an n-type substrate and a p-type epitaxy layer overlying the n-type substrate. The image sensor includes a control circuit that applies a first voltage on the n-type substrate to obtain a first output. The control circuit applies a second voltage on the n-type substrate to obtain a second output. The control circuit also applies a third voltage on the n-type substrate to obtain a third output. The p-type epitaxy layer includes a silicon germanium material. The image sensor additionally includes an epitaxy layer interposed between the n-type substrate and the p-type epitaxy layer. | 03-24-2011 |
| 20110066777 | WIRELESS MEMORY CARD AND METHOD THEREOF - A wireless memory card device includes a casing having a width, a length, and a thickness for supporting an integrated power supply. The device has one or more solar cell modules spatially disposed on a first portion of the casing. The device further includes a power supply control circuitry coupled to the one or more solar cell modules for providing regulated voltages to the device. In addition, the device includes a flash memory module provided in a second portion of the casing and a wireless communication module provided on a third portion of the casing. The device further includes one or more antennas coupled to the wireless communication module for transmitting and receiving data packets to and from a host system. The device additionally includes a power-on switch and an indicator signal for indicating the wireless data transfer between the device and the host system. | 03-17-2011 |
| 20110066270 | Rapid Thermal Annealing Method for a Semiconductor Device - The present invention discloses a rapid thermal annealing method for a semiconductor device, which includes the steps of: establishing a ternary correspondence relationship among a device electrical parameter, an annealing temperature, and an STI distribution density; deriving an STI distribution density in a specific area of the semiconductor device and a target STI distribution density; determining whether the STI distribution density in the specific area is larger than the target STI distribution density; if the STI distribution density in the specific area is larger than the target STI distribution density, adding a virtual structure in the specific area to make the STI distribution density in the specific area equal to the target STI distribution density; and deriving from the ternary correspondence relationship a target annealing temperature corresponding to the target STI distribution density and performing an annealing process with the annealing temperature on the semiconductor device to achieve a target electrical parameter. The method can alleviate the phenomenon of temperature non-uniformity of a rapid thermal annealing process so as to avoid any influence thereof upon the electrical performance of the semiconductor device. | 03-17-2011 |
| 20110065281 | METHOD OF RAPID THERMAL TREATMENT USING HIGH ENERGY ELECTROMAGNETIC RADIATION OF A SEMICONDUCTOR SUBSTRATE FOR FORMATION OF EPITAXIAL MATERIALS - A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second. | 03-17-2011 |
| 20110063924 | METHOD OF FLASH MEMORY DESIGN WITH DIFFERENTIAL CELL FOR BETTER ENDURANCE - A flash memory system includes a first flash memory cell having a first floating gate, a first source region, and a first control gate. The first control gate is connected to a word line. The first flash memory cell includes a first oxide layer separating the first control gate from the first floating gate and a first drain region connecting to a first bit line. The flash memory system also includes a second flash memory cell having a second floating gate, a second source region, and a second control gate. The second control gate is connected to the word line. The second flash memory cell includes a second oxide layer separating the second control gate from the second floating gate and a second drain region connecting to a second bit line. A comparator processes a first and second input signals received from the respective first and second bit lines. | 03-17-2011 |
| 20110063888 | Green Transistor for Resistive Random Access Memory and Method of Operating the Same - A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell. | 03-17-2011 |
| 20110062976 | Pad Structure and Test Method - The present invention discloses a pad structure and a method for testing a integrated circuit. The structure includes the first pads and the second pads, where the first pads are distributed over a peripheral portion of the integrated circuit and connected with lead-out wires of the integrated circuit, and the second pads are connected with a metal line at a circuit portion in the integrated circuit and are sized larger than the minimum characteristic dimension of the metal line and of the integrated circuit and smaller than the size of the first pads. The pad structure and method can position a test portion with improved efficiency. Correspondingly, a probe can be used to position the test portion with improved accuracy as well. | 03-17-2011 |
| 20110062551 | MULTILAYER OXIDE ON NITRIDE ON OXIDE STRUCTURE AND METHOD FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES - An integrated circuit device having a capacitor structure and methods of manufacture are disclosed. The device has a substrate, e.g., silicon wafer, silicon on insulator, epitaxial wafer. The device has a dielectric layer overlying the substrate and a polysilicon layer overlying the dielectric layer. The device has a tungsten silicide layer overlying the polysilicon layer and a first oxide layer overlying the tungsten silicide layer. A nitride layer overlies the oxide layer. A second oxide layer is overlying the nitride layer to form a sandwiched oxide on nitride on oxide structure to form a capacitor dielectric. The device also has an upper capacitor plate formed overlying the second oxide layer. | 03-17-2011 |
| 20110053349 | APPLICATION OF MILLISECOND HEATING SOURCE FOR SURFACE TREATMENT - A method for fabricating semiconductor devices, e.g., strained silicon MOS device, includes providing a semiconductor substrate (e.g., silicon wafer) having a surface region, which has one or more contaminants and an overlying oxide layer. The one or more contaminants is at least a carbon species. The method also includes processing the surface region using at least a wet process to selectively remove the oxide layer and expose the surface region. The method further includes subjecting the surface region to a laser treatment process for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants provided on the surface region. The method also includes removing the laser treatment process to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second. | 03-03-2011 |
| 20110051522 | METHOD OF PROGRAMMING FLASH MEMORY OF THE DIFFERENTIAL CELL STRUCTURES FOR BETTER ENDURANCE - A method of programming a differential flash memory cell having a first and a second memory cell is disclosed. The first memory cell includes a first transistor associated with a first threshold voltage and the second memory cell includes a second transistor associated with a second threshold voltage. The method includes reading the first and second memory cells to determine a current associated with the first and second threshold voltages. The first threshold voltage is equal to a first value and the second threshold voltage is equal to a second value. The method further includes determining if the first current corresponds to a predetermined logic state. If the current does not correspond to the predetermined logic state, the first and second memory cells are programmed. The programming includes changing the first threshold voltage from the first value to a third value and the second threshold voltage from the second value to a fourth value. | 03-03-2011 |
| 20110051496 | Resistive Random Access Memory and the Method of Operating the Same - A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density. | 03-03-2011 |
| 20110045661 | METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FOR SEMICONDUCTOR INTEGRATED CIRCUITS - A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers. | 02-24-2011 |
| 20110045649 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH Al2O3/NANO-CRYSTALLINE Si LAYER - A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure. | 02-24-2011 |
| 20110042732 | METHOD AND SYSTEM FOR CONTINUOUS LINE-TYPE LANDING POLYSILICON CONTACT (LPC) STRUCTURES - A method for making contact landing pad structures in a semiconductor integrated circuit device. The method includes forming an isolation region and forming active regions in the semiconductor substrate. The active regions are separated by the isolation region, and each of the active regions includes one or more contact regions. The method includes forming a raised structure between a first and second contact regions. The raised structure overlying the isolation region. The method includes depositing a cap layer and forming an interlayer dielectric layer overlying the cap layer. The method uses a mask pattern to selectively remove a portion of the photoresist layer to form a line type opening, which exposes a portion of the interlayer dielectric layer overlying at least the first and second contact regions. The method deposits a conductive fill material and performs a planarization process, whereby a plurality of conductive landing contact pads are formed. | 02-24-2011 |
| 20110037177 | DEVICE UNDER BONDING PAD USING SINGLE METALLIZATION - An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. Preferably, the angled cut region is within a periphery of the square shape of the at least one single metal bonding pad. A passivation layer having an opening is formed over the at least single metal bonding pad. The device has a buffer metal layer free region between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region is within an entirety of the interlayer dielectric layer. The passivation is substantially free from the buffer metal layer underlying the single metal bonding pad. | 02-17-2011 |
| 20110037130 | METHOD AND STRUCTURE FOR SELF ALIGNED CONTACT FOR INTEGRATED CIRCUITS - A high voltage integrated circuit device includes a semiconductor substrate having a surface region with a contact region, which is coupled to a source/drain region. The device has a plasma enhanced oxide overlying the surface region, a stop layer overlying the plasma enhanced oxide, and a contact opening through a portion of the stop layer and through a portion of the plasma enhanced oxide layer. The contact opening exposes a portion of the contact region without damaging it. The device has a silicide layer overlying the contact region to form a silicided contact region and an interlayer dielectric overlying the silicided contact region to fill the contact opening and provide a thickness of material overlying the stop layer. An opening in the interlayer dielectric layer is formed through a portion of the thickness to expose a portion of the silicided contact region and expose a portion of the stop layer. | 02-17-2011 |
| 20110034025 | Method for Forming Contact Hole Structure - The invention discloses a method for forming a contact hole structure, including: providing a substrate, the substrate having a surface where a metal layer is formed; forming on the surface of the substrate a dielectric layer covering the metal layer; etching the dielectric layer to form a contact hole exposing the metal layer; forming a barrier layer on sidewalls of the contact hole and an exposed surface of the metal layer; removing the barrier layer on the surface of the metal layer by sputtering, and performing sputtering on the metal layer; and, filling the contact hole with an electrically conductive material. The invention protects the dielectric layer from being damaged and improves the quality of the formation of the contact hole, and the sputtering performed on the metal layer and the subsequent filling of the contact hole with the electrically conductive material may use the same apparatus, which reduces processing steps and improves efficiency. | 02-10-2011 |
| 20110018608 | Bipolar Transistor, Band-Gap Reference Circuit and Virtual Ground Reference Circuit - The present invention provides a bipolar transistor, a method for forming the bipolar transistor, a method for turning on the bipolar transistor, and a band-gap reference circuit, virtual ground reference circuit and double band-gap reference circuit with the bipolar transistor. The bipolar transistor includes: a Silicon-On-Insulator wafer; a base area, an emitter area and a collector area; a base area gate dielectric layer on a top silicon layer and atop the base area; a base area control-gate on the base area gate dielectric layer; an emitter electrode connected to the emitter area via a first contact; a collector electrode connected to the collector area via a second contact; and a base area control-gate electrode connected to the base area control-gate via a third contact. Processes of forming the bipolar transistor are fully compatible with traditional standard CMOS processes; and the base current to turn on the bipolar transistor is based on the GIDL current and formed by applying a voltage to the base area control-gate electrode without any need of contact. | 01-27-2011 |
| 20110012613 | Failure Detection Method and Failure Detection Apparatus - The present invention discloses a failure detection method and a failure detection apparatus for detecting a defect in an electrical conductor. The failure detection method includes: providing at least two output terminals on the electrical conductor under test, the at least two output terminals having identical electric potentials; inputting a constant detection current sequentially to detection points arranged on the electrical conductor under test along a predetermined path; detecting an output current at one or more output terminals of the at least two output terminals; building a correspondence relationship between the detected one or more output currents at the one or more output terminals and positions of the detection points, based on information of the positions of the detection points and information of the detected one or more output currents at the one or more output terminals; and determining from the correspondence relationship whether the detection points have a defect. The failure detection method according to the invention can precisely locate defects; and uses a charged particle beam as the detection current source to avoid the size limitation of irradiation points, thereby satisfying the requirement for failure analysis in a small size. | 01-20-2011 |
| 20110000509 | PHOTORESIST TOOL CLEANING JIG CONFIGURED TO RECEIVE FLOW FROM TOP AND BOTTOM - A cup wash disk jig employed to clean photoresist from a spin-on chamber, receives cleaning solvent from both the bottom and the top, enhancing cleaning effectiveness. The cup wash disk includes a first set of channels allowing fluid communication between a hole positioned in a top surface of the cup wash disk jig, and a plurality of orifices distributed about the edge of the jig. Solvent is applied to the top surface of the jig, for example from an existing reduce resist control (RRC) nozzle normally utilized to dispense resist material. The solvent is flowed through these channels and ejected from the disk sides through the orifice, thereby facilitating removal of resist residue from coater cup portions of the chamber. Solvent may also be applied to an opening in a bottom surface of the jig, for example from a back rinse nozzle, to flow through a second set of channels and be ejected through different jig edge orifices. | 01-06-2011 |
| 20100316958 | METHOD AND SYSTEM FOR CALIBRATING EXPOSURE SYSTEM FOR MANUFACTURING OF INTEGRATED CIRCUITS - Method and system for calibrating exposure system for manufacturing of integrated circuits. According to an embodiment, the present invention provides a method for determining one or more focus parameters for an exposure system. As an example, the exposure system is used for forming patterns on semiconductor wafer. The method includes a step for providing a semiconductor wafer. The semiconductor wafer is characterized by a diameter. The method also includes a step for forming a plurality of patterns using the exposure system on the semiconductor wafer. As an example, each of the plurality of patterns being associated with a focus reference value (e.g., focus distance, focus angle, etc.). The method additionally includes a step for determining a plurality of shift profiles, and each of the shift profile is associated one of the plurality of patterns. | 12-16-2010 |
| 20100276745 | ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF - A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region. | 11-04-2010 |
| 20100248468 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 09-30-2010 |
| 20100233594 | SYSTEM AND METHOD FOR QUALITY ASSURANCE FOR RETICLES USED IN MANUFACTURING OF INTEGRATED CIRCUITS - System and method for quality assurance for reticles used in manufacturing of integrated circuits. According to an embodiment, the present invention provides a method for inspecting one or more blanks For example, the blanks are prepared to be used as reticles for manufacturing of integrated circuits. The method includes a step for providing a blank. For example, the blank includes an unknown level of impure particles. The method also includes a step for subjecting the blank to radiation at a first radiation level. The method additionally includes a step for receiving reflected radiation by the radiation source. Also, the method includes a step for determining a particle level based on at least the reflected radiation. Additionally, the method includes a step for determining whether to use the blank to produce a reticle. | 09-16-2010 |
| 20100227465 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method forms at least one dielectric spacer within the first recessed region and at least one dielectric spacer within the second recessed region to form a resulting surface region, and subjects the resulting surface region to a chemical mechanical polishing process to cause formation of a substantially planarized second polysilicon layer free from the dielectric material. | 09-09-2010 |
| 20100227464 | METHOD AND STRUCTURE FOIR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 09-09-2010 |
| 20100197066 | METHOD OF INTERCONNECT FOR IMAGE SENSOR - A method for fabricating CMOS image sensor device, the method includes providing a semiconductor substrate having a P type impurity characteristic. The semiconductor substrate includes a surface region. The method forms a first dielectric layer having a first thickness overlying a first region of the semiconductor substrate. The method includes providing a N type impurity region in a portion of the semiconductor substrate underneath the first dielectric layer to cause formation of a photodiode device region characterized by at least the N type impurity region and the P type substrate. A second dielectric layer having a second thickness is formed in a second region of the surface region. The second dielectric layer is formed within a portion of the first region within the first thickness of the first dielectric layer. The method forms a polysilicon gate layer overlying at least the second region to form a contact member coupled to the second region. | 08-05-2010 |
| 20100190329 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 07-29-2010 |
| 20100189196 | AMPLITUDE SHIFT KEYED (ASK) DEMODULATION PATTERN AND USE IN RADIO FREQUENCY IDENTIFICATION (RFID) - A demodulation circuit for an Amplitude Shift Keyed (ASK) modulated signal includes an envelope detector, an alternating voltage amplifier, a differentiator circuit, and a comparator having a hysteresis connected in series. The envelope detector produces an envelope signal from the received ASK signal. The amplifier blocks the DC component of the envelope signal and amplifies AC components of the envelope signal to obtain a steeper slope of the rising and falling edges. The differentiator circuit then processes the transition edges to provide a differentiated signal having positive and negative electrical pulses. The comparator converts the pulses into a binary data stream which corresponds to the transmitted data stream. The combination of the differentiated signal and comparator having a hysteresis enables better stability and sensitivity of the ASK demodulation circuit. | 07-29-2010 |
| 20100182177 | METHOD AND SYSTEM FOR ANALOG-TO-DIGITAL CONVERSION - Method and system for analog-to-digital conversion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a different operational amplifier, which includes a first output, a second output, a first input, and a second input. The operational amplifier is associated with an amplification factor. The integrated circuit also includes a first voltage input. The first voltage input can be characterized by a first voltage. Additionally, the integrated circuit includes a second voltage input. The second voltage input can be characterized by a second voltage. Furthermore, the integrated circuit includes a first voltage source configured to provide a first reference voltage. In addition, the integrated circuit includes a second voltage source configured to provide a second reference voltage. Furthermore, the integrated circuit includes a first capacitor being electrically coupled to the first input and disengageably coupled to the first voltage input. | 07-22-2010 |
| 20100171186 | SYSTEM AND METHOD FOR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion. The FET also includes a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type. A first drain portion is positioned within second portion and characterized by the second conductivity type and a first doping concentration. A second drain portion is positioned within the second portion and is characterized by the second conductivity type and a second doping concentration, the second doping concentration being different from the first doping concentration. | 07-08-2010 |
| 20100169852 | SYSTEM AND METHOD FOR DETECTING ONE OR MORE WINDING PATHS FOR PATTERNS ON A RETICLE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS - A system and method for detecting one or more winding paths for patterns on a reticle for the manufacture of semiconductor integrated circuits. A method for detecting invalid winding path in a layout design. The method includes the step of obtaining a first winding path parameter and a second winding path parameter. The method includes defining a first plurality of reticle patterns in accordance with the first winding path parameter and the second winding path parameter. The first winding path parameter has a first value. The first plurality of reticle patterns is associated with the least one winding path. The method additionally includes defining a second plurality of reticle patterns in accordance with the second winding path parameter and the second winding path parameter. The first winding path parameter has a second value. The second plurality of reticle patterns is associated with the at least one winding path. Moreover, the method includes comparing the first plurality of reticle patterns against the second plurality of reticle patterns. | 07-01-2010 |
| 20100167428 | METHOD AND SYSTEM FOR DETERMINING SEMICONDUCTOR CHARACTERISTICS - Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one opening within the substrate material. The opening can be characterized by an opening characteristic that includes a depth and an opening width associated with an unknown volume. The method includes a step for providing fill material. Additionally, the method includes a step for processing the fill material to cause a first portion of the fill material to enter the opening and occupy an entirety of the unknown volume associated with the opening characteristic while a second portion of the fill material remains outside of the unknown volume. Moreover, the method includes a step for processing the second portion of the fill material using one or more processes to determine a spatial characteristic associated with the unknown volume. | 07-01-2010 |
| 20100165165 | METHOD AND DEVICE FOR A CMOS IMAGE SENSOR - A method for determining photocurrents corresponding to a plurality of wavelength ranges. The method includes receiving at least a light by a photodiode within a first wavelength range. The first wavelength range includes a second wavelength range and a third wavelength range. The method provides a first bias voltage to the photodiode and determines a first photocurrent within the first wavelength range, the first photocurrent being associated with the photodiode and the first bias voltage. The method also provides a second bias voltage to the photodiode, different from the first bias voltage, and determines a second photocurrent within the first wavelength range, the second photocurrent being associated with the photodiode and the second bias voltage. The method further includes processing information associated with the first and second photocurrents, and determining at least a third photocurrent corresponding to the second wavelength range and a fourth photocurrent corresponding to the third wavelength range. | 07-01-2010 |
| 20100164600 | NOVEL CHARGE PUMP - A charge pump circuit includes a first voltage supply circuit configured to provide a first supply voltage in response to a first and second input signals. A first capacitor is coupled to the first voltage supply circuit. A first switch circuit is configured to provide a second supply voltage to a second terminal of the first capacitor in response to a first control signal. A second switch circuit is coupled to the second terminal of the first capacitor. A second capacitor is coupled to the second switch circuit. The second switch circuit is configured to cause charge transfer from the first capacitor to the second capacitor in response to a second control signal. The charge pump also includes an output terminal coupled to the second capacitor to provide an output voltage, the output voltage being higher than the first supply voltage, the output voltage being also higher than the second supply voltage. | 07-01-2010 |
| 20100164508 | SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER - System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing a chip. For example, the test structure and the chip are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the chip. For example, the top structure can be characterized by a first surface area. The top structure includes a first metal material occupying less than 60% of the surface area. The test structure also includes a bottom structure positioned below the chip. For example, the bottom structure can be characterized by a second surface area. The second surface area is substantially equal to the first surface area. The bottom structure includes a first silicon material. The first silicon material occupies substantially all of the second surface area. | 07-01-2010 |
| 20100153622 | Data Access Controller and Data Accessing Method - A data access controller and data accessing method is provided. The data access controller includes: a flash memory configuration register unit for storing information used for data access in a flash memory; a flash memory control unit for generating a control signal for data access to a block and a page in the flash memory according to the information used for data access stored in the flash memory configuration register unit; and a temporary memory control unit under the control of the flash memory control unit, adapted to generate a control signal for temporary storage of data. In the inventive solution, data access in the flash memory is under the control of the data access controller, thereby reducing CPU workload, improving operation speed and generality of the control on the data access in flash memory by storing the information for data access for at least one type of flash memory. | 06-17-2010 |
| 20100133702 | METHOD FOR ELIMINATING LOADING EFFECT USING A VIA PLUG - Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is characterized by a first thickness. The method also includes a stop for forming an inter metal dielectric layer overlaying the substrate. The inter metal dielectric layer is characterized by a second thickness. The method additionally includes a step for forming a first photoresist layer overlaying the inter metal dielectric layer. The first photoresist layer is associated with a first pattern. Additionally, the method includes a step for forming a first opening positioned at least partially inside the inter metal dielectric layer. The first via opening is characterized by a first depth. The method additionally includes a step for removing the first photoresist layer. The method further includes a step for forming a via plug. | 06-03-2010 |
| 20100129740 | Method for Collecting Optical Proximity Correction Parameter - This invention relates to a method for collecting an Optical Proximity Correction parameter, which includes: performing an Optical Proximity Correction for a test line containing a non-right turning-angle to generate a to-be-exposed pattern having an assistant line; obtaining, by way of simulation or actual exposure, a formed line generated from the to-be-exposed pattern being exposed; and comparing the formed line with the test line to determine a difference there between so as to determine whether there is a redundant part and/or a missing part in the assistant line at location of the turning-angle of the test line. Being compared with the prior art, this invention sets the non-right turning-angle in the to-be-exposed test line. By comparing the formed line (which is generated by simulation or actual exposure) of the above test line with the test line itself, the redundant part and/or the missing part of the assistant line, as well as proximity data such as the position of the redundant part and/or the missing part and the like, can be obtained. Then, these proximity data can be used to correct and perfect the OPC model having a line containing a non-right turning-angle. | 05-27-2010 |
| 20100123609 | Parallel to Serial Conversion Circuit - A parallel to serial conversion circuit includes a plurality of switching units and a voltage output unit providing an operating voltage for the switching units. Each of the plurality of switching units is operable to receive a first clock signal and a second clock signal which have the same frequency, a phase shift exists between the first clock signal and the second clock signal for each of the switching units, and a phase difference exists between the first clock signals received by adjacent two switching units of the plurality of switching units. The plurality of switching units receive data bits of parallel data in sequence according to the phase difference, particularly, each of the plurality of switching units receives one data bit within a time window corresponding to the phase shift. In comparison with the prior art, the inventive solution implement the parallel to serial conversion using a single system clock frequency, so that the complexity and power consumption of the system is reduced. | 05-20-2010 |
| 20100123179 | Two-Step Self-Aligned Source Etch With Large Process Window - System and method for self-aligned etching. According to an embodiment, the present invention provides a method for performing self-aligned source etching process. The method includes a step for providing a substrate material. The method also includes a step for forming a layer of etchable oxide material overlying at least a portion of the substrate material. The layer of etchable oxide material can characterized by a first thickness. The layer of etchable oxide material includes a first portion, a second portion, and a third portion. The second portion is positioned between the first portion and the third portion. The method additionally includes a step for forming a plurality of structures overlying the layer of etchable oxide material. The plurality of structures includes a first structure and a second structure. | 05-20-2010 |
| 20100106869 | USB Storage Device and Interface Circuit Thereof - A USB storage device and an interface circuit thereof are disclosed. The interface circuit of the USB storage device includes an out transaction execution unit, which controls a speed status of the out transaction according to a speed status mark recorded in the speed status register, and therefore it is not necessary to provide a control unit for each of the high-speed out transaction and the full-speed out transaction, so that the area of the interface circuit is reduced, thereby reducing the area of the USB storage device. | 04-29-2010 |
| 20100103759 | POWER LINE DECODING METHOD FOR AN MEMORY ARRAY - A method for selectively providing power supply voltage to a memory device. The method provides an integrated circuit memory device including a first plurality of memory cells. Each memory cell includes a power terminal and a ground terminal. The method includes selecting a second plurality of memory cells from the first plurality of memory cells. The method provides a first power voltage to the power terminal of each of the selected memory cells and a second power voltage to the power terminal of each of the unselected memory cells. The second power voltage is lower than the first power voltage. In an embodiment, the method applies a first ground voltage to the ground terminal of each of the selected memory cells and applies a second ground voltage to the ground terminal of each of the unselected memory cells. The second ground voltage is higher than the first ground voltage. | 04-29-2010 |
| 20100087040 | Method for Making Split Dual Gate Field Effect Transistor - A method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface. | 04-08-2010 |
| 20100072481 | Method and Resulting Structure Using Silver for LCOS Devices - A method for fabricating an LCOS device. The method includes providing a semiconductor substrate and forming a plurality of MOS transistor devices formed on a portion of the semiconductor substrate. The method includes forming a first dielectric layer overlying the plurality of transistor devices and forming a first metal layer overlying the first dielectric layer. The method includes forming a second dielectric layer overlying the first metal layer and forming a plurality of pixel regions made substantially of silver bearing material overlying the second dielectric layer. In a preferred embodiment, the silver bearing material has much higher reflectivity for wavelengths of 450 nanometers and greater. | 03-25-2010 |
| 20100059824 | SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS FABRICATED BY PROCESSES FOR MAKING CORE TRANSISTORS - A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers; | 03-11-2010 |
| 20100039167 | Charge Pump Circuit - A charge pump circuit includes a switch unit adapted to transmit charges from the input of the charge pump to the output of the charge pump; a transmission unit adapted to control turn-on or cut-off of an MOS transistor in the switch unit; and a charging unit in one-to-one correspondence with a PMOS transistor in the switch unit and adapted to store charges to boost the transmission voltage. The embodiment of the invention adopts a first NMOS transistor and at least one PMOS transistor as the switch unit during transmission of the charges, so that normal work can be enabled with high transmission efficiency in the case of a low source voltage. | 02-18-2010 |
| 20100039151 | Phase Locked Loop, Lock Detector and Lock Detection Method - The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval. The PLL, lock detector thereof and lock detection method can detect the lock state quickly and correctly. | 02-18-2010 |
| 20100037952 | Selective Emitter Solar Cell and Fabrication Method Thereof - A fabrication method of a selective emitter solar cell, including: forming a selective emitter solar cell base having a buried grid electrode; forming an anti-reflection layer on the emitter surface of the solar cell base; forming a bus-bar on the anti-reflection layer; and connecting the buried grid electrode with the bus-bar in the traversing direction underneath through the anti-reflection layer. Accordingly, the invention provides a selective emitter solar cell. With the method of the invention, emitters and bus-bars are made separately, the width of the emitters can be reduced according to actual needs, the area that is unnecessarily taken may be reduced, the effective area for a solar cell panel to receive sunlight may be increased. The invention improves conversion efficiency of a selective emitter solar cell panel from 16.5% to 18% or more. | 02-18-2010 |
| 20100029090 | NOVEL CONTACT ETCH STOP FILM - A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface region. The partially completed integrated circuit device also includes an etch stop layer overlying the surface region. The etch stop layer is characterized by a thickness having at least a first thickness portion and a second thickness portion. The second thickness portion includes an etch stop surface region. The partially completed integrated circuit device additionally includes a silicon dioxide material provided within the first thickness portion of the etch stop layer. The partially completed integrated circuit device includes a silicon nitride material provided within the second thickness portion of the etch stop layer. In addition, the partially completed integrated circuit device includes a profile characterized by the silicon dioxide material in the first thickness portion changing to the silicon nitride material in the second thickness portion. | 02-04-2010 |
| 20100027172 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) DEVICE - A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage. | 02-04-2010 |
| 20100025686 | SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MONOS MEMORY CELL STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally. | 02-04-2010 |
| 20100019308 | ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF - An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region. | 01-28-2010 |
| 20100015745 | METHOD AND STRUCTURE FOR A CMOS IMAGE SENSOR USING A TRIPLE GATE PROCESS - A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method form a first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate. | 01-21-2010 |
| 20100013100 | Method and System for Forming Conductive Bumping with Copper Interconnection - An integrated circuit system with one or more copper interconnects is provided. The one or more copper interconnects are in conductive contact with a substrate. The integrated circuit system includes a first dielectric layer, a copper material filling a first via through the first dielectric layer, a second dielectric layer in contact with the first dielectric layer, and a diffusion barrier layer. The diffusion barrier layer at least partially fills a second via through the second dielectric layer. At least a first part of the diffusion barrier layer is in direct contact with the copper material, and at least a second part of the diffusion barrier layer is in direct contact with the second dielectric layer. The integrated circuit system further includes a gold material at least partially filling the second via. The gold material is conductively connected with the copper material through the diffusion barrier layer and conductively connected with a substrate. Additionally, a method for making such an integrated circuit system with one or more copper interconnects is provided. | 01-21-2010 |
| 20100009528 | Method for Rapid Thermal Treatment Using High Energy Electromagnetic Radiation of a Semiconductor Substrate for Formation of Dielectric Films - A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections. In a specific embodiment, the oxide layer is a gate oxide layer. | 01-14-2010 |
| 20100009487 | ONO Spacer Etch Process to Reduce Dark Current - A method of forming a CMOS image sensor device. The method includes providing a semiconductor substrate having a P-type impurity characteristic. The semiconductor substrate includes a surface region. The method includes forming a gate oxide layer overlying the surface region and forming a first gate structure overlying a first portion of the gate oxide layer, the first gate structure has a top surface region and at least a side region. The method forms an N-type impurity region in a portion of the semiconductor substrate to form a photodiode device region from the N-type impurity region and the P-type impurity. The method includes forming a blanket spacer layer including an oxide on nitride on oxide structure overlying at least the first gate structure; and forming one or more spacer structures using the blanket spacer layer for the first gate structure while maintaining a portion of the oxide layer from the oxide on nitride on oxide overlying at least the photo-diode device region | 01-14-2010 |
| 20100007869 | Reticle Handler - The present invention provides an apparatus and method for handling a reticle during manufacturing processes of semiconductor devices in the fabrication line. The apparatus includes a holder for the reticle, the holder is configured to securely hold the reticle and a level indicator attached to and operative with the holder to indicate leveling condition of the holder. The apparatus further includes a shaft connected to the holder for holding and a switch connected to the shaft. The method includes providing a reticle and clamping the reticle with a reticle holder including a switch and a leveling indicator operative with the holder to indicate leveling condition of the holder. The method further includes loading the reticle into a reticle pod while maintaining the leveling condition of the holder. | 01-14-2010 |
| 20100006975 | METHOD OF ELIMINATING MICRO-TRENCHES DURING SPACER ETCH - A method of forming a semiconductor structure is provided. The method includes providing a semiconductor substrate with a substrate region. The method also includes forming a pad oxide layer overlying the substrate region. The method additionally includes forming a stop layer overlying the pad oxide layer. Furthermore, the method includes patterning the stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a height. Also, the method includes depositing alternating layers of oxide and silicon nitride to at least fill the trench, the oxide being deposited by an HDP-CVD process. The method additionally includes performing a planarization process to remove a portion of the silicon nitride and oxide layers. In addition, the method includes removing the pad oxide and stop layers. | 01-14-2010 |
| 20100006754 | METHOD FOR TREATMENT OF SAMPLES FOR TRANSMISSION ELECTRONIC MICROSCOPES - A method for analyzing a sample for the manufacture of integrated circuits, e.g., dynamic random access memory device, commonly called, DRAMS. The method also provides an integrated chip including a thickness, a width, and a length. In a specific embodiment, the integrated chip has at least one elongated structure through a portion of the thickness, while being normal to the width and the length. In a specific embodiment, the elongated structure has a structure width and a structure length that extends through a vertical portion of the thickness. The method includes removing a slice of the integrated circuit chip from a portion of the thickness in a directional manner normal to the structure length. In a specific embodiment, the slice is provided through an entirety of the one elongated structure along the structure length to cause a portion of a thickness of the slice providing the elongated structure to be of a substantially uniform sample thickness. The method also includes capturing one or more images through a portion of the slice using a transmission electron | 01-14-2010 |
| 20100004775 | METHOD AND SYSTEM FOR DEFECT DETECTION IN MANUFACTURING INTEGRATED CIRCUITS - Method and system for defect detection in manufacturing integrated circuits. In an embodiment, the invention provides a method for identifying one or more sources for possible causing manufacturing detects in integrated circuits. The method includes a step for providing a plurality of semiconductor substrates. The method includes a step for processing the plurality of semiconductor substrates in a plurality of processing steps using a plurality of processing tools. The method additionally includes a step for providing a database, which includes data associated with the processing of the plurality of semiconductor substrates. The method further includes a step for testing the plurality of semiconductor wafers after the processing of the plurality of semiconductor substrates. Additionally, the method includes a step for detecting at least one defect characteristic associated with the plurality of the semiconductor substrates that have been processed. Moreover, the method includes a step for identifying a set of processing steps. For example, the set of processing step are possibly associated with the defect characteristic. | 01-07-2010 |
| 20100003799 | METHOD FOR FORMING P-TYPE LIGHTLY DOPED DRAIN REGION USING GERMANIUM PRE-AMORPHOUS TREATMENT - A method for forming a MOS device with an ultra shallow lightly doped diffusion region. The method includes providing a semiconductor substrate including a surface region. The method provides a gate dielectric layer overlying the surface region and forms a gate structure overlying a portion of the gate dielectric layer. The method includes performing a first implant process using a germanium species to form an amorphous region within a lightly doped drain region in the semiconductor substrate using the gate structure as a mask. In a specific embodiment, the method includes performing a second implant process in the lightly doped drain region using a P type impurity and a carbon species using the gate structure as a mask. The method includes performing a first thermal process to activate the P type impurity in the lightly doped drain region. The method includes forming side wall spacers overlying a portion of the gate structure and performing a third implant process using a first impurity to form active source/drain regions in a vicinity of the surface region of the semiconductor substrate adjacent to the gate structure using the gate structure and the side wall spacer as a masking layer. The method then performs a second thermal process to activate the first impurity in the active source/drain regions. | 01-07-2010 |
| 20100003794 | METHOD FOR DEFECT REDUCTION FOR MEMORY CELL CAPACITORS - A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a rugged polysilicon layer are formed overlying the exposed storage nodes. The memory cell region is masked, exposing a peripheral region. A chemical dry etch process removes the rugged polysilicon and the polysilicon layers in the peripheral region. The rugged polysilicon and the polysilicon layers are planarized followed by a dielectric recess. The resulting cylindrical stack capacitor structures are substantially free of defects from rugged polysilicon remaining in the peripheral region thereby improving device yield and process window. | 01-07-2010 |
| 20100001738 | System and Method for Conducting Accelerated Soft Error Rate Testing - An apparatus for a user to conduct an accelerated soft error test (ASER) on a semiconductor sample is provided. The apparatus comprises a first component for holding the radiation source, where the radiation source may be either an alpha-particle or neutron-particle source. The apparatus comprises a second component for holding the semiconductor sample, where the semiconductor sample may be either a silicon wafer or semiconductor chip. The apparatus comprises a connecting assembly for placing the first component and the second component relative to each other at a plurality of positions that subject the semiconductor sample to a radiation stress from the radiation source at a plurality of stress efficiencies. Among the benefits provided are improved repeatability and credibility of ASER tests and reduced radiation exposures to operators of ASER tests. | 01-07-2010 |
| 20100001367 | Method and Resulting Structure DRAM Cell with Selected Inverse Narrow Width Effect - A shallow trench isolation structure for integrated circuits. The structure includes a semiconductor substrate and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed around a perimeter of the trench region. A trench region is formed within the semiconductor substrate. The trench region has a bottom width of less than 0.13 microns and an upper width of less than 0.13 microns. A rounded edge region is within a portion of the semiconductor substrate surrounding a periphery of the trench region. The rounded edges have a radius of curvature greater than about 0.02 um. A planarized high density plasma fill material is formed within the trench region. The structure has a P-well region within the semiconductor substrate and bordering a vicinity of the trench region. A channel region is within the P-well region within the semiconductor substrate. The implanted region has a concentration of more than double an amount of impurities as impurities in the channel region. | 01-07-2010 |
| 20100001354 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon. The method diffuses the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region. The method selectively removes the capping layer overlying the gate structure. The method then forms a silicide layer overlying the gate structure and surface of the contact polysilicon, whereupon the sidewall spacers isolate the silicide layer on the gate structure from the silicide layer on the contact polysilicon. | 01-07-2010 |
| 20100001353 | SANOS Memory Cell Structure - A semiconductor device having a silicon-aluminum oxide-nitride-oxide-semiconductor (SANOS) memory cell structure is provided. The device includes a silicon substrate including a surface, a source region and a drain region in the surface. The drain region and the source region are separate from each other. The device further includes a confined dielectric structure on the surface and between the source region and the drain region. The confined dielectric structure includes sequentially a silicon oxide layer, a silicon nitride layer, and an aluminum oxide layer. Additionally, the device includes a gate region overlying the aluminum oxide layer. In a specific embodiment, the gate region is made from patterning an amorphous silicon layer. In another specific embodiment, the gate region includes a polysilicon layer. In an alternative embodiment, a method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally or embedded for system-on-chip applications. | 01-07-2010 |
| 20100001334 | ATOMIC LAYER DEPOSITION EPITAXIAL SILICON GROWTH FOR TFT FLASH MEMORY CELL - A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH | 01-07-2010 |
| 20100001282 | TFT FLOATING GATE MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 01-07-2010 |
| 20100001281 | TFT SAS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 01-07-2010 |
| 20100001280 | TFT MONOS OR SONOS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 01-07-2010 |
| 20100001271 | SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MAS MEMORY CELL STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally. | 01-07-2010 |
| 20100001270 | AMORPHOUS SILICON MONOS OR MAS MEMORY CELL STRUCTURE WITH OTP FUNCTION - A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally. | 01-07-2010 |
| 20090325080 | Method and Structure for Fabricating Dark-Periphery Mask for the Manufacture of Semicondutor Wafers - A method for manufacturing an integrated circuit devices. The method includes providing a substrate, which includes an opaque film overlying the substrate, an overlying negative photoresist layer, a stop layer overlying the negative photoresist layer, and a positive photoresist layer overlying the stop layer. The method includes patterning the positive resist layer to form one or more window openings in the positive photoresist layer. The method also includes removing the exposed stop layer within the one or more window openings to expose a portion of the negative photoresist layer and patterning the exposed portion of the negative photoresist layer. The method includes developing the exposed portion of the negative photoresist layer and removing exposed portions of the opaque layer to expose an underlying portion of the substrate. The method further includes removing any remaining portions of the negative photoresist layer, stop layer, and positive photoresist layer to provide a patterned mask. The patterned mask is used for a manufacture of integrated circuits. | 12-31-2009 |
| 20090305440 | Method for Treatment of Samples for Auger Electronic Spectrometer (AES) in the Manufacture of Integrated Circuits - A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis. | 12-10-2009 |
| 20090294875 | Metal Oxide Semiconductor Device and Method for Manufacturing the Same - A Metal Oxide Semiconductor device includes a semiconductor substrate; a gate electrode formed on the surface of the substrate, having an offset spacer on each side; source/drain electrodes in the substrate having lightly doped regions respectively; metal silicide located on the gate electrode and the source/drain electrodes; and first impurity ions and second impurity ions in the lightly doped regions. A method for manufacturing a Metal Oxide Semiconductor device includes forming a gate electrode on a semiconductor substrate; implanting first impurity ions and second impurity ions to form lightly doped regions; depositing a dielectric layer and etching the dielectric layer to form offset spacers; implanting the first impurity ions to form the source/drain electrodes; forming metal silicide on the surfaces of the gate electrode and the source/drain regions. This invention can effectively prevent metal nickel diffusion into the lightly doped regions. | 12-03-2009 |
| 20090291550 | POLY GATE ETCH METHOD AND DEVICE FOR SONOS-BASED FLASH MEMORY - A method for forming flash memory devices is provided. The method includes providing a semiconductor substrate, which comprises a silicon material and has a periphery region and a cell region. The method further includes forming an isolation structure between the cell region and the periphery region. Additionally, the method includes forming an ONO layer overlying the cell region and the periphery region. Furthermore, the method includes removing the ONO layer overlying the periphery region to expose silicon material in the periphery region. The method also includes forming a gate dielectric layer overlying the periphery region, while protecting the ONO layer in the cell region. In addition, the method includes forming a polysilicon layer overlying the cell region and the periphery region. | 11-26-2009 |
| 20090289726 | Self-Biased Phase Locked Loop - A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator. | 11-26-2009 |
| 20090289725 | Self-Biased Phase Locked Loop - The present invention discloses a self-bias PLL including a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a divider and a bias current converter. A charging or discharging current output from the charge pump equals to a first control current. A resistor of the loop filter is controlled by a first control voltage a second control voltage which is adjusted according to the first control voltage and a second control current. The loop filter increases or decreases the first control voltage according to the charging or discharging current output from the charge pump. The voltage control oscillator generates a bias current and an oscillation voltage according to the first control voltage and increases or decreases an oscillation frequency according to the increase or decrease of the oscillation voltage. The circuit structure of the self-bias PLL is simple and the self-bias PLL has a low jitter. | 11-26-2009 |
| 20090289337 | Lead Frame - A lead frame comprises a die pad and leads arranged around the die pad. Through holes are provided in the die pad, and the through holes are located in the peripheries, i.e., margin area of the die pad. The through holes serve to be passed through by the metal wires connected with the leads. By means of the above-described lead frame, the subsequent packaging process of the semiconductor chip; including dual chips and/or multi-chips assembly, is simplified and the effect of the manufacturing process is improved, at the same time, the manufacturing cost is reduced. | 11-26-2009 |
| 20090280653 | METHOD FOR FORMING LOW DIELECTRIC CONSTANT FLUORINE-DOPED LAYERS - A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3. | 11-12-2009 |
| 20090273881 | Metal-Insulator-Metal Capacitor - The present invention provides a metal-insulator-metal capacitor, which comprises a semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; and an insulation trench and two metal trenches all running through the interlayer dielectric layer and allowing the semiconductor substrate to be exposed; wherein the metal trenches being located on each side of the insulation trench and sharing a trench wall with the insulation trench respectively, the insulation trench being filled with insulation material as an insulation structure, the metal trenches being filled with metal material as electrodes of the capacitor. | 11-05-2009 |
| 20090273379 | Self-Biased Phase Locked Loop and Phase Locking Method - The present invention discloses a self-bias phase locked loop including a phase frequency detector, a charge pump, a loop filter, a voltage control oscillator, a divider and a bias current converter. A charging or discharging current output from the charge pump equals to a first control current. A resistor of the loop filter is controlled by a first control voltage a second control voltage which is adjusted according to the first control voltage and a second control current. The loop filter boosts or lowers the first control voltage according to the charging or discharging current output from the charge pump. The voltage control oscillator generates a bias current according to the first control voltage and increases or decreases an oscillation frequency according to the boosted or lowered first control voltage, and symmetric loads of the voltage control oscillator are controlled by the first control voltage. The first control current output from the bias current converter equals to the ratio of the bias current to a constant, and the second control current output from the bias current converter equals to the ratio of the bias current to a frequency division factor. The circuit of the self-bias phase locked loop is simple and a low jitter. | 11-05-2009 |
| 20090273020 | SONOS Flash Memory - A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, comprising: preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easy to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching. Thus, no polysilicon residue will be formed on the sidewall of the dielectric layer. Thereby, the short circuit between different memory cells may be avoided. | 11-05-2009 |
| 20090269865 | Method for PMOS Device Processing Using a Polysilicon Footing Characteristic to Achieve Low Leakage - A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate. | 10-29-2009 |
| 20090216470 | Method and Computer Code for Statistical Process Control for Censored Production Data - A method for monitoring device characteristics of semiconductor integrated circuits. The device characteristics includes censored data and uncensored data. The method includes determining a plurality of minimum breakdown voltages numbered from 1 through N, respectively, for a plurality of lots (e.g., wafer fabrication lots) numbered from 1 through N. Each of the plurality of minimum breakdown voltages is respectively indicative of the plurality of samples through order statistics. One or more of the plurality of samples includes one or more uncensored data points and one or more censored data points. The method includes processing the minimum breakdown voltages, respectively, for the plurality of lots. Each of the minimum breakdown voltages is processed for the respective plurality of lots and is indicative of a population characteristic breakdown voltage numbered from 1 through N for the respective lot numbered from 1 through N. The method includes determining one or more anomalies based upon the processing of the minimum breakdown voltages. The one or more anomalies is associated with one or more processes associated with at least one of the lots. | 08-27-2009 |
| 20090212823 | Low Jitter CMOS to CML Converter - The present invention provides a low jitter CMOS to CML converter, including: a differential circuit including differential pair transistors, a pair of loads and a biased transistor, each differential transistor of the differential pair transistors having an input terminal, an output terminal and a connection terminal. With the current compensation device, an additional current path may be provided for the current of the biased transistor which is used as a constant current source when the differential transistors are turned off, so that the peak tail current in the biased transistor current may be eliminated. Thus, the problem caused by the tail current that the common mode output voltages of the converter is unstable and has a high jitter may be solved. | 08-27-2009 |
| 20090212783 | BGA Package Holder Device and Method for Testing of BGA Packages - An apparatus for supporting BGA packages for one or more testing processes is disclosed. The apparatus includes a substrate member. The substrate member has a plurality of contact pads, with each of the contact pads being spatially disposed around a peripheral region of the substrate. The apparatus further includes a plurality of contact regions spatially configured on a portion of the substrate member. Each of the plurality of contact regions is numbered from 1 through N being electrically connected to respective contact pads numbered from 1 through N. The plurality of contact regions is configured to provide electrical contact to respective plurality of balls provided on a BGA package. The apparatus additionally includes a holder device coupled to the substrate member. The holder device is adapted to mechanically hold the BGA package in place to provide mechanical contact between the plurality of balls and respective plurality of contact regions. | 08-27-2009 |
| 20090200564 | Method and Structure for Fabricating Smooth Mirrors for Liquid Crystal on Silicon Devices - A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g., BPSG, FSG) overlying the transistor layer. The method includes planarizing the interlayer dielectric layer and forming a sacrificial layer (e.g., bottom antireflective coating, polymide, photoresist, polysilicon) overlying the planarized interlayer dielectric layer. The method includes forming a plurality of recessed regions within a portion of the interlayer dielectric layer through the sacrificial layer while other portions of the interlayer dielectric layer remain intact. Preferably, lithographic techniques are used for forming the recessed regions. The method includes forming an aluminum layer (or other reflective layer or multilayers) to fill the recessed regions and overlying remaining portions of the sacrificial layer and selectively removing the aluminum layer overlying portions of the sacrificial layer to form a plurality of electrode regions corresponding to each of the recessed regions. | 08-13-2009 |
| 20090155977 | Methods for Forming a Gate and a Shallow Trench Isolation Region and for Planarizating an Etched Surface of Silicon Substrate - There is provide a method for forming a gate, which can improve the etching uniformity of the sidewalls of the gate, including the following steps: forming a dielectric layer on a semiconductor substrate; forming a polysilicon layer on the dielectric layer; etching the polysilicon layer; performing an isotropic plasma etching process on the etched polysilicon layer by using a mixed gases containing a fluorine-based gas and oxygen gas; and cleaning the semiconductor substrate subjected to the isotropic plasma etching process, thereby forming a gate. there are also provided a method for forming a shallow trench isolation region, which can improve the filling quality of a subsequent spacer and the electrical properties of the resultant shallow trench isolation region by improving the etching uniformity of sidewalls and bottom surface of the shallow trench, and a method for planarizating an etched surface of silicon substrate, which can improve the etching uniformity of the surface of silicon substrate. | 06-18-2009 |
| 20090152608 | DRAM Cell Transistor Device and Method - A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure. | 06-18-2009 |
| 20090152604 | System and method for sensing image on CMOS - A system and method for sensing image on CMOS. According to an embodiment, the present invention provide a CMOS image sensing pixel. The pixel includes an n-type substrate, which includes a first width and a first thickness. The pixel also includes a p-type epitaxy layer overlying the n-type substrate. The p-type epitaxy layer includes a second width and a second thickness. The second width is associated with one or more characteristics of a colored light. The pixel additionally includes an n-type layer overlying the p-type epitaxy layer. The n-type layer is associated with a third width and a third thickness. Additionally, the pixel includes an pn junction formed between the p-type epitaxy layer and the n-type layer. Moreover, the pixel includes a control circuit being coupled to the CMOS image sensing pixel. | 06-18-2009 |
| 20090152599 | Silicon Germanium and Polysilicon Gate Structure for Strained Silicon Transistors - An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others. | 06-18-2009 |
| 20090101898 | METHOD AND RESULTING STRUCTURE FOR FABRICATING TEST KEY STRUCTURES IN DRAM STRUCTURES - A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1. | 04-23-2009 |
| 20090085600 | Method and System for Derivation of Breakdown Voltage for MOS Integrated Circuit Devices - A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment. | 04-02-2009 |
| 20090075454 | Method and High Gapfill Capability for Semiconductor Devices - A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench. | 03-19-2009 |
| 20090072396 | Method of Forming Low Stress Multi-Layer Metallurgical Structures and High Reliable Lead Free Solder Termination Electrodes - Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed. The barrier layer prevents formation of an intermetallic compound in proximity to the first layer by precluding diffusion of tin from the termination electrode to the first layer. In a specific embodiment, the first layer includes stress release copper underneath a barrier layer which includes nickel. | 03-19-2009 |
| 20090066417 | High bandwidth apparatus and method for generating differential signals - An apparatus and method for generating differential signals. The apparatus includes a first operational amplifier receiving a first signal, a second operational amplifier receiving a second signal, and a first transistor. The first transistor includes a first gate, a first terminal, and a second terminal. Additionally, the apparatus includes a second transistor. The second transistor includes a second gate, a third terminal, and a fourth terminal. Moreover, the apparatus includes a first resistor coupled to the first terminal and the third terminal, and a second resistor coupled to the second terminal and the fourth terminal. Also, the apparatus includes a first current supplier coupled to the first terminal, a second current supplier coupled to the second terminal, a third current supplier coupled to the third terminal, and a fourth current supplier coupled to the fourth terminal. | 03-12-2009 |
| 20090065805 | Method and structure using a pure silicon dioxide hardmask for gate pattering for strained silicon MOS transistors - A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region. | 03-12-2009 |
| 20090042379 | Method for Fabricating Semiconductor Device Capable of Adjusting the Thickness of Gate Oxide Layer - The present invention provides a method for fabricating semiconductor device, which is capable of adjusting a gate oxide layer thickness, including: providing a semiconductor substrate; growing a first oxide layer on a surface of the semiconductor substrate; patterning the first oxide layer to expose the first oxide layer corresponding to a gate to be formed; removing the exposed first oxide layer; immersing the substrate into deionized water to grow a second oxide layer; forming a polysilicon layer on the surfaces of the first oxide layer and the second oxide layer; and etching the polysilicon layer to form a gate. The method for fabricating semiconductor device according to the present invention, which is capable of adjusting the thickness of gate oxide layer, can control the thickness of gate oxide layer precisely to satisfy the requirement for different threshold voltages. | 02-12-2009 |
| 20090042145 | Method for Detecting Light Intensity Distribution for Gradient Filter and Method for Improving Line Width Consistency - A method for detecting light intensity distribution for a gradient filter, including: providing a mask plate which has patterns with identical line widths; providing a semiconductor substrate with a photosensitive material layer, and transferring the patterns of the mask plate to the photosensitive material layer, to form patterns of the photosensitive material layer; measuring line widths of the patterns of the photosensitive material layer at different positions on the semiconductor substrate, to obtain line width distribution of the patterns of the photosensitive material layer; inputting the measured line width distribution of the patterns of the photosensitive material layer into a function of light intensity distribution for a gradient filter versus line width distribution, to obtain light intensity distribution for the gradient filter. The present invention further provides a method for improving line width consistency in a photolithography process. The methods of the present invention are relatively simple, time-saving and cost-reducing. | 02-12-2009 |
| 20090009209 | Multiple Point Gate Oxide Integrity Test Method and System for the Manufacture of Semiconductor Integrated Circuits - A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure. If the second measured leakage current is below the second predetermined amount, the device a good device. The method provides a way to monitor gate oxide integrity and/or process stability using extrinsic measurements according to a specific embodiment. The method includes determining a breakdown voltage associated with the second measured leakage value. In a preferred embodiment, the second measured leakage current is characterized as extrinsic information and the breakdown voltage is characterized as intrinsic information. | 01-08-2009 |
| 20080319721 | Method for Building MOS Transistor Model and Method for Verifying MOS Transistor Model - The present invention discloses a method for building an MOS transistor model enclosing statistical variation of noise, including: measuring noise in MOS transistors from different dies; creating a noise distribution diagram in accordance with the obtained noise data of the MOS transistors; adding a variation of noise parameter in at least one noise model file into a library file of MOS transistor to simulate noise in MOS transistors; if a simulation result does not cover the noise data in the noise distribution diagram, changing the variation of the noise parameter until the simulation result covers the noise data in the noise distribution diagram; if the simulation result covers the noise data in the noise distribution diagram, adding corresponding variation of the noise parameter into the library file of MOS transistor as the MOS transistor model enclosing statistical variation of noise. The model obtained by the present invention is more precise. | 12-25-2008 |
| 20080318382 | METHODS FOR FABRICATING TUNNELING OXIDE LAYER AND FLASH MEMORY DEVICE - A method for manufacturing a tunneling oxide layer including the following steps: forming a tunneling oxide layer on a semiconductor substrate by in-situ steam generation oxidation; performing a annealing on the tunneling oxide layer. There is also provided a method for manufacturing a flash memory device. According to the invention, the dangling bonds between silicon oxide in a tunneling oxide layer and silicon adjacent to a semiconductor substrate interface are terminated by performing a annealing on a tunneling oxide layer, thereby improving the erase rate of the tunneling oxide layer. | 12-25-2008 |
| 20080315295 | Atomic Layer Deposition Method and Semiconductor Device Formed by the Same - Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases. | 12-25-2008 |
| 20080315293 | Atomic Layer Deposition Method and Semiconductor Device Formed by the Same - There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method. | 12-25-2008 |
| 20080315292 | Atomic Layer Deposition Method and Semiconductor Device Formed by the Same - There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method. | 12-25-2008 |
| 20080314418 | Method and System for Furnace Cleaning - The present invention provides a method and a system for cleaning furnace, including the steps of introducing a nitrogen gas flow into a cleaning agent tank to carry the cleaning agent, introducing the nitrogen gas carrying the cleaning agent into the furnace via a pipeline to clean the furnace; and generating a steam by mixing and igniting a hydrogen gas flow and an oxygen gas flow, and then introducing the steam into the furnace to clean the furnace. The method for cleaning furnace according to the invention can effectively remove metal and non-metal impurities deposits in a furnace of semiconductor oxidation furnace equipment. | 12-25-2008 |
| 20080311757 | SYSTEM AND METHOD FOR CHEMICAL DRY ETCHING SYSTEM - A system and method for chemical dry etching system. The present invention provides a method for performing an etching process for manufacture of integrated circuits. The method includes providing a semiconductor wafer. The method also includes the step of maintaining the semiconductor wafer in a predetermined environment. The method includes subjecting a portion of the layer to a plasma environment. The plasma environment includes one or more plasma species. For example, the plasma species are used to perform etching. The method also includes monitoring a pressure condition within a first transport device using a sensing device. The sensing device is spatially configured between a valve and a pumping device. The valve is coupled to a second exhaust coupled to the plasma chamber. The method additionally includes determining if the pressure condition within the first exhaust is within a predetermined condition. The method includes removing the one or more plasma species through the first exhaust, through the valve, and through the second exhaust if the pressure condition within the first exhaust is within the predetermined condition. | 12-18-2008 |
| 20080292743 | SHAPING DIE FOR CHIP PACKAGE LEADS - Disclosed herein is a shaping die for chip package leads including a base portion, on which lead pressing portions are provided, the lead pressing portions having contact portions contacting with TSOP package leads, a groove for holding the TSOP package being formed between the lead pressing portions, wherein the depth of the groove, which is the minimum distance between a location of the groove where the TSOP package is held and the contact portions of the lead pressing portions, corresponds to the maximum distance between the leads and the surface of the TSOP package held by the groove. The flatness of the shaped leads in the invention is improved and the package will not be damaged during the shaping procedure. | 11-27-2008 |
| 20080290901 | Voltage Shifter Circuit - The present invention provides a voltage shifter circuit, in which a control circuit is used to control the pull-up circuit, so that the pull-up circuit is kept as off when the signal from the input signal source changes from a low voltage to a high voltage. Hence, the competition between the pull-up circuit and the pull-down circuit is avoided. The speed of the voltage shifter circuit is improved and the voltage shifter circuit can operate within a wider voltage range. The delay time of the pull-up circuit and the pull-down circuit is small and the duty cycle is small. In addition, since no direct current path is established, no current is wasted. Additionally, the voltage shifter circuit uses the second delayer to compensate the delay time between the pull-up circuit and the pull-down circuit and optimizes the duty cycle. | 11-27-2008 |
| 20080274609 | Method and structure for low-K interlayer dielectric layer - An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first interlayer dielectric layer. A contact structure including metallization is within the first interlayer dielectric layer and a metal layer is coupled to the contact structure. A passivation layer is formed overlying the metal layer. Preferably, an air gap layer is coupled between the passivation layer and the metal layer, the air gap layer allowing a portion of the metal layer to be free standing. Depending upon the embodiment, a portion of the air gap layer may be filled with silicon bearing nanoparticles, which may be oxidized at low temperatures. This oxidized layer provides mechanical support and low k dielectric characteristics. Preferably, a portion of the air gap layer is filled with a low k dielectric material as well. | 11-06-2008 |
| 20080270662 | SYSTEM AND METHOD FOR PROVIDING LIVE INSERTION - System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal. | 10-30-2008 |
| 20080266917 | DC/DC CONVERTING SYSTEM - A DC/DC converting system, comprising: a DC/DC converter adapted to convert an input voltage to a second output voltage; and a charge pump adapted to provide an operation voltage to the DC/DC converter. According to embodiments of the present invention, a DC/DC converter having a large operation voltage range can be implemented by connecting a charge pump with a DC/DC converter and using the first output voltage of the charge pump as the operation voltage of the DC/DC converter. Moreover, by connecting at least one back-to-back diode switch between the power supply terminal and the first output terminal of the first DC/DC converting circuit of the charge pump, a first output voltage may be output stably as the operation voltage of the DC/DC converter when different input voltages are input to the power supply terminal. | 10-30-2008 |
| 20080265949 | CMOS DRIVING CIRCUIT - A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a voltage converting circuit in a multi-voltage system as one DC input voltage. The driving load capacity of the CMOS driving circuit is improved by converting the higher of the two DC input voltages to a modulated driving voltage and outputting it via an output terminal, so that the on-resistance of a power transistor connected with the output buffer stage is lowered, the power consumption of the power transistor is reduced, the output capacity is improved, and the area of the power transistor is lowered with the same output power. | 10-30-2008 |
| 20080264901 | Chemical Mechanical Polishing Process for Planarizing Copper Surface - Disclosed is a chemical mechanical polishing planarization method for copper surface, including the following steps: depositing a dielectric layer on the copper surface, and polishing the copper surface having the dielectric layer thereon. The method for planarizing a copper surface by chemical mechanical polishing process according to the present invention can achieve the planarization of the surfaces of both the copper and the dielectric layer, so as to avoid the occurrence of the dishing phenomenon. | 10-30-2008 |
| 20080261397 | Method for Manufacturing Semiconductor Device - There is provided a method for manufacturing a semiconductor device, which includes the steps of: providing a semiconductor substrate including a gate, a source and a drain, wherein the gate includes a gate dielectric layer disposed on the semiconductor substrate; forming an etching barrier layer on the semiconductor substrate; and subjecting the resulted structure to hydrogen annealing. According to the present invention, the interface energy level between a gate dielectric layer and a semiconductor substrate is lowered and the reliability of the semiconductor device is improved. | 10-23-2008 |
| 20080252868 | MASK-LESS METHOD AND STRUCTURE FOR PATTERNING PHOTOSENSITIVE MATERIAL USING OPTICAL FIBERS - A method for patterning objects, e.g., semiconductor wafer, glass plate, composite, etc. The method includes providing an object, which has an overlying layer of photosensitive material. The method includes selectively applying light through one or more fiber cores from a plurality of fiber cores. Each of the fiber cores has an input end and an output end. Each of the input ends is coupled to the optical source. The plurality of fiber cores is numbered from 1 through N, where N is an integer greater than 1. Each of the output ends is also numbered from 1 through N, which corresponds respectively to each of the plurality of fiber cores numbered from 1 through N. The method exposes the photosensitive material from light emitted selectively through the one or more fiber cores. The one or more fiber cores out(s) light respectively through one or more output ends of the fiber cores. Each of the output ends numbered from 1 through N is associated with a pixel numbered respectively from 1 through N. | 10-16-2008 |
| 20080238381 | Device and Method for Voltage Regulator with Stable and Fast Response and Low Standby Current - An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third transistor coupled to the second transistor and configured to receive a first voltage from the second transistor, and a fourth transistor configured to receive the first voltage from the second transistor and generate an output voltage. Moreover, the apparatus includes an adaptive system coupled to the fourth transistor. Also, the apparatus includes a delay system coupled to the third transistor and configured to receive a sensing current from the third transistor and generate a delayed current associated with a predetermined time delay. Additionally, the apparatus includes a current generation system. | 10-02-2008 |
| 20080233692 | Method and System for Forming a Controllable Gate Oxide - Method and system for forming gate structure with controllable oxide. The method includes a step for providing a semiconductor substrate and defining a source region and a drain region within the semiconductor substrate. Furthermore, the method includes a step for defining a gate region positioned between the source region and the drain region. Moreover, the method provides a step for forming a first layer overlaying the gate region. The first layer includes silicon nitride and/or silicon oxynitride material. Also, the method includes a step for forming a second layer by subjecting the semiconductor substrate to at least oxygen at a predetermined temperature range for a period of time. The second layer has a thickness less than 20 Angstroms. | 09-25-2008 |
| 20080230843 | Isolation Structure for MOS Transistor and Method for Forming the Same - A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively. | 09-25-2008 |
