| SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC Patent applications |
| Patent application number | Title | Published |
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| 20120126324 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N− type semiconductor layer. A source layer including an N− type layer is disposed in a surface portion of the body layer. An N− type drift layer is formed in a surface portion of the N− type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region. | 05-24-2012 |
| 20120112278 | ELECTRONIC DEVICE INCLUDING A WELL REGION - An electronic device including an integrated circuit can include a buried conductive region and a semiconductor layer overlying the buried conductive region, and a vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The integrated circuit can further include a doped structure having an opposite conductivity type as compared to the buried conductive region, lying closer to an opposing surface than to a primary surface of the semiconductor layer, and being electrically connected to the buried conductive region. The integrated circuit can also include a well region that includes a portion of the semiconductor layer, wherein the portion overlies the doped structure and has a lower dopant concentration as compared to the doped structure. In other embodiment, the doped structure can be spaced apart from the buried conductive region. | 05-10-2012 |
| 20110300679 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor portion overlying the underlying doped region, wherein the semiconductor portion has a primary surface spaced apart from the underlying doped region. The process can further include forming a vertically-oriented conductive region extending from the primary surface towards the underlying doped region, forming a horizontally-oriented doped region adjacent to the primary surface, and forming a conductive electrode over, spaced-apart from, and electrically insulated from the vertically-oriented doped region. The process can still further include forming a gate electrode after forming the conductive electrode. The electronic device can include a transistor that includes the underlying doped region, the vertically-oriented conductive region, the horizontally-oriented doped region, and the gate electrode. | 12-08-2011 |
| 20110206344 | METHOD AND APPARATUS FOR PROVIDING A SYNCHRONIZED VIDEO PRESENTATION WITHOUT VIDEO TEARING - The present invention provides a method and apparatus for feeding a video stream from a video source in a manner that prevents video tearing. | 08-25-2011 |
| 20110156141 | TRANSISTOR AND METHOD THEREOF - An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions. | 06-30-2011 |
| 20110057709 | PADE' APPROXIMANT BASED COMPENSATION FOR INTEGRATED SENSOR MODULES AND THE LIKE - Methods and systems using Pade' Approximant expansion ratios provide mappings between nonlinear sensors and a more linear output domain. The method includes a method of converting an input digital signal having a nonlinear dependency on a physical variable into an output digital signal that exhibits a substantially linear dependency with respect to the variable is disclosed. The method includes: (a) multiplying the input digital signal by a variable multiplying factor to thereby generate a multiplied digital version of the input signal; (b) adding to the multiplied digital version of the input signal, a predefined digital offset signal to thereby produce the output digital signal; (c) multiplying the output digital signal by a predefined feedback gain correction factor to thereby produce a digital feedback signal; (d) using the digital feedback signal to produce the variable multiplying factor. | 03-10-2011 |
| 20100156512 | CHARGE PUMP CONTROLLER AND METHOD THEREFOR - In one embodiment, a charge pump controller is configured to a charge pump controller to charge a plurality of pump capacitors during a charging time interval and to sequentially form a plurality of discharge time intervals with a different pump capacitor coupled to supply a current to a load for each discharge time interval. | 06-24-2010 |
| 20100000772 | ELECTRONIC PACKAGE HAVING DOWN-SET LEADS AND METHOD - In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly. | 01-07-2010 |
| 20090273868 | TRANSIENT VOLTAGE SUPPRESSOR AND METHOD - A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event. | 11-05-2009 |
| 20090267673 | SIGNAL GENERATION CIRCUIT - A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design. | 10-29-2009 |
| 20090189573 | METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR - A voltage regulator having an overload protection circuit and a method for protecting against an output voltage being less than a predetermined level. The voltage regulator has an overload protection circuit coupled between a feedback network and a regulation section. A power factor correction circuit is connected to the regulation section. An output voltage from the power factor correction circuit is fed back to the feedback network, which transmits a portion of the output voltage to the overload protection circuit. If the output voltage is less than the predetermined voltage level, a transconductance amplifier generates a current that sets an overload flag. Setting the overload flag initiates a delay timer. If the delay exceeds a predetermined amount of time, the overload protection circuit shuts down the voltage regulator. | 07-30-2009 |
| 20090075601 | LOW-IF TRANSCEIVER ARCHITECTURE - A transceiver, receiver, and transmitter are provided. The transmitter includes an in-phase path and a quadrature path, a first path associated with a first local frequency and a second path associated with a second local frequency, and a band selector for swapping the in-phase and quadrature paths to switch connection between the in-phase and quadrature paths and the first and second paths. The receiver includes an in-phase path and a quadrature path, a polyphase filter having first and second inputs and first and second outputs, and a selector for swapping the in-phase and quadrature paths to switch connection between the in-phase and quadrature paths and the first and second inputs. The transceiver may include a receiver and a transmitter, each of the receiver and the transmitter including in-phase signal and quadrature signal paths and first and second paths for processing signals on the in-phase signal and quadrature signal paths. In the transceiver, each of he receiver and the transmitter may include a band selector for selecting a band by swapping in-phase signal and quadrature signal paths. The transceiver may include a receiver, a transmitter, and a programmable matching block for impedance-matching between an antenna and the receiver input and between the antenna and the transmitter output. The receiver may include an in-phase path and a quadrature path, and a module provided for the in-phase path and the quadrature path for enhancing image rejection. The module includes a polyphase filter having first and second inputs and first and second outputs, and an adder for adding the first and second outputs. | 03-19-2009 |
| 20090066403 | EMC PROTECTION CIRCUIT - A protection circuit for protecting an electronic circuit against EMC disturbances and/or negative transient overvoltage pulses comprises a switch in series between a power supply and the electronic circuit to be protected; a comparator for comparing a first operating parameter with a second operating parameter and producing a comparison signal, the comparison signal being used as a control signal for controlling opening and closing of the switch; and a delay circuit adapted for delaying closing of the switch. A corresponding method is also provided. | 03-12-2009 |
| 20090015225 | METHOD FOR REGULATING A VOLTAGE AND CIRCUIT THEREFOR - A voltage regulator ( | 01-15-2009 |
| 20080303487 | Battery Protection Method and Structure Therefor - In one embodiment, a circuit is formed to couple a battery to a charging voltage at least a portion of a time when the charging voltage is greater than zero volts and is less than a first voltage value. The circuit is also formed to decouple the battery from the charging voltage approximately when the charging voltage is greater than the first voltage and also approximately when the charging voltage is no greater than zero volts. | 12-11-2008 |
| 20080246450 | Soft-Start Circuit and Method Therefor - In one embodiment, a soft-start circuit is configured to form drive pulses that increase in width independently of the current through the power switch during a first portion of the soft-start operation period. | 10-09-2008 |
| 20080246130 | Semiconductor Package Structure Having Enhanced Thermal Dissipation Characteristics - In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed. | 10-09-2008 |
